JPH1083692A - Control gate driver circuit for non-volatile memory and memory using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a control gate driver circuit which operates in a wide range of voltage and furthermore minimizes the area of integrated circuit. SOLUTION: The control gate driver circuit 900 supplies a variety of voltages to the gate of a floating-gate non-volatile memory cell 10 using a single circuit. At the time of readout, a bias circuit 920 and a reference transistor 925 biases the gate of a pass transistor 936 connected to the output of a level shifter 910 so that the transistor 936 may become slightly conducting without using a charge pump. At the time of programming, a pulse circuit 940 gradually raises the program voltage being supplied to the cell accompanying the selector row and allows smaller transistors 932, 934 and a smaller capacitance of the charge pump to use. The cell of the non-selection row is driven at a different voltage, reduces the junction leakage and maintains a high disturbance voltage against the cell of the non-selection row.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a control circuit for a nonvolatile memory, and more particularly to a control circuit for a nonvolatile memory for supplying positive and negative voltages to a control gate of a memory cell.

[0002]

2. Description of the Related Art An electrically erasable and programmable read only memory (EEPROM) is a non-volatile memory device that is erased and programmed using electrical signals. EEPROM devices typically include thousands of memory cells, each of which can be individually programmed and erased. Generally, an EEPROM cell includes a floating gate transistor and a selection transistor. E
Selection transistors in EPROM devices are used to select individual EEPROM cells to be erased or programmed. The floating gate transistor of the device is the transistor that actually stores the digital value of each particular memory cell.

To program and erase cells, the Fowler-Nordheim tunnel effect (Fowl)
A phenomenon known as er Nordheim tunneling is commonly used to store positive or negative charge on the floating gate electrode of the floating gate transistor. For example, programming is accomplished by applying a positive voltage to the drain and gate of the select gate transistor, while maintaining the control gate of the floating gate transistor at ground. As a result, electrons tunnel from the floating gate of the floating gate transistor to the drain through the tunnel dielectric, leaving the floating gate in a positively charged state.

[0004] One particular structure of an EEPROM is a flash EEPROM. Flash EEPROMs provide electrical erasing and programming capabilities and generally have large circuit densities. This large circuit density typically comes at the cost of only being able to block erase a flash EEPROM array. Typically,
The array is erased in a single step or in flash, which is why it is called a flash EEPROM.

[0005] Charge pumps are commonly used to generate the high voltages required to program and erase flash EEPROMs. The use of charge pumps in applications requiring low power supply voltages has become important, as applications with lower operating voltages are becoming more prevalent. However, as operating voltages decrease, charge pumps that can operate at these voltages become more difficult to design. Currently, flash EEPROMs operate up to voltages of approximately 2.7 volts. Flash EEPROMs operating at voltages below 2.7 volts are highly desirable, but are not currently commercially available. Prior art charge pumps typically use a linear charge pump stage to generate high voltages. Linear charge pumps typically include a number of circuit stages, each of which can charge a previously generated or available voltage by an amount limited to approximately the voltage of the positive power supply conductor (Vdd). For example, if three such charge pump stages are used, and if Vdd is 3 volts, then if no load is applied, a total output voltage of four times Vdd will be the total output voltage. Will. The disadvantage of using linear charge pumps is that their area or area efficiency is relatively low. This area efficiency is defined as the total space required to configure the charge pump as compared to the amount of current available at the voltage generated by the configured charge pump. Therefore, there is a need for a technically large area efficient charge pump.

[0006]

Since the erase and program states of a cell are determined by applying a large voltage to the control gate, it becomes difficult to design a driver circuit that can operate with such a range of voltages. . For example, as integrated circuit geometries decrease, higher voltages applied between the gate and source or drain of the transistor itself in the drive circuit are causing reliability problems. Furthermore, the need to apply various high voltages makes it difficult to implement with a small amount of circuit area. Integrated circuit EEPROM devices are traditionally implemented with complementary metal oxide semiconductor (CMOS) technology. When using CMOS technology, a transistor of a given conductivity type is typically formed in a substrate, and if a transistor of the opposite conductivity type is desired, a region known as a well or tub is formed in the substrate and The transistor must then be formed in the well or tub. However, exposure to these very high voltages can cause breakdown of the parasitic diode between the well and the substrate. Exposure to a negative voltage will cause the parasitic diode to become forward biased.

For example, if an integrated circuit EEPROM is formed on a P-type substrate, a normal N-channel transistor can be formed directly on the substrate, while a P-channel transistor requires an N-type well. However, if an N-channel transistor is formed directly on the substrate, exposure to a negative program or erase voltage will cause the parasitic PN diode to become forward biased. Therefore, the N-channel transistor needs to be further arranged in the P well within the N well. These well structures increase integrated circuit area and are generally undesirable. Therefore, there is a need to provide a control gate driver circuit that can accommodate a wide variety of voltages but can do so with a minimum circuit area.

[0008]

According to the present invention, a control circuit receives an erase voltage, a positive program voltage, and a negative program power supply. The control circuit generates a bias voltage via the bias circuit. During a program cycle to the selected memory cell, negative program power is supplied to the control gate line. During a program cycle to unselected memory cells, a positive program voltage is provided to the control gate line. During an erase cycle for the selected memory cell, the erase voltage is supplied to the control gate line. During a read cycle, the bias voltage is provided to a control gate line.

The present invention is directed to a drain disturbance or drain disturbance problem for a non-volatile memory array.
isturb probe and band-to-band leakage
e) providing a method for improving To address these problems, known devices have modified the layout of the memory array or adjusted the structure of each memory cell in the array. However, the present invention modifies how the memory array operates rather than modifying the physical design of the memory array.

Since only the operation of the non-volatile memory array is changed, it is not necessary to make expensive changes to the layout of the memory array or the design of the individual memory cell structure. The present invention is not limited to a particular EEPROM cell structure, as it does not involve changes to the memory array. This allows the programming and reading techniques of the present invention to be used with a variety of non-volatile memory array structures.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a detailed description will be given of a method for programming a nonvolatile memory array according to the present invention. FIG. 1 shows a memory array 25 consisting of individual memory cells each having an isolation transistor and a floating gate transistor. FIG. 1 is provided to provide a schematic representation of a non-volatile memory array and it should be understood that the invention is not limited to this structure itself or the number of memory cells in memory array 25. One of the many features of the present invention is that the following operating techniques are compatible with memory arrays of various sizes and structures.

In this particular example, memory array 25 has 2
It is configured to have one row or row of memory cells, each row having four cells. The dotted boxes are used to identify the elements of two specific memory cells in memory array 25. For the following description, memory array 25 includes selected memory cells 10 and unselected memory cells 30. Selected memory cells 10 refer to memory cells that are being programmed, erased or read, and unselected memory cells 30 are nearby memory arrays 25 that are not enabled and may be affected by the drain disturbance phenomenon. Cell.

Each memory cell in memory array 25 is enabled by a control gate line, an isolation gate line, a source line, and a drain line. All of these signal lines provide the necessary potential to the appropriate portions of each memory cell during operation of the memory array 25. As previously mentioned, embodiments of the present invention are not limited to certain memory cell structures. However, certain memory cell structures are provided as examples of memory cells that can be used in memory array 25 for clarity. FIG. 2 is an enlarged cross-sectional view of a memory cell 10 that can be used to configure the location of each memory cell.

As shown in FIG. 2, the memory cell 10 has two transistors, an isolation transistor 2
2 and a floating gate transistor 23. The structure and fabrication of the memory cell 10 is described in U.S. Patent No. 5,471,422 issued to Chang et al. On November 28, 1995 and is incorporated herein by reference. Isolation transistor 22 has a gate terminal 19 used to modulate the channel between source terminal 12 and drain terminal 13. Floating gate transistor 23 has a gate terminal 21 electrically insulated from floating gate structure 18 by dielectric material 17, and gate terminal 21 for modulating the channel between source terminal 13 and drain terminal 14. Used as control gate. Note that the drain terminal 13 of the isolation transistor 22 also acts as the source terminal 13 of the floating gate transistor 23. Both transistors 22 and 23 are formed on a common dielectric layer 16, which provides electrical isolation between substrate 11 and gate terminal 19 and floating gate structure 18.

[0015] Conventionally known non-volatile memory arrays typically include memory cells formed from a single floating gate transistor that stores the logic state of each memory cell. Such memory arrays are generally configured such that the drain voltage for all transistors in a particular column is shared and thus the gate voltage is shared by all transistors in a common row. To program individual memory cells,
A negative voltage is applied to the gate terminal, the source line is grounded, and a positive voltage is applied to the drain line. In an array structure, only the selected floating gate transistor has both a negative voltage on the gate and a positive voltage on the drain, creating a large voltage difference to facilitate programming. However, it is well known that other floating gate transistors in the same column as the memory cell being programmed also have a positive voltage on their drains. These unselected memory cells, however, have no negative voltage applied to their gate terminals. Therefore, they will not have the same magnitude of voltage difference as the memory cell being programmed, but will still have a voltage difference large enough to induce the drain disturbance problem.

The programming technique of the present invention addresses this shortcoming of previously known memory arrays by reducing the voltage difference present in all unselected memory cells. Returning to FIG. 1 for the following description, the selected memory cells 10 are programmed while the unselected memory cells 30 are undisturbed. Most signal lines are deliberately identified by the same element numbers of the structures used in FIG. 2, since they are used to provide potential to these structures. To program the selected memory cell 10 in accordance with the present invention, between about -5 volts and -15 volts.
A negative voltage, in volts, is applied to gate terminal 21 by control gate line 21. The drain line 14 is used to apply a positive voltage, about 0.1 volt to 10 volts, to the drain terminal 14 of the floating gate transistor 23.
Is applied. Isolation gate line 19 is typically grounded, ie, 0 volts, or has a voltage low enough to turn off isolation transistor 22. Source line 12 shared by both selected memory cell 10 and unselected memory cell 30 has a potential of about -5 volts to 5 volts.

The present invention is now different from the prior art in that different voltages are applied to the terminals of the unselected memory cells 30 when the selected memory cells are programmed and verified. Instead of grounding the gate terminal of the unselected transistors, a voltage of about 0.1 volt to 10 volts is applied to the unselected memory cells 30 using the control gate line 32.
Is applied to The potential of the gate terminal 32 is
About 0.1 volts to 20 volts above, the drain disturbance problem in unselected memory cells 30 is greatly improved. Unlike the ground as in the prior art, a positive voltage is applied to the gate terminal of the unselected gate, so that the vertical electric field along the drain terminal of the unselected gate is greatly reduced.

It should also be pointed out that the programming technique of the present invention cannot be used with previously known memory arrays having a single floating gate transistor for each memory cell. Since these previously known memory cells do not have isolation transistors, a single floating gate transistor is exposed to all voltages present in the memory array. If a positive voltage is applied to the gate terminal of an unselected memory cell, that voltage will induce a channel between the source and drain of all floating gate transistors. This current not only consumes an enormous amount of power, but also causes unselected transistors to be programmed by hot carrier injection (HCI).

The programming technique of the present invention not only protects unselected memory cells from drain disturbance problems, but also reduces the amount of current flowing from the charge pump. By reducing the vertical electric field at the drain terminals of all unselected memory cells, the amount of current flowing from the substrate to the drain terminals is greatly reduced. This in turn reduces the amount of current required to be provided by the charge pump during the programming sequence. Thus, the present invention allows a non-volatile memory array to be designed using a small charge pump, which reduces the final manufacturing cost of the memory array.

The present invention also relates to a memory cell 10 once selected.
Provides an improved technique for reading the memory array 25 when is programmed. Selected memory cell 10
To read the value stored in
Five volts are applied to drain line 14 and control gate line 21. Power supply voltage Vdd is applied to isolation gate line 19, and source line 12 is grounded. Once the voltage is set, the current through the floating gate transistor 23 is measured or detected to determine the state of the memory cell 10.

Conventionally known read techniques generally ground the gate terminal of an unselected memory location during a read operation. Even at ground potential, there is some finite amount of leakage current through each memory cell. In large array structures, this parasitic leakage increases the power consumption of the read operation. However, the present invention provides a known voltage level to the gate terminals of the isolation transistors of the unselected memory cells to ensure that these memory cells do not conduct. For example, the isolation gate line 31 is grounded to prevent the unselected memory cells 30 from conducting. This not only reduces the amount of current required by the charge pump, but also reduces the power consumption of the memory array 25. This feature of the present invention allows the control gates of unselected memory locations to be at any potential. Unselected memory locations do not contribute to the leakage current because they are electrically isolated by isolation transistors.

FIG. 3 is provided to illustrate a particular set of states for both selected and unselected memory cells during program, erase, and read operations. While this particular example falls within the scope provided by the present invention, it should be noted that FIG. 3 should not be considered in any way limiting in determining the scope of the present invention.

FIG. 4 shows, in partial block diagram and partial plan view form, a memory module 400 according to the present invention. The memory module 400 generally comprises a control and predecode unit 410, low voltage word decode units 420 and 460, and high voltage word decode units 430 and 47.
0, high voltage predecode units 432 and 474, bit cell arrays 440 and 480, and a sense amplifier (amplifier) unit 450. The control and pre-decode unit 410 reads “address / control (ADDRESS / CONT)
ROL), an input for receiving address and control information, a bidirectional terminal for leading a signal labeled "DATA", and low voltage word decode units 420 and 460, high voltage predecode. Part 4
32 and 472, and an output connected to the sense amplifier unit 450. Low voltage word decode sections 420 and 460 have outputs connected to bit cell arrays 440 and 480, respectively, and provide signals to select gates of transistors in bit cell arrays 440 and 480. High voltage predecode units 432 and 472 have outputs connected to high voltage word decode unit 430 and high voltage word decode unit 470, respectively. High voltage word decode section 430 and high voltage word decode section 470 are provided for bit cell arrays 440 and 4
80.

The memory module 400 has a left half (le
A flash EEPROM memory array having an ft half bit cell array 440 and a right half bit cell array 480. Each bit cell array includes memory cells located at the intersection of rows, represented by control and select gate lines, and columns, represented by bit lines, respectively. The bit lines are connected to corresponding inputs of a sense amplifier unit 450 for selecting eight columns. During the read mode, the sense amplifier unit 450
Detects signals from the eight selected bit lines and controls the detected signals from the control and predecode unit 410.
, And the control and pre-decoding unit 410 outputs “data” in response. During the program mode, "data" is input to the sense amplifier section 450 via the control and predecode section 410 and is driven to eight selected bit lines for programming into corresponding memory cells. FIG. 4 shows two representative memory cells 10 and 30, which are identical to the memory cells of FIG. 1 and are therefore given the same reference numerals. “Select gate” and “isolation gate”
Note that “gate)” is used interchangeably in this description. The drain terminal 14 and the drain terminal of another memory cell located in the same column are connected to a bit line connected to the sense amplifier unit 450. “IBIT” related to the read cycle
There is a bit cell current, which is conveniently labeled in the direction flowing to the selected memory cell, and is useful in understanding the operation of the following read cycle more completely.

In the illustrated embodiment, memory module 400 is a module configured for connection to a microcontroller core as part of a microcontroller (not shown). However, it should be apparent that the memory module 400 can be similarly configured to accommodate a single chip flash memory. The control and predecode block 410 is configured to allow connection to the microcontroller's internal bus and has inputs for receiving addresses and control signals therefrom and bidirectional connections to the data portion of the microcontroller's internal bus. ing. “Data” can include any number of signals, depending on the configuration of the memory module 400, but in the illustrated embodiment includes eight data signals.

The control and predecode block 410 performs several functions. Control and predecode 410
Includes various registers to enable different operations of the memory module 400. Such operations include, but are not limited to, charge pump enable, write enable, and erase enable. In addition, the control and predecode block 410 includes logic that receives "address / control" and performs some of the decoding functions required to fully decode the address. The control and predecode block 410 also includes switching functions for routing various power signals, including the voltages associated with the charge pump 1120 shown later in FIG. Depending on the read or program cycle,
Control and predecode block 410 provides the predecoded address to low voltage word decode blocks 420 and 460 for further decoding. Additional decoding is further performed to allow a fully decoded select gate drive signal to be output therefrom.

Further, the low voltage word decode block 4
20 and 460 are bit cell arrays 440 and 48
The predecoded signal spanning zero is provided to high voltage word decode blocks 430 and 470. For example,
FIG. 4 shows a pre-decode signal (PREDECODED S).
IGNAL), which is provided by the low voltage word decode unit 420 to the high voltage word decode unit 430 across the bit cell array 440. By splitting the low and high voltage decoders between the two ends of the array and transmitting the predecoded signals on signal lines that fit within the available pitch of the memory cells in the array, Memory 4
00 reduces the circuit area required for decoding.

The high voltage predecode blocks 432 and 472 are respectively high voltage word decode blocks 430
And provide a high voltage signal for use at 470. High voltage predecode blocks 432 and 472
Receive three input power supply voltages, including +5 volts, +15 volts, and -12 volts, and also receive part of the address and various control signals. High voltage predecode blocks 432 and 472 provide high voltage predecode address signals to high voltage word decode blocks 430 and 470, respectively. High voltage word decode blocks 430 and 470 receive predecoded signals from both low voltage word decode blocks 420 and 460 and high voltage predecode blocks 432 and 472, and drive transistor control gates on selected rows accordingly. I do. The control gate is driven to the appropriate voltage as described above with respect to FIG.

Each of bit cell arrays 440 and 480 includes an individual bit cell located at a unique intersection of a word line and a bit line in each half of memory module 400. For example, bit cell arrays 440 and 480 are each organized into 256 word lines × 512 bit lines. Note that a unique control and select gate signal is used for each word line. Each of the 512 bit lines provides a bit line signal to the sense amplifier unit 450. Within bit cell array 440, a representative pair of bit cells corresponding to memory cells 10 and 30 of FIG. 1 are shown, and are therefore indicated by the same reference numerals.

The sense amplifier section 450 includes 64 sense amplifiers and has a bidirectional connection to the control and predecode section 410. Each of the 64 sense amplifiers is connected to eight bit lines, and based on the decode information from the predecode unit 410, during the read mode, 8: 1.
Multiplex function. 1 to 8 during program or erase mode
Note that the de-multiplex function is performed. The eight multiplexed outputs from the 64 sense amplifiers are further selected to provide an 8-bit output. According to one aspect of the invention, a portion of the sense amplifier is further used to store data during a program cycle, saving integrated circuit area as described in more detail below with reference to FIG. .

During a read cycle, control and predecode block 410 receives an input address and control signals specifying a read cycle. During this cycle, the control and predecode block 410 should have one byte of memory cells selected in the left half array or in the right half array such that only array 440 or array 480 is active. Decide what to do. During a read cycle, the control gates of all memory cells are held at a constant voltage level. In the illustrated embodiment, the constant level is equal to a small additional voltage equal to the P-channel threshold plus approximately 200 millivolts represented by "V _SS" named supply voltage plus "V _TP". V _SS is a negative or ground power supply voltage terminal from having approximately zero volts nominal. For unselected memory cells, the isolation gate remains at 0 volts, while for selected memory cells, the isolation gate is driven to the value of the power supply voltage terminal labeled "V _DD ". Although _VDD is a more positive supply voltage terminal having a nominal value of 2.7 volts, its actual value can be reduced to approximately 1.8 volts in accordance with the present invention. These voltages select one word line of the bit cell array. For example, if the word line where the memory cell 10 is located is to be selected, select gate 1
"SG1" is driven to a voltage of _VDD and control gate 1 "CG1" is held at a constant level. as a result,
The conductance of the memory cell 10 acts to discharge the bit line 14. However, the memory cell 30
Is kept at a constant (DC) level,
The isolation gate will be driven to approximately 0 volts.

During a program cycle, also known as a write cycle, control and predecode block 410 receives an address and control signal indicating that a write cycle is in progress and reads the decoded address signal in a read cycle. Provide as well. However, during the write cycle, the data flow is reversed. The sense amplifier in sense amplifier section 450 performs an additional function by latching input data and driving the input data to a selected bit line. During a write cycle, the memory cells on the selected word line have their isolation gates driven to 0 volts and their control gates driven to -12 volts by high voltage word decode block 430 or 470. However, memory cells on unselected word lines have their isolation gates driven to 0 volts and their control gates driven to 3.5 volts. The 3.5 volt voltage is obtained by reducing the 5 volt charge pump voltage by an amount equal to the N-channel transistor threshold "V _TN " of a properly sized N-channel transistor. During a read cycle, the voltage on the isolation gate determines whether the memory cell 10 is on the active word line, while in the program mode, the voltage on the control gate is on the word line when the cell 10 is active. Determine if there is.

During an erase cycle, a selected word line, a word line of a selected block, or the entire bit cell array can be erased. Note that the choice of options for erasure will vary from embodiment to embodiment. During an erase cycle, the voltage driven on the control gate determines whether the memory cells on the selected word line are erased. The memory cells of the selected word line have their control gates driven to 15 volts by a high voltage word decode block 430 or 470 for a sufficient amount of time. Note that the 15 volts applied to the control gates of the memory cells of the selected word line must be maintained for approximately 50 milliseconds. In a memory module 400 configured for use with a microcontroller core, the 50 ms is determined by the microcontroller core, which must ensure that the memory module 400 is not accessed until such time has elapsed. Must. However, if the memory module 400 is implemented as a stand-alone or stand-alone memory, it preferably includes an on-chip timer to measure the elapsed time during the erase mode. During the erase mode, the isolation gate of the selected word line is driven to a voltage of _VDD . Also during erase mode, all bit lines are held at zero volts. Keeping the isolation gate at a value of V _DD allows tunneling to occur more uniformly across the channel and can improve reliability.

FIG. 5 illustrates, in partial block diagram, partial logic diagram, and partial circuit diagram formats, the decode and sense amplifier portion (sense amplifier) 500 of the memory module 400 of FIG. The sense amplifier 500 represents any of the sense amplifiers SA1 to SAN shown in FIG. Sense amplifier 500 includes decode logic units 510 and 52
0, P-type MOS transistors 542, 544, 562,
564, inverters 546 and 566, current source 54
8,550,568 and 570, and the voltage comparator 5
30. The decoding logic unit 510 includes the transistor 51
2 and 513, a selection circuit 515, and a plurality of N-type MOS transistors including a threshold voltage generator 511. Transistor 512 has a gate, a first current electrode receiving one of the plurality of bit lines from bit cell array 440, and a second current electrode. Transistor 513 has a gate, a first current electrode receiving one of the plurality of bit lines from bit cell array 440, and a second current electrode.
Current electrodes. The selection circuit 515 includes the transmission gate 51
8 and 517. The transmission gate 518 includes a positive and negative control electrode connected to the control and decode unit 410, a first current electrode connected to the second current electrode of the transistor 513, and "I
Having a second current electrode connected to a node 513 labeled NA ". Transmission gate 517 includes a positive and negative control electrode connected to said control and decode unit 410;
A first terminal connected to a second current electrode of the transistor 512
And a second current electrode connected to the node INA 531.

The decode logic 520 includes a transistor 522
And 523, a selection circuit 525, and a plurality of N-type MOS transistors including a threshold voltage generator 521. The transistor 522 has a gate and a bit cell array 4
A first current electrode receiving one of the plurality of bit lines from 80, and a second current electrode. Transistor 5
23 has a gate, a first current electrode receiving one of the plurality of bit lines from the bit cell array 480, and a second current electrode. The selection circuit 525 includes a transmission gate 528.
And 527 including a plurality of transmission gates. The transmission gate 528 is a positive and negative control electrode connected to the control and decode unit 410, the second of the transistor 523.
A first current electrode connected to the current electrode of
B ″ has a second current electrode connected to node 532. Transmission gate 527 is connected to the positive and negative control electrodes connected to control and decode section 410, the second current electrode of transistor 522. It has a first current electrode connected to it and a second current electrode connected to node INB.

Transistor 542 has a gate, a source connected to _VDD , and a drain. Transistor 544 has a gate connected to node INA 531;
It has a source connected to the drain of the transistor 542 and a drain connected to the node INA. The inverter 546 is connected to the right array enable (RIGHTAR
RAY ENABLE) "584, and an output terminal connected to the gate of transistor 542. The current source 548 outputs a signal “LEFT ARRAY EN”.
ABLE) 580, a first current terminal connected to _VDD , and a second current terminal connected to node INA 531.
Current source 550 is an enable input terminal for receiving signal “Right Array Enable” 584, node INA 531
A first current terminal connected to, and a second current terminal connected to V _SS.

The P-type MOS transistor 562 has a gate,
It has a source connected to V _DD , and a drain.
P-type transistor 564 has a gate connected to node INB, a source connected to the drain of transistor 562, and a drain connected to terminal INB.
Inverter 566 has an input terminal for receiving "left array enable" 580, and a second output connected to the gate of transistor 562. Current source 568 has an enable signal terminal for receiving a signal labeled "Right Array Enable" 584, a first current terminal connected to _VDD , and a second current terminal connected to node INB. Current source 570 has an enable terminal for receiving a signal labeled "Left Array Enable" 580, a first current terminal connected to ground, and a second current terminal connected to node INB. The voltage comparator 530 indicates “Compare Enable (COMPARE
A control input terminal for receiving a signal labeled ENABLE) 582, a first input terminal connected to node INA, a second input terminal connected to node INB, and a "data output (DATA OUT)" 534. And an output terminal for providing a signal labeled.

The sense amplifier 500 is a sense amplifier 450
Represents a part of one sense amplifier. The elements shown in the sense amplifier 500 are the parts of the sense amplifier associated with the read mode.

In operation, during the beginning of a read cycle, the voltage levels on nodes 531 and 532 on either side of voltage comparator 530 are equalized to _VDD by circuitry not shown in FIG. By causing different discharge rates between the nodes INA 531 and INB 532, the sense amplifier 500
At 30 the appropriate stored data state in the bit cell is sensed and the signal "data out" 5
34 can be driven.

If node INA 531 is selected to receive information from bit cell array 440 and a non-conducting bit cell of array 440 is selected, node I
There is no discharge rate on NA531. As a result, node INA 531 maintains its precharge level of _VDD . However, node INB 5 has not been selected to receive information from bit cell array 480.
32 is allowed to discharge at a predetermined rate, and the voltage comparator is
532 allows a lower voltage to be detected. Based on this comparison, the voltage comparator 530 outputs the signal "data out"
534 is provided as a logic level high or logic level low signal specified by the system.

If node INA 531 is selected to receive information from bit cell array 440 and a conductive bit cell of array 440 is selected, node INA 531
The discharge rate (discharger) on 531
ate) occurs. The sense amplifier 500 is connected to the node INA.
The discharge rate at 531 is designed to be higher than the discharge rate on node INB 532. This difference in discharge rate is caused by the fact that the voltage comparator 530 determines whether the node INB 5
This allows a lower voltage to be detected on node INA 531 than on 32. As a result, when the non-conducting bit cell is read, voltage comparator 530 will detect a state that is complementary to what is read.

Node INB, which acts as a reference when data is being read from bit cell array 440,
The discharge rate of 532 is “left array enable” 580
Is controlled to a substantially fixed rate by current source 570, which is enabled when is asserted to indicate the beginning of a read cycle. Activation of the signal “Left Array Enable” 580 also enables the current source 548,
The current source 548 is connected to the node INA 531 when selected.
Current to charge at a given rate. The rate at which current source 548 supplies charge to node INA 531 is such that node INA 531 maintains a precharge voltage of _VDD when a non-conducting bit cell is selected in array 440. Further, the current source 5
The rate at which 48 provides charge to node INA 531 differs in amplitude from the discharge rate of current source 570, so that the discharge rate on node INA 531 is greater than the discharge rate on node INB 532 when a conduction bit is detected. To be. Thus, the charging rate of current source 548 is much lower than the discharging rate of current source 570.

The relationship between current sources 548 and 570 is such that voltage comparator 530 properly senses the conduction state of the bit cell when node INB 532 and / or node INA 531 is discharging. This relationship is important in that when operating at high operating frequencies or operating frequencies, the discharge occurs over a relatively short period of time. If the sense amplifier 500 is connected to the node 531 for a long time,
And 532 are completely discharged to zero volts, the conducting bit cell cannot be read, thereby preventing voltage comparator 530 from reading accurate data. To solve this problem, a sense amplifier 500
Is a diode-connected P-channel transistor 564
And a clamp circuit formed by enable P-channel transistor 562. Transistors 562 and 564 clamp node INB 532 to a pre-defined voltage, and
70 prevents node 532 from completely discharging.
As a result, in a low speed system, if nodes 531 and 532 have finished discharging, nodes INB 532
Maintain a higher voltage level than node INA 531, which voltage difference can be detected by voltage comparator 530. Conversely, if a non-conducting bit is being read, node INB 532 will be at a lower voltage than node INA 531.

In order to sense data as described above, it is necessary to convert the current sensed from the bit cells in array 440 to a voltage at node INA 531. The sense amplifier 500 accomplishes this sensing function in a manner that separates the current-to-voltage conversion function from the loading function and distributes them to different sides of the selection circuit 515 to allow operation at very low supply voltages. Sense amplifier 500 can reduce the amount of voltage drop detected in voltage comparator 530 by ensuring that the amount of voltage drop is optimized relative to the prior art, which had less current to produce the voltage drop. Operation.

The voltage conversion relationship between these components begins when transmission gate 517 is selected. Note that transmission gate 517 is one of the eight transmission lines in left bit decode block 519 controlled by decode logic to select one of the eight bit gates from bit cell array 440. Once selected, the sensed current from the selected bit line can flow through the N-channel transistor 512, the N-channel transistor 512 is an N-channel threshold 2 than V _SS by voltage reference 511
Biased one level higher. This allows N-channel transistor 512 to operate similarly to that of a common gate amplifier having a low input impedance and a relatively high output impedance. The low input impedance characteristic of transistor 512 causes the bit line side of transistor 512 to be quickly precharged at the beginning of a read cycle, while the high impedance output characteristic combined with the very high impedance characteristic of current source 548 provides a high impedance output characteristic to node INA 531. Enables high voltage gain across transistor 512.

As a result of the distribution of sense amplifier functions, transistor 512 in this embodiment provides a lower impedance to the bit line than provided by the prior art. The advantage of arranging the current-to-voltage converter in this manner is that a lower voltage drop is obtained across the transmission gate 517, resulting in less bit line charging time or a smaller pre-charging transistor. Yet another advantage of the present invention over the prior art is the fact that node INA 531 is charged to _VDD prior to the beginning of a read cycle. As a result, when the transmission gate 517 is selected, the P-channel gate-source voltage of the transmission gate 517 is the full power supply voltage _VDD . This allows the P-channel portion of voltage transmission gate 517 to be fully conductive. In the prior art, gate-source is limited to _VDD -bitline operating level, which provides gate drive very close to the threshold of the device. As a result, prior art transmission gates operate near the cutoff. The present invention ensures that node INA 531 can be completely discharged to ground during slow operation memory cycles. Without the N-channel portion of gate 517, this cannot occur.

Although the preceding description has focused on the reading operation from memory array portion 440, data is not
If read from 80, the circuit operates similarly and mirror-symmetrically.

FIG. 6 shows a timing diagram of various signals related to the read cycle of both conductive and non-conductive memory cells, which is useful in understanding the operation of sense amplifier 500 of FIG. The horizontal axis represents the time for each graph section.
The conducting bit read and the non-conducting bit read are each represented by three graph parts. The first graph part represents the voltage for vertical access, the second graph part represents the current, while the third graph part represents the output state of the comparator.

FIG. 6 illustrates the signal relationships described with respect to FIG. 5 for conducting bit reads and non-conducting bit reads. Although the relative values of the signals shown in FIG. 6 are useful in understanding the operation of memory module 400, it should be noted that they are not necessarily drawn to scale. As previously mentioned, during a conduction bit read, when data is read at node INA 531,
The voltage level of node INB 532 is
It is discharged at a different rate than the signal at 31 and is not completely discharged to ground. As a result, the voltage comparator 530
Nodes INA 531 and INB 53, which are distorted only by the internal voltage offset of comparator 530
The state of the selected memory cell can be read by detecting the voltage difference between the two.

Similarly, the graph 600 is “IBIT” 61
2, a representation of the memory cell current associated with the bit cells of array 440, a representation of the current through current sources 548 and 568, designated "S1" 614, and "S1".
Shown is a representation of the current through current sources 550 and 570, referred to as 1 "614. Similarly, graph information for unselected bit reads is also provided in graph 600.

FIG. 7 shows, in block diagram form, a programming driver 700 for use in the memory module 400 of FIG. Programming driver 70
0 forms part of the sense amplifier 500 of FIG. 5 and includes both elements common to read cycles and elements unique to write cycles. The programming driver 700 is a part of the voltage comparator 530 in FIG.
0, decoders 720 and 760, and forcing circuits 740 and 780. The part of the voltage comparator 530 related to the programming driver 700 is an isolation circuit 7
30 and 770, and includes a balanced latch 750. Isolation circuit 730 has an input connected to node 731, and an output connected to node INA 531. The isolation circuit 770 is connected to the node 7
It has an input connected to 71, and a terminal INB. The balance type latch 750 is connected to a “read latch (READ L
ATCH) "and" Read Latch B (READ LATC) ".
HB) "," PROGRAMLAT "
CH) ”,“ PROGRAM Latch B (PROGRAM L
ATCHB), a data input terminal connected to nodes 731 and 771, and a signal "DATA OUT".
T) "534 with an output terminal.

The forcing circuit 740 outputs “data L (D
ATA)) and an output terminal connected to node 731.
Forcing circuit 780 is "data R (DATAR)"
And an output terminal connected to node 771. Program driver 710 includes a voltage reference input terminal for receiving a charge pumped reference voltage labeled "VPGM", a first input terminal labeled "IN1" connected to node 731, a node 771, a second input terminal labeled "IN2", a first output terminal labeled "OUT1" for providing a first output signal labeled "V _OUTL ", and " OUT2 "has a second output terminal for providing a signal labeled" _VOUTR ".

In operation, programming driver 700 includes elements in common with sense amplifier 500 of FIG. 5, which saves circuit area. As shown in FIG. 7, voltage comparator 530 is also used during program mode and includes balanced latch 750 and two isolation circuits 730 and 770. Balanced latch 750 includes forcing circuits 740 and 780
Receive data to be driven to the selected bit line. When in program mode, signals "Data L" and "Data R" are driven together, but driven in a complementary manner. Which one of the signals "data L" and "data R" is true and which one is complementary depends on which half of the array is selected. This state is indicated by “PGM LATCH” and “PGM LATCH”.
GM latch B (PGM LATCHB) is stored in the latch when activated. The latched data is received by program driver 710, which provides the appropriate voltage level to the bit line decoder where the selected bit line is located. Similarly, if right bit cell array 480 is selected during the write mode, forcing circuit 780 drives the appropriate state to latch 740 and program driver 710 provides the appropriate signal to bit line decoder 760. .

Program driver 710 provides nodes 731 and 771 at inputs IN1 and IN2, respectively.
And output signals labeled OUT1 and OUT2, respectively.
The voltages at OUT1 and OUT2 are at a higher voltage level than the reception voltage. The higher voltage level is determined by the input voltage signal VPGM, which is approximately 5 volts. For the operation of program driver 710, voltage comparator 530 requires isolation circuits 730 and 770 to prevent higher voltages on signals OUT1 and OUT2 from damaging the circuit of balanced latch 750. Also, during a program cycle, the current requirement of the selected memory cell has a significant effect on the voltage of VPGM,
It is important to power the balanced latch 750 from an antenna _VDD power supply that is separate from the PGM. Reuse of the voltage comparator 530 allows for a reduction in circuit area and allows the drive function of the program to be achieved within a relatively small pitch, i.e., at the pitch of the eight bit lines associated with the sense amplifiers.

FIGS. 8 and 9 together show, in partial logic and partial schematic form, specific circuits that can be used to form part of the sense amplifier 500 of FIG. 5 and the programming driver 700 of FIG. . 8 and 9
5 are specific examples of these circuits, there is not necessarily a one-to-one correspondence between the signals of FIGS. 8 and 9 and those of FIG. For example, the signal “COMPARE ENABLE” 582 in FIG. 5 is the complementary signal SALATB and SALAT in FIGS.
Is configured using The signal "Data output (DATA
OUT) ”534 forms a part of the bus.
(DATAR) ". 8 and 9
Are the nodes INA 531 and INB 532 of FIG. 5, respectively. Other elements corresponding to the elements in FIGS. 5 and 7 are designated by the same reference numerals.

FIG. 10 shows, in partial block diagram, partial logic diagram, and partial schematic form, a control gate driver circuit 900 according to the present invention. The control gate driver circuit 900 represents a part of the high voltage word decode unit 430 of FIG. The control gate driver circuit 900 includes an isolation circuit / level shifter 910, a voltage reference switch 912, P-type MOS transistors 925, 932, 9
34 and 936, bias circuit 920, erase power supply 91
4. Positive program power supply 916, negative program power supply 9
30, the pulse circuit 940, and the high-voltage row decoder 9
50.

Isolation Circuit / Level Shifter 91
0 is “Program / Erase Decode (PROGRAM / E
RASE DECODE) 964, a first input terminal for receiving a read signal (REA
D SIGNAL) 962, a second input terminal for receiving a signal, a first voltage reference terminal, a second voltage reference terminal connected to ground potential, and an output terminal. Voltage reference switch 912 provides a first input voltage reference terminal, a second input voltage reference terminal, and a third input voltage reference terminal, and a voltage reference output to the first voltage reference terminal of isolation circuit 910. Output terminal connected as follows.

Transistor 925 has a gate connected to ground potential, a drain connected to ground potential, a source connected to the first input voltage reference terminal of voltage reference switch 912, and a bulk terminal. Bias circuit 920 has a first terminal connected to the source of transistor 925, and a second terminal connected to the bulk terminal of transistor 925. Bias circuit 920 includes resistors 921 and 922. Resistor 921 has a first terminal connected to _VDD , and a second terminal connected to the bulk electrode of transistor 925. Resistor 922 has a first terminal connected to the second terminal of resistor 921, and a second terminal connected to the source of transistor 925.

The erase power supply 914 has a first terminal connected to a ground reference potential, and a second terminal connected to a second voltage reference input of the voltage reference switch 912. Positive program power supply 916 has a first voltage terminal connected to a ground potential reference, and a second voltage reference terminal connected to a third input voltage reference terminal of voltage reference switch 912. Transistor 936 has a gate connected to the ground reference potential, a first current electrode connected to the output terminal of isolation circuit 912, a second current electrode connected to the control gate of the transistor along the selected row, and A bulk electrode connected to one current electrode;
Transistor 934 has a gate, a first current electrode, a second current electrode connected to the second current electrode of transistor 936, and a bulk electrode connected to the first current electrode of transistor 936. Transistor 932 has a gate, a first current electrode, a second current electrode connected to the first current electrode of transistor 934, and a bulk electrode connected to the first current electrode of transistor 936. Negative programming power supply 930 has a first terminal connected to the ground power supply and a second terminal connected to the first current electrode of transistor 932. The pulse circuit 940 outputs “decode address (DECODED A)
DDRESS), and a first output terminal connected to the gate of transistor 932, and a second output terminal connected to the gate of transistor 934. High voltage row decoder 950 has an input for receiving a signal labeled "ADDRESS" 960, and an output for providing the "decode address" to pulse circuit 940.

Note that as shown in FIG. 10, control gate driver circuit 900 includes a portion of high voltage predecode block 432 and high voltage word decoder 430. However, in other embodiments, the designation of these functions may be different. Therefore, it is important to recognize that the function is comprehensively achieved by the control gate driver circuit 900.

In operation, the control gate driver circuit 900 drives the control gate shown in FIG. 3 and further described with reference to FIG. During read mode,
Voltage reference switch 912 is set in the first position to allow electrical connection to the source of transistor 925.
Also, during the read mode, the "read signal" 962 is activated to cause the isolation circuit / level shifter 910 to provide its output terminal with a voltage equal to the voltage at the first voltage reference terminal. This voltage is equal to the P-channel threshold voltage of transistor 925 plus a small additional value. This small additional value is
1 and 922 and transistor 92
5 is determined. The bias circuit 920 has M
The body effect of the OSFET is used to cause the threshold of transistor 925 to increase slightly, so that the voltage at the source of diode-connected transistor 925 is necessary to make it conductive at the source of transistor 936 A little higher than the voltage. Because of the incremental difference in bias between transistor 925 and transistor 936, transistor 936 becomes slightly conductive. Transistor 9
This control, which makes 36 slightly conductive, is controlled by transistor 925.
Is biased slightly higher than the source by bias circuit 920 and transistors 925 and 936
Is achieved by making a match between Preferably, transistors 925 and 936 are given the same gate width and the same gate length dimension and are oriented in the same direction on the integrated circuit. Further, the small additional voltage is preferably selected to ensure that transistor 936 is conductive for all expected process variations.

During the erase mode, the voltage reference switch 91
2 is set at the second position to electrically connect the erase power supply 914 and the first voltage reference terminal of the isolation circuit / level shifter 910. Since the "read signal" 962 is inactive during the erase mode, whether the isolation circuit / level shifter 910 supplies +15 volts to the control gate is determined by the "PGM / erase decode signal" 964. "PGM / erase decode signal" 964 represents a logical combination of both the program / erase signal and the predecode signal received from low voltage word decode block 420 or 460.
During the erase mode, if "PGM / erase decode signal"
If 964 is active, the control gate driver 90
A 0 drives the corresponding control gate to a level of +15 volts generated by erase power supply 914.

During the program mode, the voltage reference switch 912 is set to the third position to electrically connect the positive program power supply 916 and the first voltage reference terminal of the isolation circuit / level shifter 910. Unlike the erase mode, the signal “PGR / erase decode” 96
4 is active during the program mode if the corresponding control gate is not at the selected low. When driving an unselected row, the isolation circuit / level shifter 910 drives a voltage equal to 3.5 volts, which is provided by the positive program power supply 916. A 3.5 volt signal applied to the first current electrode of transistor 936 causes transistor 936 to conduct, thereby providing a 3.5 volt voltage to the control gates of cells that are not selected for programming.

[0064] a signal "PGM / erase decode" 964 inactive, if the corresponding control gate is shown that is positioned in the selected row, isolation circuit / level shifter 910 to the first of the _{V SS} transistors 936 Drive to the current electrode, turning off transistor 936. At the same time, high voltage row decoder 950 activates the signal "decode address" to pulse circuit 940. The pulse circuit 940 turns on the transistors 932 and 934 so that the negative program power supply 930 is connected to the control gate. When selected in this manner, transistor 936 acts as an isolation transistor, and the -12 volts provided by negative program power supply 930 provides the isolation circuit /
Care must be taken to prevent reaching the output terminal of the level shifter 910.

By providing a 3.5 volt bias to cells that are not selected for programming,
Control gate driver circuit 900 serves two purposes. First, it reduces the portion of the bit cell junction leakage current that is affected by the electric field near the edge of the floating gate. This reduction in leakage current in turn reduces the current demand from the programming power supply. Control gate driver circuit 900 also uses a 3.5 volt bias on the unselected control gate to moderate the electric field across the tunnel oxide of the unselected cells on the selected bit line for programming. This reduces the rate at which the bit line voltage disturbs the data state stored in the unselected cells of the bit line being programmed.

The negative program power supply 930, the positive program power supply 916, and the erase voltage 914 are common to both the left half bit cell array 440 and the right half bit cell array 480. There are four transistors in high voltage word decode block 430, and transistor 932 is representative. Further, there is a transistor corresponding to the transistor 934 corresponding to each word line.

During the program mode, instead of providing a continuous active signal on the selected word line, pulse circuit 940 provides a pulse flow to select transistors 932 and 934 to provide a -12 volt voltage on the selected word line. Expand the program voltage gradually. The circuit for connecting the negative program power supply 930 does not need to maximize speed since read mode speed is not a critical path, which gradually expands the -12 volts required by the pulse circuit 940. It can be so. Further, transistors 932 and 934 can be smaller.
In the illustrated embodiment, transistor 934 can be small enough to fit within the pitch of the memory cells. In addition, this pulsing action allows for a smaller capacitance in the charge pump to generate or function as the negative program power supply 930.

FIG. 11 shows, in schematic form, a particular circuit that can be used to implement a portion of the pulse circuit 940 of FIG. Note that this circuit is exemplary and other circuits can be used. FIG. 11 also shows transistor 934 and P-channel transistor 1002. The transistor 1002 is a transistor 934
, Except that the control gate is driven by a different word line than transistor 934. Transistor 934 provides a control gate drive signal labeled "CG0", while transistor 1002 provides a different control gate signal labeled "CG1". Because of the particular configuration of the present invention, there is no need for a one-to-one correspondence between the signals of FIG. 11 and those of FIG.

FIG. 12 shows a charge pump 1120 used to generate a power supply voltage for the control gate driver circuit 900 of FIG. 10 in accordance with the present invention in partial block diagram and partial schematic form. The charge pump 1120 has a non-linear stage.
ge) 1130, reference voltage generation stage 1140, and linear stages 1150 and 11
60 inclusive. The voltage reference generating circuit 1140 is connected to the first voltage reference terminal (V _DD ) and generates a reference voltage named “Vz”. _VDD is a more positive supply voltage terminal having a nominal value of 2.7 volts, but it can have a lower value. The circuit stage 1130 is connected to V _DD
, And the reference voltage Vz and the “program / erase control (PROGRAM / ERASE CONTROL)”
Receiving a signal named “program voltage 1”
(PROGRAM VOLTAGE1) "and" φA "," φB "," φC "and" φ
D ". Linear stage 1150 receives signals φC, φD and“ program voltage 1 ”and generates an output signal labeled“ ERASE VOLTAGE ”. The linear stage 1160 receives the signal φA
And φB and “program voltage 2 (PROGR
AM VOLTAGE2) ". As shown in FIG. 3, "program voltage 1" is approximately 5 volts, while "program voltage 2" is approximately-
12 volts, so these are the EEPRs of FIG.
Suitable for use in programming OM cells. The "erase voltage" is also set to approximately 15.5 volts.

The non-linear stage 1130 has an input connected to _VDD , an input labeled "Vz" for receiving a voltage reference signal, and an output voltage that substantially doubles the voltage received at the input. Regulated voltage doubling stage having an output for generating
stage doubling stage) 1132
including. The non-linear stage 1130 also includes the circuit stage 1132
A voltage doubling having an input connected to the output of the input, an input labeled "Vz" for receiving a voltage reference signal, and an output for producing an output voltage substantially doubled the voltage received at the input. Step (voltage double)
ing stage) 1134. Nonlinear stage 113
0 further comprises an input connected to the output of said circuit stage 1134, an input labeled “Vz” for receiving a voltage reference signal, a signal “program voltage 1” and a phase signal φ.
A voltage doubling stage 1136 having an output for producing A, φB, φC, and φD is included.

Preferably, said voltage Vz is selected to limit any circuit stage from producing an output greater than the 5 volts required by "program voltage 1". In this embodiment of the invention, each circuit stage receives the same voltage reference, and they all receive the same voltage Vz. In another embodiment, a different reference voltage can be used for each circuit stage. Adjustment voltage doubling stage 1136 generates a series of drive signals having a voltage amplitude approximately equal to "program voltage 1". These drive signals are applied to the linear stage 1
Used to provide timing and power to 150 and 1160.

The voltage reference generation circuit 1140 includes an adjustment voltage doubler 1142 connected to the adjustment voltage multiplier 1144. The circuit stage 1144 is connected to a linear stage 1146. Circuit stage 1146 is connected to a current shunt regulating diode 1148, the diode 1148 is connected to a power supply voltage terminal labeled _{"V SS".} V _SS has a nominal value of zero volts, which is generally lower than V _DD . The regulated voltage doubling stages 1142 and 1144 are used in a non-regulated manner. Thus, circuit stage 1142, like circuit stage 1144, doubles the voltage provided at its input. Similarly, the linear stage 1146 may also be
gulled). However, those skilled in the art will recognize that any one of these stages 1142, 1144 and 1146 may require a secondary adjustment to prevent the breakdown of the intrinsic transistor.
It will be appreciated that it is necessary to have Circuit stages 1142, 1144 and 1146
It can be appreciated that can be various combinations of linear and voltage doubling stages depending on the current and area constraints of a given application. For the charge pump 1120, the stages 1142, 1144 and 1146 need to generate a voltage Vz sufficient to bias the diode 1148 such that it breaks down, thereby generating a reference voltage Vz. is there.

Linear stages 1150 and 1160 are used to generate “erase voltage” and “program voltage 2”, respectively. Circuit stages 1150 and 1160 are of the Dickson type, which is well known in the art.
pe) is a linear charge pump.

FIG. 13 shows, in partial block diagram and partial circuit diagram form, a voltage doubler (voltage double).
ing stage) 1132 is shown. Voltage doubling stage 11
Note that 32 can be used as one of the other voltage doubling stages of FIG. The voltage doubling stage 1132 has a capacity of 128
2 (C1), 1292 (C2) and 1204 (C
3), P-type transistors 1283, 1284, 128
5,1286,1293,1294,1295,129
6 and 1202, N-type transistors 1287 and 129
7 and 1206, and a level shifter 1270. The capacitor C1 has a first electrode and a second electrode.
A P-type transistor 1283 includes a control electrode for receiving a signal named “CK3”, a first current electrode, and a capacitor C.
A second current electrode connected to the first electrode; and an N-type bulk terminal connected to the first current electrode. Transistor 1284 is connected to a control electrode connected to receive a signal labeled CK7, a first current electrode, a second current electrode connected to the first electrode of capacitor C1, and a bulk terminal of transistor 1283. N-type bulk terminals. P-type transistor 1285 is CK
A control electrode connected to receive a signal labeled 6, a first current electrode connected to a second current electrode of transistor 1284, and a first electrode connected to receive an input voltage labeled "V _IN ". It has two current electrodes and an N bulk terminal connected to the N bulk terminal of the P-type transistor 1283. P-type transistor 1286 has a control electrode connected to receive a signal labeled CK5, a first electrode connected to a second current electrode of transistor 1285.
Current electrode, a second current electrode connected to the second electrode of C1, and N connected to receive the input voltage _VIN.
Has bulk terminals. Transistor 1287 has a control electrode connected to receive a signal labeled CK1 and a first electrode connected to a second current electrode of transistor 1286.
And a second current electrode connected to the first voltage reference terminal. The transistor 1294 is CK8
A control electrode connected to receive a signal named
It has a first current electrode connected to the first current electrode of the transistor 1284, a second current electrode, and an N bulk terminal connected to the N bulk terminal of the P-type transistor 1283. The P-type transistor 1295 is a transistor 12
The control electrode connected to the control electrode 86, the transistor 1
A first current electrode connected to the second current electrode of H.294;
It has a second current electrode connected to receive V _IN , and an N bulk terminal connected to the N bulk terminal of transistor 1283. A P-type transistor 1296 is connected to a control electrode connected to the control electrode of transistor 1285, a first current electrode connected to a second current electrode of transistor 1295, a second current electrode, and connected to receive _VIN . It has N bulk terminals. Transistor 129
7 is a control electrode connected to receive a signal labeled CK2, a first current electrode connected to a second current electrode of transistor 1296, and a second current connected to a first voltage reference terminal. It has electrodes. C2 is a first electrode connected to a second current electrode of transistor 1294;
And a second electrode connected to a second current electrode of the transistor 1296. The transistor 1293 is CK
A control node connected to receive the clock signal labeled 4; a first current electrode connected to the first current electrode of transistor 1283; a second current electrode connected to the first current electrode of C2. And transistor 1283
Have N bulk terminals connected to the N bulk terminals.

The transistor 1202 is a control electrode connected to the first voltage reference terminal.
A first current electrode connected to the first current electrode of the transistor 1294, a second current electrode connected to the first current electrode of the transistor 1294, and an N bulk terminal connected to the N bulk terminal of the transistor 1283. Capacitor C3 is connected to the second current electrode of transistor 1202 and “unregulated output voltage (UNREGULATED OUTPUT VOL)
TAGE) ".
And a second voltage connected to the first voltage reference terminal. Transistor 1206 has a control electrode connected to receive voltage Vz, a first current electrode connected to the first electrode of C3, and a "regulated output voltage (REGU).
(LATED OUTPUT VOLTAGE) ".
Level shifter 1270 is connected to the first current electrode of transistor 1206, receives _VIN , φ1 to φ4, and receives signals CK3, CK4, CK5, CK6, CK7, and C
Generate K8.

In operation, voltage reference circuit 1140 applies reference voltage Vz to voltage doubling stage 113 of nonlinear stage 1130.
2, 1134 and 1136. Since Vz only provides a voltage reference, only a minimal amount of charge need be provided by circuit 1140.
Non-linear stage 1130 provides "program voltage 1" and thus provides the charge required by an external load (not shown). By using a non-linear stage,
First stage capacitances with thinner dielectric layers can be formed over the semiconductor devices because of the very low voltage in these first stages. Thinner dielectrics allow capacitance with higher capacitance, as will be described later with reference to FIG. This allows a charge pump to use less semiconductor area.

FIG. 14 shows a signal timing diagram useful in understanding the operation of the voltage doubler stage 1132 of FIG. FIG. 14 shows the timing relationship between signals φ1 to φ4 and CK1 to CK8 for controlling the operation of the adjustment voltage doubler 1132 in FIG. Considering FIG. 14 in combination with FIG. 13, each clock signal is active or inactive during a particular time or portion of a clock cycle. Each part of the clock cycle is t1,
Referenced as t2, t3 and t4. CK1 is t1
And active high during t2. CK4 is t1
Active low during CK6 is active low during t1. CK8 is active low during t1. CK2 is active high during periods t3 and t4, and CK3 is active low during t3. CK5
Is active low during t3. CK7 is active low during t3. Note that the arrow in FIG. 14 indicates that an edge occurs at t2 or t4 at substantially the same time, but actually follows another edge that occurs at substantially the same time. . For example, the rising edge of CK4 at time t2 is CK4 during time t2.
Occurs after the sixth rising edge. This ensures that the transistor controlled by CK6 transitions before the CK4 signal goes inactive. C
K1 and CK2 transition to active low at the end of times t2 and t4, respectively. The timing of FIG. 14 allows the capacitors 1282 and 1292 to be charged alternately by the input signal, while providing a “regulated output voltage” through transistor 1206.

Once a steady state is obtained during t1, capacitor C1 is charged while capacitor C2 is discharged.
The capacitor C1 is charged by the transistors 1285 and 1287
Is easily driven because it is actively driven,
On the other hand, transistors 1284, 1286 and 1283 are driven inactive. This means that the capacitance C1 is V
Connected between _IN and the first voltage reference, while isolating capacitance C1 from the rest of circuit 1132. As a result, charge flows into C1 until it is charged to voltage _VIN or the cycle ends. During t3, capacitance C2 is charged to _VIN in a similar manner.

During t1, C2 is generating the doubled voltage required to generate the "unregulated output voltage". This is because transistors 1293, 1296 and 1
294 is driven active while transistors 1297, 1295, 1284, and 1286 are driven inactive. This connects C2 between the "unregulated output voltage" terminal and _VIN , while isolating capacitance C2 from the rest of circuit 1132.
The voltage generated at the first electrode of transistor 1294, representing the unregulated output voltage, is the sum of the voltage across C2 and _VIN . As mentioned earlier, the voltage across C2 is approximately _VIN , thus producing a doubled or doubled _VIN . The unregulated output voltage is regulated by a transistor 1206 biased by a substantially constant signal Vz to provide a "regulated output voltage."
I will provide a. During t3, the capacitor C1 is connected in a similar manner between _VIN and the output terminal.

During the time t2, the electric charge is
It is necessary to keep transistor 1287 active to prevent injection at the common electrode of 86 and 1287. This ensures that the electrode is held at ground, thereby ensuring that the drain-substrate junction represented by the electrode is not forward biased. For example, the transistor 128
By ensuring that 4,1285 and 1286 transition completely before transistor 1287 becomes inactive, the possibility of forward biasing the substrate junction is avoided. Similarly, transistors 1294, 1295
And 1296 are transitioning during time t4, ensuring that transistor 1297 is held active to avoid the same effect at a node common to transistors 1296 and 1297.

Transistors 1283, 1284, 128
5,1293, 1294, 1295 and 1202 have a common N bulk terminal. The N bulk terminal according to one embodiment of the present invention is actually an N well. This N-well is charged to the "unregulated output voltage" through transistors 1283 and 1293, respectively, which are active during times t3 and t1. The transistor 1202 is N
A weak transistor used to ensure that the well voltage does not rise significantly above the "regulated output voltage" and remains there for a long period of time. For example,
At startup, or when an output load is applied to the output of the charge pump, there may be situations where the N-well is charged to a voltage well above the "unregulated output voltage". Such a voltage difference makes the MOS transistor less conductive than otherwise. If sustained, such a condition would reduce the overall output of the pump. Thus, transistor 1202 ensures that any voltage differences are merely transient in nature. By driving the N-bulk to an "unregulated output voltage" so that it does not charge and discharge each cycle, gaining high efficiency because no charge is lost due to capacitive parasitics associated with the well Can be.

Between times t2 and t4, there can be a period in which CK4 transitions and CK1 does not transition. During this time, the "regulated output voltage" cannot receive that voltage from the capacitors C1 or C2, and thus the capacitor C3 is needed to bridge the gap during this period. And supply the charge required by the level shifter 1270 between times t2 and t4. In general, since the time represented by t2 is much smaller than t1, capacitance C3 will be much smaller than capacitances C1 and C2.
Similarly, C3 provides the required voltage during time t4.

Level shifter 1270 receives signals φ1 to φ4 as shown in FIG. φ1 represents the active signal during time t1. Signal φ2 represents a signal active during time t2. Signal φ3 represents an active period during time t3. Signal φ4 represents a signal active during time t4. These signals are combined to form CK1-CK8
Generate appropriate active and inactive signals for CK1 and CK2 have an inactive low voltage of zero or ground, and have an active high voltage reference of _VDD . CK3 to CK8, whether active or inactive, have a low signal equal to zero or ground, while a high state indicates whether the capacitance C3 is active or inactive. Equal to the "unregulated output voltage" appearing at one electrode. Further, CK1 and CK2 are generated by combining signals φ1 and φ2 and signals φ3 and φ4, respectively. Accordingly, the level shifter applies the appropriate voltage levels necessary to drive the circuit stages in charge pump 1120 of FIG.

Returning to FIG. 12, circuit stages 1142 and 1
144 is implemented using the regulated voltage doubler circuit of FIG. However, block 1144 is shown to drive two signals, φ5 and φ6, to drive Dickson type circuit stage 1146. Dickson circuit stage 114
Due to the requirement of 6, the signals φ5 and φ6 must be substantially equal to the bias or output voltage of the circuit stage 1144. If this condition is met, the Dickson circuit stage 1146, which has three internal circuit stages, can provide an output voltage on the order of four times its input voltage, but in each case is limited to the breakdown voltage of the diode 1148.

Circuit stages 1132 and 11 of nonlinear stage 1130
34 and 1136 use the regulated voltage doubling stage circuit 1132 of FIG. In each of these cases, the regulation voltage Vz limits the voltage generated by any circuit stage to 5 volts. The final stage of the non-linear stage 1130 includes additional phase signals φA, φB, φC and φD.
I will provide a. These signals are two N and P connected between the "regulated output voltage" node and ground.
Generated from circuit 1132 using a transistor pair (not shown). The timing is controlled by the timing signal of FIG. Which pair of N and P transistors is selected is actually controlled by a "program / erase control" signal. The selected N and P transistor pairs are Dickson charge pumps 1150 and 11
60 generates the necessary complementary output signals to enable operation. It should be noted that the operation of circuit stages 1150 and 1160 are mutually exclusive in that only one circuit stage is driven at any given time.

The regulated voltage doubling stages 1132 and 113
To estimate or calculate the capacitance value for C1 and C2 for each of 4,1136, 1142 and 1148, the following equation can be used.

## EQU1 ## Q = Iout / Freq

V (n) = V _DD ^* (Vout / V _DD ) ^**
(N / N)

Vc (n) = 2 ^* V (n-1) -V (n)

## EQU4 ## C (n) = QE12 ^* ((2 ^** (N-n))
^* (Eff ^** (n-1-N))) / Vc (n)

Ctotal (N) = (sum of all C (n) from n = 1 to N) where _VDD is the power supply voltage, N is the number of circuit stages in the charge pump and Iout Is the desired output current, Vout is the desired output voltage, eff is the efficiency of the circuit, and Freq is the frequency at which the charge pump is switching.

Equation 1 shows the amount of charge obtained at the output of the charge pump. Equation 2 shows the voltage at the output of a given circuit stage n, where the circuit stages may be dimensioned to produce a uniform interstage voltage gain. Equation 3
Indicates the change in voltage across a given circuit stage capacitance and during a pump cycle, including the charging and discharging of a capacitance such as C1 or C2. Equation 4 shows the total capacity of the charge pump in a circuit stage and indicated in picofarads. The value C (n) is the sum of the capacities of C1 and C2. Generally, C1 and C2 are substantially the same. For example, it requires 1.8 volts of _VDD and 1 microamp of output current and 4.5 volts of required output voltage, 1 megahertz clock signal and 98
For a three stage charge pump with a% circuit efficiency, the capacitance value for the first stage is 3.7 picofarads per microamp of output current. Circuit stage 2 has a capacity requirement of 1.3 picofarads per microamp of output current, while circuit stage 3 has a capacity requirement of 0.5 picofarads per microamp of output current. This is the required capacitance value for the combined capacitance of C1 and C2.

The selected capacitance values as described above illustrate the advantages of using the non-linear charge pump of the present invention. The capacitance of circuit stage 1 (stage 1) is much larger than the capacitance required in the combined circuit stage 2 (stage 2) or circuit stage 3 (stage 3). This relationship is illustrated in FIG. 15, which shows, in graphical form, the capacitance associated with each circuit stage of the charge pump 1120 of FIG. The advantage is that the operating voltage of the first circuit stage is much lower than that of the second and third circuit stages, so that a thinner dielectric layer can be used in the formation of the capacitor C1. For example, in one embodiment of the present invention, the capacitance C1
May be the same thickness as the tunnel oxide dielectric used in the bit cell. This is due to the higher voltage associated therewith than using thick film dielectrics required in circuit stages C2 and C3.
Allow the volume to be formed using a much smaller surface area.

Although the present invention has been described in terms of a preferred embodiment, it will be apparent to one skilled in the art that the present invention can be modified in many ways and can take many other embodiments than those specifically described and described above. There will be. For example, other voltage levels can be used to program a memory cell, or a different number of control gates can be controlled by a control circuit. It is therefore intended by the appended claims to cover all modifications of the invention that fall within the true spirit and scope of the invention.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a memory array.

FIG. 2 is a cross-sectional view of a memory cell that can be used with the present invention.

FIG. 3 is an illustration showing a method for operating a memory array according to the present invention.

FIG. 4 is an explanatory view showing a memory module according to the present invention in the form of a partial block diagram and a partial plan view.

FIG. 5 is a block diagram partially showing a decode and sense amplifier unit related to reading of the memory module of FIG. 4;
FIG. 3 is an explanatory diagram shown in a partial logic diagram and a partial circuit diagram format.

FIG. 6 is a timing diagram illustrating various signals associated with a read cycle for both conductive and non-conductive memory cells.

FIG. 7 is a block diagram illustrating a programming driver for use in the memory module of FIG. 4;

8 is an electrical schematic showing in partial logic and partial schematic form a circuit that can be used in combination with FIG. 9 to form part of the circuit shown in connection with FIGS. 5 and 7; .

FIG. 9 is an electrical schematic showing in partial logic diagram and partial schematic form a circuit that can be used in combination with FIG. 8 to implement the portions of the circuit shown with reference to FIGS. 5 and 7;

FIG. 10 is an explanatory diagram showing a control gate driver circuit according to the present invention in the form of a partial block diagram, a partial logic diagram, and a partial circuit diagram.

FIG. 11 is an electrical schematic showing a particular circuit that can be used to implement a portion of the pulse circuit of FIG.

FIG. 12 is an illustration showing, in partial block diagram and partial schematic form, a charge pump used to generate a supply voltage for the control gate driver circuit of FIG. 10 in accordance with the present invention.

FIG. 13 is an illustration showing one of the voltage doubling stages of FIG. 12 in partial block diagram and partial circuit diagram form.

FIG. 14 is a timing diagram of signals useful for understanding the operation of the voltage doubler of FIG. 13;

FIG. 15 is an explanatory diagram showing, in a graph form, capacitance associated with each circuit stage of the charge pump of FIG. 12;

[Explanation of symbols]

25 Memory array 10 Selected memory cell 30 Non-selected memory cell 22 Isolation transistor 23 Floating gate transistor 400 Memory module 410 Control and predecode section 420,460 Low voltage word decode section 430,470 High voltage word decode section 432,472 High Voltage predecoder 440, 480 Bit cell array 450 Sense amplifier 500 Decode and sense amplifier 510, 520 Decode logic 542, 544, 562, 564 P-type MOS transistor 546, 566 Inverter 548, 550, 568, 570 Current source 530 Voltage comparator 512, 513 N-type MOS transistor 515 Selection circuit 511 Threshold voltage generator 517, 518 Transmission gate 522, 523 N MOS transistor 521 Threshold voltage generator 525 Selection circuit 527,528 Transmission gate 700 Programming driver 710 Program driver 720,760 Decoder 740,780 Forcing circuit 730,770 Isolation circuit 750 Balanced latch 900 Control gate driver circuit 910 Isolation circuit / level shifter 912 Voltage reference switch 925 923, 934, 936 P-type MOS transistor 920 Bias circuit 914 Erase power supply 916 Positive program power supply 930 Negative program power supply 940 Pulse circuit 950 High voltage low decoder 1120 Charge pump 1130 Non-linear stage 1140 Reference voltage generation stage 1150, 1160 Linear stage

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yanmin Suu 1310, Cedar Park, Whippo Will Drive, Texas, 13613, U.S.A.・ Lane 11219

Claims (5)

[Claims] 1. A charge pump (1120), comprising: a voltage reference generation circuit (1140) having at least one output terminal for providing a corresponding reference voltage; a voltage input terminal connected to a power supply voltage terminal; A reference input terminal coupled to a voltage reference generation circuit for receiving a first reference voltage, and a voltage output terminal for providing a first regulated voltage, and doubling the voltage at the voltage input terminal A first regulated voltage doubler charge pump stage (113) having a first capacitance (1282, 1292) used to provide said first regulated voltage
2) and a voltage input terminal connected to the voltage output terminal of the first regulated voltage doubling charge pump stage (1132), coupled to the voltage reference generation circuit for receiving a second reference voltage. A reference input terminal, and an output terminal for providing a second regulated voltage, and used to double the voltage at the voltage input terminal to provide the first regulated voltage. The second capacity (12
82, 1292) having a second regulated voltage doubler charge pump stage (1134), wherein the first capacitor is formed using an oxide thinner than the second capacitor, and A charge pump (1120) for saving area. 2. A control gate driver circuit (900) configured to provide a predetermined voltage to a control gate of an erasable programmable non-volatile memory cell during its read mode, comprising: a first voltage; A gate electrode coupled to the reference terminal, a first current electrode, a second current electrode coupled to the control gate,
And a predetermined conductivity type pass transistor (936) having a bulk electrode coupled to the first current electrode, and a bias circuit (920) having an output terminal coupled to the first current electrode of the pass transistor. Wherein the bias circuit generates a predetermined voltage at the output terminal, the predetermined voltage being substantially equal to a threshold voltage of the pass transistor (936) plus a certain incremental voltage; A control gate driver circuit (900), comprising: 3. A control gate driver circuit (900) configured to provide a predetermined voltage to a control gate of an erasable and programmable non-volatile memory cell during its program mode, the control gate driver circuit comprising: A first program voltage source (930) having a reference terminal for providing a voltage, a control electrode, a first current electrode coupled to the reference terminal,
A first pass transistor of a predetermined conductivity type having a second current electrode for driving the control gate, and coupled to a control electrode of the first pass transistor. A pulse circuit (940) having a pulse output terminal and a data input for receiving at least one data signal, the pulse circuit (940) pulsing the at least one data signal at the pulse output terminal. A decoder (950) having an address input for receiving an address signal, and a decode output coupled to a data input of the pulse circuit (940), the decoder (950) comprising: Decoding the address input during a program mode. Your gate driver circuit (900). 4. The method of claim 1, wherein the predetermined voltage is a charge pump (1120), a non-linear stage (1130) having a voltage input terminal connected to a power supply voltage terminal, and a voltage output terminal for providing a regulated voltage. ) Wherein the non-linear stage (1130) comprises a plurality of serially coupled regulated voltage doubling stages (1132,
1134) and a linear stage (1150) having a voltage input terminal connected to the voltage output terminal of the non-linear stage (1130) and an output terminal for providing the predetermined voltage. The control gate driver circuit (900) of claim 3, wherein the control gate driver circuit (900) is generated by a charge pump (1120). 5. A control gate driver circuit (900) having a control gate voltage terminal for providing a control gate voltage to a control gate of an erasable and programmable nonvolatile memory cell, comprising: a read voltage terminal (962). An erase voltage terminal (914); a program selection voltage terminal (916); a program non-selection voltage terminal (964); an address and control signal; and the read voltage terminal, the erase voltage terminal, and the program non-selection voltage terminal And a first decoding unit (910) having a first voltage output, wherein the first decoding unit (910) is associated with a control gate of a memory cell, the decoding unit comprising the address and A plurality of modes are supported based on a control signal, wherein the memory cell is selected and the control signal is An erase mode in which the first decoding unit couples the erase voltage terminal to the first voltage output when indicating an erase mode; and when the memory cell is selected and the control signal indicates the erase mode. The first decoding unit (910)
A program select mode in which the read voltage terminal is coupled to the first voltage output. The first decode section (91) when the memory cell is not selected and the control signal indicates the erase mode.
0) is a program non-select mode in which the program selection voltage terminal is coupled to the first voltage output, and the first decoding unit (910) connects the read voltage terminal to the read voltage terminal when the control signal indicates reading. A read mode coupled to a first voltage terminal, a second decode unit (950) for receiving address and control signals and coupled to the program voltage terminal and having a second voltage output. The first decoding unit is associated with a control gate of the memory cell, and the second decoding unit is configured to change the program voltage when the memory cell is selected and the control signal indicates a program mode. Providing a second voltage output; a control electrode coupled to a first voltage reference; a first current electrode coupled to the first voltage output; Second to provide a coupled to the output and the control gate voltage terminal
And a transistor of a predetermined conductivity type having a current electrode and a bulk electrode coupled to the second current electrode.
6) A control gate driver circuit (900), comprising: