JPS6146642A - 直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路 - Google Patents

直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路

Info

Publication number
JPS6146642A
JPS6146642A JP59167524A JP16752484A JPS6146642A JP S6146642 A JPS6146642 A JP S6146642A JP 59167524 A JP59167524 A JP 59167524A JP 16752484 A JP16752484 A JP 16752484A JP S6146642 A JPS6146642 A JP S6146642A
Authority
JP
Japan
Prior art keywords
input
terminal
reference clock
data
preset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59167524A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0316054B2 (enrdf_load_stackoverflow
Inventor
Tsuneyuki Kitajima
恒之 北島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Communication Equipment Co Ltd
Original Assignee
Toyo Communication Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Communication Equipment Co Ltd filed Critical Toyo Communication Equipment Co Ltd
Priority to JP59167524A priority Critical patent/JPS6146642A/ja
Publication of JPS6146642A publication Critical patent/JPS6146642A/ja
Publication of JPH0316054B2 publication Critical patent/JPH0316054B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59167524A 1984-08-10 1984-08-10 直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路 Granted JPS6146642A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59167524A JPS6146642A (ja) 1984-08-10 1984-08-10 直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59167524A JPS6146642A (ja) 1984-08-10 1984-08-10 直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路

Publications (2)

Publication Number Publication Date
JPS6146642A true JPS6146642A (ja) 1986-03-06
JPH0316054B2 JPH0316054B2 (enrdf_load_stackoverflow) 1991-03-04

Family

ID=15851291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59167524A Granted JPS6146642A (ja) 1984-08-10 1984-08-10 直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路

Country Status (1)

Country Link
JP (1) JPS6146642A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292125A (ja) * 1988-09-29 1990-03-30 Pfu Ltd データ受信装置
JPH03123338U (enrdf_load_stackoverflow) * 1990-03-27 1991-12-16

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220534A (ja) * 1982-06-17 1983-12-22 Shinko Electric Co Ltd 同期パルス抽出回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220534A (ja) * 1982-06-17 1983-12-22 Shinko Electric Co Ltd 同期パルス抽出回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292125A (ja) * 1988-09-29 1990-03-30 Pfu Ltd データ受信装置
JPH03123338U (enrdf_load_stackoverflow) * 1990-03-27 1991-12-16

Also Published As

Publication number Publication date
JPH0316054B2 (enrdf_load_stackoverflow) 1991-03-04

Similar Documents

Publication Publication Date Title
AU600871B2 (en) Clock recovering device
CA1308448C (en) Method of and circuit arrangement for recovering a bit clock from a received digital communication signal
US5550878A (en) Phase comparator
JPS62145924A (ja) デイジタル・フエ−ズロツクル−プ回路
CN111416619A (zh) 一种延时测量电路、延时测量方法、电子设备及芯片
JPS6146642A (ja) 直列デ−タ伝送装置用受信デ−タサンプリングパルス発生回路
EP0094956B1 (en) A method of bringing an oscillator into phase with an incoming signal and an apparatus for carrying out the method
JPS5895447A (ja) クロツク再生回路
JP2002319928A (ja) 中心位相判定回路とその中心位相判定方法
JPH07229979A (ja) 多相クロック時間計測回路
CN112332834B (zh) 激光雷达的时间数字转换器避免亚稳态的矫正方法及装置
JP3513399B2 (ja) シリアルデータによるタイミング可変装置
JP2712725B2 (ja) 並列ディジタル信号のラッチ装置
JPH10135796A (ja) 外部同期方法及び外部同期回路
JP3742092B2 (ja) 中心位相判定回路とその中心位相判定方法
JPH0537508A (ja) 調歩信号のパルス幅歪補正回路
JPS61199348A (ja) 非同期検出回路
JP2523820B2 (ja) 位相同期回路
JP2690990B2 (ja) カウンタ
KR950002305B1 (ko) 수신데이타에 의한 동기클록발생회로
JPH03202910A (ja) 同期化回路
JPH04314230A (ja) ビット相関判定回路
JPH03204251A (ja) クロック同期回路
JP2003179587A (ja) データ入力装置
JPS62281534A (ja) フレ−ム同期パタ−ン相関検出回路