JPS6137706B2 - - Google Patents
Info
- Publication number
- JPS6137706B2 JPS6137706B2 JP55118599A JP11859980A JPS6137706B2 JP S6137706 B2 JPS6137706 B2 JP S6137706B2 JP 55118599 A JP55118599 A JP 55118599A JP 11859980 A JP11859980 A JP 11859980A JP S6137706 B2 JPS6137706 B2 JP S6137706B2
- Authority
- JP
- Japan
- Prior art keywords
- request signal
- memory
- signal
- clock
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Memory System (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55118599A JPS5744289A (en) | 1980-08-28 | 1980-08-28 | Memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55118599A JPS5744289A (en) | 1980-08-28 | 1980-08-28 | Memory control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5744289A JPS5744289A (en) | 1982-03-12 |
JPS6137706B2 true JPS6137706B2 (enrdf_load_stackoverflow) | 1986-08-25 |
Family
ID=14740553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55118599A Granted JPS5744289A (en) | 1980-08-28 | 1980-08-28 | Memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5744289A (enrdf_load_stackoverflow) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59117782A (ja) * | 1982-12-24 | 1984-07-07 | Nec Corp | 記憶装置リフレツシユ制御方式 |
JPS62209606A (ja) * | 1986-02-17 | 1987-09-14 | Fujitsu Ltd | 主記憶装置タイミング作成方式 |
-
1980
- 1980-08-28 JP JP55118599A patent/JPS5744289A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5744289A (en) | 1982-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1205529A (en) | Arbiter circuit and method | |
KR100311044B1 (ko) | 클럭 주파수에 따라 레이턴시 조절이 가능한 레이턴시 결정 회로 및 레이턴시 결정 방법 | |
US5835422A (en) | Circuit and method for generating a control signal for a memory device | |
JP2695535B2 (ja) | タイマ入力制御回路及びカウンタ制御回路 | |
JP2551338B2 (ja) | 情報処理装置 | |
JPS6137706B2 (enrdf_load_stackoverflow) | ||
KR100508581B1 (ko) | 버스제어방법및그방법을이용한장치 | |
JP3018404B2 (ja) | マイクロプロセッサ | |
US7441138B2 (en) | Systems and methods capable of controlling multiple data access using built-in-timing generators | |
JP2624388B2 (ja) | Dma装置 | |
JPH0143392B2 (enrdf_load_stackoverflow) | ||
JPS61177564A (ja) | 共有記憶装置 | |
JPH0245274B2 (enrdf_load_stackoverflow) | ||
KR100200769B1 (ko) | 중앙 처리 장치의 출력제어회로 | |
US6275416B1 (en) | Pulse generator circuit, particularly for non-volatile memories | |
SU1524089A1 (ru) | Устройство дл управлени динамической пам тью | |
JPS6120077B2 (enrdf_load_stackoverflow) | ||
US20010036121A1 (en) | Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit | |
JPS60138661A (ja) | 処理装置の制御方式 | |
JP2626112B2 (ja) | マイクロプロセッサ | |
SU1182532A1 (ru) | Устройство для синхронизации обращения к памяти | |
JPH03132852A (ja) | バス非同期制御方式 | |
JPH05134924A (ja) | メモリ制御回路 | |
SU1755367A1 (ru) | Устройство дл формировани серий импульсов | |
JPH0767288B2 (ja) | サイリスタ・インバ−タのゲ−トパルス制御装置 |