JPS6134778A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simultaneously write and read data to independent memory areas of a semiconductor memory by accessing two independent memory areas on a semiconductor substrate by selecting an address or converted address. CONSTITUTION:An address is selected which is converted by being interleft, etc., at an address and address converted part 20 by an address bus 22 of one system, by an addressf selection circuit 23 controlled by a control circuit 45. Independent memory areas 11 and 12 are accessed on the same semiconductor substrate which is connected to input and output data buses 31 and 32 respectively different according to the selected address. Consequently, the writing and reading of the data of the independent 2 memory areas of the semiconductor memory can be simultaneously executed without any trouble.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory capable of simultaneously writing and reading data.

Conventional Structures and Problems The recent information society is largely dependent on many electronic devices such as computers that process large amounts of digital signals, which are the substance of information. By the way, after processing a large amount of digital signals, it goes without saying that the data is stored on a medium such as recording the data on a magnetic disk, magnetic tape, etc., or transmitting the data to another location via an optical fiber. A lot of things change. Various data processing is performed during this change, and semiconductor memory is used in various parts of the processing.

For example, when data is transferred to another medium, an error correction code is usually added to the data to increase the reliability of the data so that errors in the data can be detected and corrected. This error correction code also cannot cope with burst errors in which large amounts of data are continuously lost. Therefore, the order of the data is intentionally rearranged and the data is transferred to another medium to prevent burst errors. This is a method called interleaving. Semiconductor memories are typically used to interleave data. First, data is selected sequentially from addresses 0, 1.2, 3, 4.5, etc. and temporarily stored in memory, and then 0, 10° 20. 30.4
Select an address such as 0.50, read the data from the memory, rearrange the order of the data, and send it out. In this case, one memory is used, and data is written once in the entire storage area of the memory and then read out. However, due to the requirement to transfer a large amount of data at high speed, two semiconductor memories RAM0 and RAM1 are used, for example, as shown in FIG. 1,2゜3
is the data bus, bus 1 [RAM0], bus 2 RAM2
3 is a common data bus, and a bus switching circuit 4 switches between buses 1, 2, and 3. 6゜6 is the address bus,
Bus es corresponds to RAMO, and bus 6 corresponds to RAM1. 7 and 8 are address generation circuits, and the addresses generated by the circuits 7 and 8 are different from each other. These addresses are transferred by the address switching circuit 9 to the switching RAM0. Address signals are supplied to each RAM1.

First, data is written into one memory RAM○ via data bus 1. In this case, interleaving is not performed. Then, data is written into the RAM 1 via the data bus 2 in the same manner. At this time, data is read from RAM0 at the same time. The address selection at this time is interleaved and is different from the address at the time of writing. In this way, data is sequentially written to and read from RAM0 and RAM1. Although this method can transfer data at high speed, it requires two memories, and when implemented as an electronic device, extra space is required on the printed circuit board, and the cost of the components itself is compared to the case of one memory. Therefore, twice as much is required, which hinders cost reduction. There are many cases where data is written to and read from a plurality of memories, not only when using the interleaving method as described above.

In this case as well, due to the nature of memory having a block diagram as shown in FIG. 2, writing and reading cannot be performed simultaneously on one memory chip, which has often resulted in wasted implementation costs.

OBJECTS OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor memory in which data can be written and read simultaneously.

Structure of the Invention A semiconductor memory according to the present invention has two mutually independent storage areas on the same semiconductor substrate, each of the two storage areas has an input/output data bus, and one address bus.
system only, and an address translation section,
It is possible to simultaneously select different addresses for two storage areas, and by using a semiconductor memory with such a configuration, it is possible to achieve the above objectives.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Third
The figure shows a block diagram of a semiconductor memory according to an embodiment of the present invention. In FIG. 3, 11.degree. and 12 are two independent storage areas, 2o is an address translation section, 21.22 is an address bus, and as a matter of course, the addresses of the buses 21.22 are different. 23 is an address selection circuit, 41, 42, 43 are control circuits, and 44 is a control signal line.

The block diagram shown in FIG. 3 is all constructed on the same semiconductor substrate.

As shown in Fig. 3, it has two storage areas 11 and 12, and input/output data buses 31 and 3 for each.
2 is provided. However, as for the address bus, it does not correspond to each storage area like the data bus, but as shown in Figure 3, the address bus has 22
(when viewed from the outside). This address bus 2
2 is input to the address selection circuit 23 and the address conversion section 20. In the address conversion unit 2o, as described in the explanation of the conventional example, when performing interleaving, the order of data is simply rearranged, so interleaving can be performed by performing simple operations on input addresses. It is possible to output the assigned address to the bus 21, and therefore the inside thereof can be configured with a relatively simple circuit. Also, if complex operations other than interleaving are required,
It is possible to deal with various cases by storing the relationship between the input address (bus 22) and the output address (bus 22) in a ROM.

In this way, different addresses exist on the address buses 21 and 22, and the addresses are selected by the address selection circuit 2.
Select with 3. These selections are made by a control signal line 45, which will be described later. Each address is storage area 1
1.12 to read and write data. That is, it is possible for a memory on the same semiconductor substrate to select two mutually different addresses, and to read or write data therefrom.

Which of the two addresses each storage area selects, and whether to read or write data is determined by
It is controlled by a control circuit 43. A control signal 44 is input to the control circuit 43 from the outside. The control signal 44 includes a write enable signal.

There are chip select signals, etc. These control signals 44 select several modes of operation. For example, writing data to storage area 11.12, conversely, writing data to area 11.1
There are modes such as reading data from area 11 and reading data from area 12, or vice versa, reading data from area 11 and writing data to area 12.

As can be seen from the above, by using a semiconductor memory configured as described above, it becomes possible to simultaneously perform operations of writing and reading data. Therefore, if a semiconductor memory with this configuration is used in an electronic device where semiconductor memory is used to read and write data at the same time, one memory chip can be used instead of at least two memories in the past. This is a good thing, and when you consider the mounting costs on printed circuit boards and the packaging of the semiconductor memory itself, it is clear that it will greatly contribute to reducing the cost of electronic devices. Furthermore, since the semiconductor memory according to the present invention is also equipped with an internal ROM configuration address conversion unit, only one address generation circuit is required instead of two, which simplifies the circuit. Therefore, it has the advantage of contributing to miniaturization and cost reduction of electronic devices.

Effects of the Invention As described above, the present invention has two mutually independent storage areas on the same semiconductor substrate, each storage area has a data bus, while there is only one address bus system, and separate address The present invention aims to provide a semiconductor memory that is equipped with a converter and can read and write data at the same time. If the semiconductor memory of the present invention is applied to electronic devices that read and write data at the same time, only one will be needed instead of two, which will reduce implementation costs. It has the advantage of making a large contribution.

[Brief explanation of drawings]

Figure 1 is a diagram showing a conventional example using semiconductor memory, Figure 2 is a diagram showing a conventional example using semiconductor memory.
The figure is a conventional 7022 diagram of a semiconductor memory, and FIG. 3 is a block diagram of a semiconductor memory according to an embodiment of the present invention. 11.12...Storage area, 2Q...Address conversion section, 21.22...Address bus, 31
．． 32...Input/output data bus. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure @2 figure

Claims (2)

[Claims] (1) Having two mutually independent storage areas on the same semiconductor substrate, each of the two storage areas having an input/output data bus, while having only one system of address buses and having an address converter. . A semiconductor memory characterized in that it is possible to simultaneously select different addresses for the two storage areas. (2) Regarding two storage areas, it is possible to write data to one storage area and read data from the other storage area at the same time. semiconductor memory.