JPH0273442A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a status buffer memory by writing only the status of the erroneous data to the status buffer memory and then reading the status out of the buffer memory only when the erroneous data is read out of the buffer memory. CONSTITUTION:In case the input data has no error, the data is stored in an error flag buffer memory 11 and the writing of the data is inhibited to a status buffer memory 6. When the input data has an error, the data is stored in the memory 11 and at the same time only the error status is stored in the memory 6. When the data and the status are read, an error bit is also read out of the memory 11. Then the status is read out of the memory 6 only when the error bit is valid. Therefore it is not required to store the status of a normal state into the memory 6. Thus the capacity of the menory 6 can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device that converts serial data into parallel data, determines the presence or absence of errors in this data, and outputs its status along with the data. be.

[Prior Art] FIG. 2 is a block diagram showing a schematic configuration of a conventional data processing device having a serial data input/output function. In the figure, (1) is a received serial data input terminal;
(2) is a data receiving circuit that receives serial data, (
3) is a data conversion circuit consisting of a shift register that converts serial data to parallel data; (4) is a data buffer memory circuit that stores the converted parallel data; (5) determines whether there is an error in the received data; A status generation circuit that generates status, (6) a status buffer memory circuit that stores the status generated by the status generation circuit (5), and (7) a buffer memory circuit that reads data and status from (4) and (6). (8) is a data read line, and (9) is a status read line.

Next, the operation will be explained. The received serial data to the input terminal (1) is taken into the data processing device by the data receiving circuit (2), converted to parallel data by the data converting circuit (3), and the converted parallel data is stored in the data buffer memory. It is stored in the circuit (4). At the same time, the status generation circuit (5) checks for parity errors, framing errors, overrun errors, etc., generates a status, and stores it in the status buffer memory (6). In this way, the buffer memory (
4) Stored in (6). These stored data and status are read out to the internal bus (7) via the data read line (8) and status read line (9) as required.

[Problems to be Solved by the Invention] Since the conventional data processing device is configured as described above, it is possible to generate a status even for normal data without errors among the received serial data and store it in the buffer memory. Therefore, there was a problem in that a large capacity buffer memory circuit was required.

This invention has been made to solve the above-mentioned problems, and its purpose is to provide a data processing device that can perform error checking, status generation, and storage using a status buffer memory with a minimum capacity. do.

[Means for Solving the Problems] A data processing device according to the present invention is provided with an error flag buffer memory circuit that stores error bits according to the presence or absence of an error in each input data generated in the status generation circuit. When writing data to the data buffer memory circuit, the status is written to the status buffer memory circuit according to the error bit generated by the error flag buffer memory circuit. The configuration is such that reading of the status from the status buffer memory circuit when reading data from the status buffer memory circuit is controlled respectively.

[Function] The data processing device according to the present invention controls writing of the status to the status buffer memory circuit depending on whether the error bit output from the status generation circuit is valid or invalid depending on the presence or absence of an error in the received data. , when reading data from the data buffer memory circuit,
At the same time, reading of the status from the status buffer memory circuit is controlled depending on whether the error bit read from the error flag buffer memory circuit is valid or invalid. Therefore, only the status of erroneous data is written to the status buffer memory circuit, and the status is read from the status buffer memory circuit only when the erroneous data is read from the data buffer memory circuit. Can be done.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing a schematic configuration of an embodiment of the present invention. In the figure, (1) is a reception serial data input terminal, (2) is a data reception circuit, (3) is a data conversion circuit,
(4) is a data buffer memory circuit; (5) determines whether there is an error in the received data, and when there is an error, it generates a valid bit U1U, and when there is no error, it generates an invalid bit II OII, and the status of the data. (6) is a status buffer memory circuit, (7) is an internal bus, (8) is a data read line,
(9) is a status read line, (10) is a status write line, (11) is an error flag buffer memory circuit that stores error bits in correspondence with data, and (12) is an error hit generated in the status generation circuit (5). An error bit write line (13) is used to output to the error flag buffer memory circuit (11) and to control writing to the status backup memory circuit (6).The line (13) reads error bits from the error flag buffer memory circuit (I2). This is an error focus readout line for controlling readout of the status buffer memory circuit (6).

Next, the operation will be explained. The received serial data to the input terminal is taken into the data processing device by the data receiving circuit (2), converted to parallel data by the data converting circuit (3), and the converted parallel data is sent to the data buffer memory circuit (4). ). At the same time, a status generation circuit (5) checks parity errors, framing errors, overrun errors, etc., and generates error bits and status.

If there is no error in the input data, the error bit becomes an invalid bit LL OI+ and the error bit write line (12
) is stored in the error flag buffer memory circuit (11). Furthermore, this invalid bit prohibits writing of the status to the status data buffer circuit (6). In other words, the normal status is invalid. Next, if there is an error in the input data, the error bit becomes a valid bit rr I I+ and is sent to the error flag buffer memory circuit (
11). This valid bit allows writing of the status to the status buffer memory (6), and only error status is stored in the status buffer memory (6).

Each data from the data buffer memory circuit (4) and the status buffer memory circuit (6) to the internal bus (7),
When reading the status, error bits corresponding to the read data are simultaneously read from the error flag buffer memory circuit (11) to the error bit read line (13). If the read error bit is an invalid bit, reading from the status buffer memory circuit (6) is prohibited, and a predetermined status (for example, all O's) is output on the status read line (9). Conversely, if the read error bit is a valid bit, reading from the status buffer memory circuit (6) is permitted, and the error status corresponding to the read data from the status buffer memory circuit (6) is transferred to the status read line (9). ) to the internal bus (7).

In this way, only the error status is stored in the status buffer memory circuit (6), so there is no need to store the normal status in the status buffer memory, and the capacity of the status buffer memory can be reduced.

In the above embodiment, the error flag buffer memory circuit (
11), an error bit read line (13) for controlling reading of the status data buffer memory circuit (6) is shown, but an error bit read line (13) is also provided for the data buffer memory circuit (4). (13) is connected, and when reading data with an error, the error flag from the error flag buffer memory (12) is
Alternatively, the data may be output to the internal bus (7) via the data read line (8).

[Effects of the Invention] As described above, according to the present invention, an error flag buffer memory circuit is provided that stores error bits according to the presence or absence of errors in each input data generated in the status generation circuit, and The status is written to the status buffer memory circuit when writing data to the data buffer memory circuit, depending on the error bit read from the error flag buffer memory circuit. Since the reading of the status from the status buffer memory circuit during data reading is configured to be controlled individually, the capacity of the status buffer memory circuit can be significantly reduced and some hardware can be eliminated, resulting in inexpensive data processing. There is an effect that the device can obtain.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing a schematic configuration of a conventional data processing device having a serial data input/output function. . In the figure, (1) is the received serial data input terminal, (
2) is a data reception circuit, (3) is a data conversion circuit, (4)
) is the data buffer memory circuit, (5) is the status generation circuit, (6) is the status buffer memory circuit, (7
) is the internal bus, (8) is the data read line, (9) is the status read g, (10) is the status write line,
(11) is an error flag buffer memory circuit, (12)
(13) is an error bit write line, and (13) is an error bit read line. The same reference numerals in the figures indicate the same or corresponding parts. Representative Masuo Oiwa Figure Receive serial data input terminal Internal bus data read line Status continuous line Status write line Error bit write line Error bit read, line

Claims (1)

[Claims] a data receiving circuit that receives serial data, a data conversion circuit that converts the received serial data into parallel data, a data buffer memory circuit that stores the converted parallel data, and determines whether or not there is an error in the converted parallel data; A data processing device that includes a status generation circuit that generates and outputs the status, a status buffer memory circuit that stores the status from this circuit, and an internal bus that reads the data and status stored in these buffer memory circuits. An error flag buffer memory circuit is provided to store error bits corresponding to the presence or absence of an error in each input data generated in the status generation circuit, and the data buffer memory The writing of the status to the status buffer memory circuit when writing data to the circuit is determined according to the error bit read from the error flag buffer memory circuit, and the status buffer memory when reading data from the data buffer memory circuit. A data processing device characterized in that reading of status from the circuits is controlled respectively.