JP2009032055A - Data storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data storage device to be commonly used for a plurality of system LSIs for reducing increase in access latency or deterioration in through-put. <P>SOLUTION: This data storage device is provided with a memory mat part being a group of memory cells; at least three types of bus, namely, an address bus for transmitting an address signal to designate a memory word configured of a single memory cell to be accessed or the group of a plurality of memory cells to be simultaneously accessed from the memory mat part, a control bus for transmitting a control signal accompanied by the address signal, and a data bus for transferring data to be read from and written in the memory mat part; and a bus terminal group for connecting the three types of bus groups to the outside. The data bus is configured as a bus of at least two systems capable of executing independent data transfer in parallel. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data storage device used as a temporary storage location of data in a system LSI configured to be mounted inside a television receiver or the like that supports digital broadcasting, and in particular, data usable as an external memory chip. The present invention relates to a storage device.

  In recent years, with the digitization of video processing, so-called digital home appliances such as television receivers that support digital broadcasting are increasingly configured with a plurality of system LSIs mounted therein. Many of these system LSIs use a storage device such as an SDRAM as an external memory chip as a temporary storage location of the data.

  In these memory chips, with the progress of semiconductor manufacturing processes in recent years, an increase in storage capacity and an increase in transfer speed (higher transfer bandwidth) have been realized. This is realized by improving the operation speed at the pins of the memory chip. Therefore, the operating frequency in the data transfer path between the memory chip and the system LSI is higher, and the signal amplitude is becoming smaller. As a result, it has become difficult to connect a single memory chip and a plurality of system LSIs to the same bus and share the memory. In order to enable one-to-one connection, it is required to mount the same number of memory chips on the product. In other words, there is no significant increase in the storage capacity of the memory that is connected to such a system LSI on a one-to-one basis and is required as a temporary storage location for data.

  On the other hand, the bit price of the memory tends to decrease in inverse proportion to the progress of the increase in capacity. This is because the memory chip itself is composed of a memory mat portion whose area is proportional to the memory capacity and an interface portion that is not proportional to the memory capacity. This is because the ratio of the interface unit that is not proportional to the memory capacity to the price of the product is relatively low, which leads to a decrease in the bit unit price. For this reason, small-capacity memories that are not cost-effective are gradually being removed from the market, making it difficult to obtain them.

  Because of these factors, especially in the fields where the required memory capacity does not increase significantly, such as the above-mentioned digital home appliances, the increase in memory capacity realized with the recent progress in semiconductor manufacturing processes described above Rather, it is necessary to mount a high-priced memory having a useless capacity on a plurality of system LSIs on a one-to-one basis, which is a cause of problems in terms of product cost.

Patent Document 1 below describes so-called cascade connection of an external memory and a plurality of system LSIs accessing the external memory.
JP 2006-293591 A

  As described above, in the prior art (Patent Document 1), since an external memory and a plurality of system LSIs accessing the external memory are connected in a so-called cascade, they are accessed from an LSI far from the external memory. In this case, there is a problem that the so-called access latency increases. Furthermore, while one LSI is accessing the external memory, the other LSI cannot access the memory, which causes a problem that the throughput decreases. .

  Therefore, the present invention has been made in view of the above-described problems in the prior art, and the object thereof is to be used in common for a plurality of system LSIs, and the access latency can be reduced. An object of the present invention is to provide a data storage device with little increase or decrease in throughput.

  According to the present invention, in order to achieve the above object, first, a memory mat portion which is a set of memory cells capable of holding at least data, and a single memory cell to be accessed from the memory mat portion Or an address bus for transmitting an address signal for designating a memory word consisting of a set of a plurality of memory cells accessed simultaneously, a control bus for transmitting a control signal associated with the address signal, and the memory mat section A data storage device comprising at least three types of data buses for transferring data to be read from and written to, and a bus terminal group for connecting the three types of bus groups to the outside The data bus is provided with at least two or more buses capable of executing independent data transfer in parallel. It is.

  According to the present invention, in the data storage device described above, the number of bus terminal groups for the address bus is preferably smaller than the number of bus terminal groups for the data bus. It is preferable that only the system is provided. Furthermore, according to the present invention, in the data storage device described above, it is preferable that the memory cells constituting the memory mat portion retain data even when power supply is stopped, or the three types The bus groups preferably operate in synchronization with the reference clock.

  That is, according to the present invention described above, memory chips can be shared by a plurality of system LSIs with almost no decrease in access latency. Further, for an address bus with a small transfer amount, by performing pin sharing, the number of pins of the memory chip can be reduced, and a cost-effective data storage device can be provided. In addition, by configuring the memory of the data storage device as an external memory with a plurality of banks, it is possible to realize parallel access without lowering the throughput even when the access target is a different bank. Exhibits an excellent effect.

  Hereinafter, various embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

  The data storage device according to the first embodiment of the present invention will be described below in detail with reference to FIG. First, in FIG. 1, reference numeral 1 indicates an external memory including a data storage device according to the present invention, and a plurality of systems (two in this example) each access the external memory 1. The LSIs 2 and 3 are connected so as to be commonly accessible via at least three types of bus groups described below. Reference numeral 4 in the figure denotes a timing generation circuit for generating timing information for the external memory 1 and the plurality of system LSIs 2 and 3. In the present embodiment, as shown in the figure, the timing generation circuit 4 includes a clock signal (CLK) 100 serving as a reference clock for the memory access operation and a phase signal (PHASE) 110 obtained by dividing the clock signal by two. And output. Further, each of the system LSIs 2 and 3 includes a memory control circuit therein.

  On the other hand, the external memory 1 includes a controller 10, memory arrays 11 and 12, input / output (I / O) buffers 15 and 16, and the like. In this embodiment, the memory is divided into two memory arrays, that is, the memory array 11 and the memory array 12 according to the most significant bit of the memory address. More specifically, when the most significant bit of the memory address is “0”, the memory array 11 is to be accessed, and when the most significant bit of the memory address is “1”, the memory array 12 is accessed. It becomes a target. That is, these memory arrays 11 and 12 constitute a memory mat section that is a set (memory bank) of memory cells capable of holding data. These memory cells are constituted by SDRAMs that can retain data even when power supply is stopped. However, the present invention is not limited to this, and a non-volatile memory such as a ROM. It is also possible to configure by applying

  Further, inside the controller 10, address buffers 20 and 21 for holding an address input as an address signal 101 described later are provided. Each memory array includes coders 22 and 23, sense amplifiers 24 and 25, and column decoders 26 and 27, respectively.

  Next, a simple memory read (read) sequence will be described below, taking as an example the operation when the system LSI 2 reads data from the external memory 1 whose configuration has been described above. In this example, 8 pieces of 8-bit width data stored in consecutive addresses are read out. The signal waveform at this time is shown in FIG.

  In FIG. 2, reference numeral 100 indicates a reference clock (CLK) for memory access, while 110 indicates that any of the two system LSIs accesses the common external memory 1. A so-called phase signal (PHASE) indicating whether or not it can be activated is shown. Reference numeral 101 in the figure is an address signal (ADDR) for giving a row address and a column address to the external memory 1, and 102 is one system LSI 2 that puts the external memory 1 into an operating state. Reference numeral 106 denotes a chip select signal (CS0 #) for shifting, and reference numeral 106 denotes a chip select signal (CS1 #) for the other system LSI 3 to shift the external memory 1 to an operating state. In addition, reference numeral 103 is a row address strobe signal (RAS #) that specifies the row address issue timing, 104 is a column address strobe signal (CAS #) that specifies the column address issue timing, and 105 is A so-called write enable signal (WE #) indicating that the access type is write (write) is shown. In the present embodiment, these signals 102, 103, 104, 105, and 106 are negative logic signals. In FIG. 2, reference numerals 200 and 202 indicate data signals (DATA0, 1), and 201 and 203 indicate DQS signals (DQS0, 1) as timing information.

  That is, the address signal (ADDR) 101 designates a memory word consisting of a single memory cell to be accessed or a set (memory bank) of a plurality of memory cells accessed simultaneously from the memory mat portion. Is transmitted on the address bus. In addition, a control signal accompanying the address signal is transmitted on the control bus as the various control signals.

  In the cycle (period) in which the phase signal (PHASE) 110 becomes “H (high)”, the system LSI 2 outputs the row address to be accessed to the address signal 101 and simultaneously outputs the row address strobe signal 103 to “L ( Low) ”. The memory array to be accessed is determined by the most significant bit of the row address signal at this time. In this example, the most significant bit of the row address signal is “0”, that is, the memory array 11 is accessed. Thereby, the memory controller 10 of the external memory 1 stores the access when the chip select signal is “L”, that is, the access address from the system LSI 2 in the upper area of the address buffer 20. Thereafter, this address is given to the address decoder 22 of the memory array 11 so that the contents (data) stored in the corresponding row of the memory address 11 are sent to the sense amplifier 24.

  Subsequently, in a cycle (period) in which the phase signal (PHASE) 110 becomes “H (high)”, the system LSI 2 outputs the column address to be accessed to the address signal 101 and simultaneously outputs the column address strobe signal 104. Set to “L”. This column address is stored in the lower area of the address buffer 20. This address is sent to the column decoder 26, and data to be accessed is selected (accessed) from the output of the sense amplifier 24. The selected data passes through the input / output (I / O) buffer 15 and is output as a data signal 200 (DATA) onto the data line (bus). At that time, a DQS signal (DQS0) 201 is also generated as timing information. Thereafter, the data is sequentially output while incrementing the column address. Since the output timing of this data, the role of the DQS signal, and the like are the same as those of a general DDR-SDRAM, the description thereof is omitted here. The number of cycles until the data is output after the column address strobe signal 104 is set to “L (low)” is fixed (that is, a fixed cycle). However, the number of cycles can be changed in advance. is there. Similarly, the number of data output continuously can also be changed.

  Next, as shown in FIG. 3 attached, in the cycle (period) in which the phase signal 110 (PHASE) becomes “L (low)”, the system LSI 3 replaces the system LSI 2 with the external memory 1. Can be accessed. In this case, the chip select signal 106 is used instead of the chip select signal 102, and the address buffer 21 is used instead of the address buffer 20 in the memory controller 10 of the external memory 1. Here, one system LSI 2 uses a space where the most significant bit of the memory address which is the first half of the memory space is “0”, and the other system LSI 3 has the most significant bit of the memory address which is the second half of the memory space is “1”. In other words, the access from the system LSI 3 is always directed to the memory array 12 and the access result passes through the input / output (I / O) buffer 16. It is sent to the system LSI 3.

  In the above example, when the column address strobe signal (CAS #) 104 is set to “L (low)”, the write enable signal (WE #) 105 is held at “H (high)”. The type is read (read) access. On the other hand, when the write enable signal (WE #) 105 is set to “L (low)”, the type is write (write) access. This will be further described with reference to FIG. 4. In the write (write) access, after four cycles have elapsed since the column address strobe signal (CAS #) 104 was set to “L (low)”, the system LSI 2 The write data is output as the data signal (DATA0) 200 on the data bus. Note that the number of cycles from the column address strobe signal (CAS #) 104 to the data output and the number of continuous writing (writing) can be changed. FIG. 4 shows an example of writing eight pieces of data.

  Next, characteristics of the data storage device according to the first embodiment of the present invention, that is, sharing of the external memory 1 by the system LSIs 2 and 3 will be described with reference to FIG. In the first embodiment, the case where there are two system LSIs has been described as an example. However, in principle, the number is not limited. Further, the external memory 1 has been described as a two-bank configuration including the memory arrays 11 and 12, but there is no limitation to this.

  In sharing the external memory 1 by the system LSIs 2 and 3, first, when the phase signal (PHASE) 110 is “H (high)”, one system LSI 2 outputs the row address onto the address bus as the address signal 101, At the same time, the row address strobe signal (RAS #) 103 and the chip select signal (CS0 #) 102 are set to “L (low)”. This row address is stored in the upper part of the address buffer 20 of the memory controller 10.

  When the phase signal (PHASE) 110 becomes “L (low)” in the next cycle, the other system LSI 3 outputs the row address on the address bus as the address signal 101 and the row address strobe signal. The (RAS #) 103 and the chip select signal (CS1 #) 106 are set to “L (low)”. This row address is stored above the other address buffer 21 of the memory controller 10. In this example, the case where the other system LSI 3 starts access in the next cycle accessed by one system LSI 2 is shown, however, the present invention is not necessarily limited to this.

  Next, when the phase signal (PHASE) 110 is “H (high)”, the system LSI 2 outputs the column address onto the address bus as the address signal 101, and the column address strobe signal (CAS #) 104 and the chip. The select signal (CS0 #) 102 is set to “L (low)”. This column row address is stored in the lower order of the address buffer 20 of the memory controller 10.

  When the phase signal (PHASE) 110 becomes “L (low)” in the next cycle, the other system LSI 3 outputs the column address onto the address bus as the address signal 101 and the column address strobe signal ( (CAS #) 104 and chip select signal (CS1 #) 106 are set to “L (low)”. This column address is stored in the lower order of the address buffer 21 of the memory controller 10.

  As described above, in the above embodiment, since the most significant bit of the address stored in the address buffer 20 of the memory controller 10 is “0”, it is used for accessing the memory array 11. The address stored in 21 is used for accessing the memory array 12 because the most significant bit is “1”. In other words, the data read from each memory array 11 or 12 is sent to the respective data bus via the input / output (I / O) buffer 15 or 16, respectively, to the data signal (DATA0 or 1) 200. Or it will be output as 202. At the same time, the timing signal (DQS0, 1) 201 or 203 is output. These data are sent to the system LSI 2 or 3, respectively. Here, since the data signals (DATA0, 1) 200, 202 and the timing signals (DQS0, 1) 201, 203 to the data bus are independent of each other, data is transferred in parallel. Is possible.

  Similarly, write (write) access can be executed in parallel. This will be described below with reference to FIG. The difference from FIG. 5 in the write (write) access operation is that the write enable signal (WE #) 105 is controlled and the data signals (DATA0, 1) 200, 202 and their timing signals ( DQS0, 1) in 201, 203. That is, the write enable signal (WE #) 105 is set to “L (low)” at the same timing as the column address strobe signal (CAS #) 104, so that the current access type is write (write). Is sent to the external memory 1. Further, regarding the data signals (DATA0, 1) 200, 202, the external memory 1 outputs in the above-described read (read) access, whereas the write (write) access, the system LSI 2 or 3 outputs. Will be performed. Similarly, the timing signal (DQS0, 1) 201 or 203 is also transmitted in the same direction as the data. Data sent as a data signal (DATA) 200 on the data bus is written to the memory array 11, and data sent as a data signal (DATA 1) 202 is written to the memory array 12.

  In the above description, the two system LSIs 2 and 3 have been described as executing the same type of access. However, as described above, since these accesses are independent, the same type of access is performed. For example, one system LSI 2 can read (read) the shared external memory 1 and the other system LSI 3 can write (write) to the external memory 1 without being limited to the execution of access. .

  In addition, the external memory 1 can be used as a memory having a double data width by using the chip select signals (CS0 #) 102 and (CS1 #) 106 in a bundle. The connection structure between the external memory 1 and the system LSI 5 at this time (modified example) is shown in FIG. 7 attached, the waveform at the time of read (read) access is shown in FIG. 8, and the write (write) access The time waveforms are shown in FIG. The operation at this time can be the same as that of the conventional DDR-SDRAM, that is, from the viewpoint of compatibility. Further, only one system LSI 5 is shown here for simplicity of explanation, but in the present invention, a plurality of these system LSIs can share the external memory 1 as in FIG. It will be clear that there is.

  First, in FIG. 7, the chip select signal (CS0 #) 102 and the chip select signal (CS1 #) 106 are connected to each other, thereby operating as one chip select signal. As for data, a data bus is constructed with the data signal (DATA1) 202 at the upper level and the data signal (DATA0) 200 at the lower level. In this example, each of the data signal (DATA0) 200 and the data signal (DATA1) 202 has an 8-bit width, and therefore when used together, it is used as a 16-bit width memory. It becomes possible to do. In this case, the timing signal (DQS0, 1) 201 or 203 is also used as a timing signal having a double width.

  That is, in the data storage device shown in FIG. 6 connected as described above, the chip select signal (CS0 #) 102 and the chip select signal (CS1 #) 106 become “L (low)” at the same time. In the row address and the column address applied as the address signal 101 on the address bus, the row address strobe signal (RAS #) 103 and the column address strobe signal (CAS #) 104 become “L (low)”, respectively. The data is written into the address buffers 20 and 21 of the memory controller 10 at the timing. Then, the memory arrays 11 and 12 are accessed by the addresses stored in these address buffers, and then read (read) data obtained by the access passes through the input / output (I / O) buffers 15 and 16. Thus, the data signals (DATA0, 1) 200 and 202 are output on the data bus.

  The write (write) access is the same as described above, and the write enable signal (WE #) 105 is set to “L (low)” when the column address strobe signal (CAS #) 104 becomes “L (low)”. As a result, the system LSI 5 writes (writes) the data signals (DATA0, 1) 200, 202 on the data bus to the corresponding portions of the memory arrays 11, 12.

  Next, a data storage device according to the second embodiment of the present invention will be described with reference to FIG. In addition, the big difference with Example 1 mentioned above is as follows. First, in the first embodiment, the timing generation circuit 4 generates the phase signal (PHASE) 110, and the phase signal (PHASE) 110 is “H (high)” and “L (low)”. The ratio with the period of “is ½. In contrast, in the second embodiment, the system LSI 6 generates the phase signal (PHASE) 110.

  According to such a configuration, the properties of the phase signal (PHASE) 110 can be freely changed as compared with the first embodiment. According to this, for example, in a time zone in which the system LSI 6 needs to execute a large amount of data transfer, the system LSI 6 keeps the phase signal (PHASE) 110 in the “H (high)” state, so that the system LSI 6 The shared external memory 1 can be occupied. Conversely, when the system LSI 6 does not require the external memory 1, the external memory 1 can be released by continuing to maintain the phase signal (PHASE) 110 in the “L (low)” state. Become. As described above, in the data storage device according to the second embodiment, the system LSI can mainly control the use ratio of the shared external memory 1.

  In addition, the waveform signal of each part in the data storage device which becomes the said Example 2 is shown in attached FIG. In this example, the system LSI 6 occupies the shared external memory 1 in the period of 3 cycles in which the phase signal (PHASE) 110 is in the “H (high)” state, but in other periods, Other system LSIs 3 can freely use the external memory 1.

  In the data storage devices of the present invention shown in the first and second embodiments described above, the memory arrays that can be accessed by the respective system LSIs are fixed. However, the present invention is limited to this. There is nothing. For example, the memory array accessible by each system LSI can be freely changed. According to this, a memory space that can be used by each system LSI is expanded, and furthermore, a plurality of system LSIs can perform data communication with each other using the shared external memory.

  Therefore, the configuration of the data storage device according to the present invention for realizing the above will be described with reference to FIG. The third embodiment is different from the first embodiment in that a so-called crossbar switch is provided between the memory arrays 11 and 12 constituting the external memory 9 and the input / output (I / O) buffers 17 and 18 in the third embodiment. 30 is inserted. That is, the function of the crossbar switch 30 makes it possible to connect an arbitrary memory array to an arbitrary input / output (I / O) buffer. According to this, for example, even from the system LSI 17 in the figure, by setting the most significant bit of the address to “1”, not only the memory array 11 but also the memory array 12 can be accessed. It becomes possible.

  However, in the above-described configuration and method, there is a possibility that access from a plurality of system LSIs occurs to one memory array. More specifically, for example, as shown in the signal waveform of each part in FIG. 13 attached, read access from two system LSIs 7 and 8 occurs for one memory array, and as a result, When the two data phases compete in time, the external memory 9 cannot output the data signals (DATA0, 1) 200, 202 on the data bus at the original timing. Therefore, in this third embodiment, ready signals (RDY0, 1) 210, 211 for indicating that data transfer is possible are added. These ready signals (RDY0, 1) are negative logic. Therefore, during a read (read) access, there is a period during which the ready signals (RDY0, 1) are in the “L (low)” state. This is a valid data phase, and the period of the “H (high)” state is an invalid data phase. Therefore, even during the prescribed data transfer timing, effective data transfer is not performed while the ready signal (RDY0, 1) is “H (high)”. Therefore, the system LSI confirms the values (“L” or “H”) of these ready signals (RDY0, 1), and captures data only during the period when the ready signals (RDY0, 1) are “L”. Configured.

  The ready signal (RDY0, 1) can be applied not only to the read (read) access but also to the write (write) access. However, in the third embodiment, similarly to the read (read) access, a situation in which accesses from a plurality of system LSIs concentrate on one memory array may occur during a write (write) access. In such a case, the write (write) destination address is temporarily stored in the address buffers 20 and 21 of the memory controller 19 and the write (write) data is temporarily stored in the input / output (I / O) buffers 15 and 16. However, these buffers cannot be used by other accesses until the write (write) access to the memory array is completed. That is, if the system LSI issues the next memory access during this period, the address and data cannot be held, and so-called transactions are lost.

  Therefore, in the third embodiment, the ready signals (RDY0, 1) 210 and 211 are used in order to prevent the data storage device from the above-described problems. More specifically, at the time of write (write) access, the external memory 9 completes the write (write) operation to the memory array, and the address buffers 20 and 21 and the data buffer are free from other accesses. When ready for use, the ready signal (RDY0, 1) is set to the “L (low)” state for one cycle. On the other hand, the system LSI is configured so that when a write (write) access is issued, the next access is not issued until the ready signal (RDY0, 1) becomes “L (low)”. It is possible to prevent the above-described transaction from being lost.

  In the third embodiment, the number of stages of the address buffer and data buffer is described as being prepared for one transfer. However, the memory access performance of the data storage device can be improved by increasing the number of stages. Is possible.

  In the embodiment according to the present invention described above, it is described that a protocol similar to DDR-SDRAM is used for access to the external memory 1, however, the present invention is not limited to this. . Further, the bit width of data and address is not limited to the above-described embodiment. Further, in the above embodiment, for the sake of simplicity, the description about the write mask at the time of writing (writing) is not performed, but such a mask function is supported by adding a signal for that purpose separately. Is also possible. The data storage device according to the present invention is preferably manufactured by a semiconductor manufacturing process as a single memory chip.

1 is a block diagram showing the structure of a data storage device according to a first embodiment of the present invention, including connections when used as a common memory for a plurality of LSIs. FIG. 2 is a waveform diagram of each part for explaining a simple memory read (read) sequence operation in the data storage device of FIG. 1. It is a wave form diagram of each part for demonstrating the memory read (read) operation | movement in a data storage device. It is a wave form diagram of each part for demonstrating the memory read (read) operation | movement in the said data storage device. It is a wave form diagram of each part for demonstrating the memory read (read) operation | movement in the said data storage device. It is a wave form diagram of each part for demonstrating the write (write) access operation | movement in the said data storage device. FIG. 6 is a block diagram showing a structure of a data storage device as a modification of the first embodiment, including connection when used as a common memory of a plurality of LSIs. It is a wave form diagram of each part for demonstrating access operation in the data storage device which becomes the said modification. It is a wave form diagram of each part for demonstrating access operation in the data storage device which becomes the said modification. It is a block diagram which shows the structure in the case of using the structure of the data storage device which becomes Example 2 of this invention as a common memory of several LSI including a connection. It is a wave form chart of each part for demonstrating the access operation in the data storage device which becomes Example 2 of the said invention. It is a block diagram which shows the structure of the data storage device which becomes Example 3 of this invention including the connection in the case of using it as a common memory of several LSI. It is a wave form chart of each part for demonstrating the access operation | movement in the data storage device which becomes the said Example 3 of this invention. It is a wave form chart of each part for demonstrating the access operation | movement in the data storage device which becomes the said Example 3 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 9 ... External memory 2, 3, 5-8 ... System LSI 4 ... Timing generation circuit 10 ... Memory controller 11, 12 ... Memory array 15-18 ... Input / output (I / O) buffer 20, 21 ... Address buffer 22 , 23 ... row address decoder 24, 25 ... sense amplifier 26, 27 ... column address decoder 30 ... crossbar switch.

Claims (5)

A memory mat portion which is a set of memory cells capable of holding at least data;
An address bus for transmitting an address signal for designating a single memory cell to be accessed or a memory word comprising a set of a plurality of memory cells accessed simultaneously from the memory mat portion;
A control bus for transmitting a control signal accompanying the address signal; and
At least three types of data buses for transferring data to be read from and written to the memory mat unit; and
A data storage device comprising a bus terminal group for connecting the three types of bus groups to the outside,
The data storage device according to claim 1, wherein the data bus is at least two or more buses capable of executing independent data transfer in parallel.   2. The data storage device according to claim 1, wherein the number of bus terminal groups for the address bus is smaller than the number of bus terminal groups for the data bus.   3. The data storage device according to claim 2, wherein only one system of the address bus is provided.   2. The data storage device according to claim 1, wherein the memory cells constituting the memory mat portion are non-volatile capable of holding data even when power supply is stopped. .   2. The data storage device according to claim 1, wherein the three types of bus groups operate in synchronization with a reference clock.

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