JPS6130286Y2 - - Google Patents

Info

Publication number
JPS6130286Y2
JPS6130286Y2 JP1977030940U JP3094077U JPS6130286Y2 JP S6130286 Y2 JPS6130286 Y2 JP S6130286Y2 JP 1977030940 U JP1977030940 U JP 1977030940U JP 3094077 U JP3094077 U JP 3094077U JP S6130286 Y2 JPS6130286 Y2 JP S6130286Y2
Authority
JP
Japan
Prior art keywords
insulating plate
metal film
semiconductor element
lead
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977030940U
Other languages
English (en)
Other versions
JPS53124649U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1977030940U priority Critical patent/JPS6130286Y2/ja
Publication of JPS53124649U publication Critical patent/JPS53124649U/ja
Application granted granted Critical
Publication of JPS6130286Y2 publication Critical patent/JPS6130286Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 この考案は半導体装置に係り、特に半導体素子
をパツケージに装着した形態の半導体装置の改良
に関するものである。
半導体装置には半導体素子を装着し、半導体素
子の端子を外部回路に接続するためのリード導体
が設けられたパツケージが広く用いられている。
第１図は従来の半導体装置の一例を示す平面図
で、第２図は第１図の−線での断面図であ
る。図において、１はアルミナ、ベリリヤ磁器な
どの絶縁物からなる基板、２は基板１と同じ材料
からなり後述の半導体素子を装着するための窓を
有し且つ基板１と重ねて一体化された第１の絶縁
板、３は基板１の上面の第１の絶縁板２の窓の部
分にメタライズによつて形成された金属膜層、４
は金属膜層３を介して基板１に固着された半導体
素子、５は第１の絶縁板２の上面に互いに所定絶
縁距離を保つてメタライズによつて形成された複
数本のリード金属膜であり、上記窓の４辺から両
長辺の外側面に延在して設けられている。６は半
導体素子４の電極端子、７は各電極端子６と各リ
ード金属膜５とを接続するために超音波接着もし
くは熱圧着によつて接合された金、アルミニウム
などの金属細線、８は基板１と同一材質からな
り、第１の絶縁板２の窓より大きな窓を有して各
リード金属膜５の金属細線接続端部が露出するよ
うに第１の絶縁板２上に接着された第２の絶縁
板、９は基板１と第１の絶縁板２と第２の絶縁板
８とからなるこの半導体装置のパツケージ、１０
はパツケージ９の長辺側の外側面に設けられリー
ド金属膜５に銀−銅ロウ材などでロウ接された外
部リード導体である。
従来の半導体装置では、リード金属膜５の金属
細線接続端部は第１の絶縁板２の窓の周囲に四方
に設けられ、これと外部リード導体１０との接続
は、リード金属膜５を第１図に示すようなパター
ンにすることによつて達成されている。
ところで、この種の半導体装置のパツケージ９
は、その幅（図示Ｗ）が7.6mm（300ミル），10.1
mm（400ミル），15.2mm（600ミル）に規格化され
ている。しかるに、上述の従来装置では、半導体
素子４の周辺に各辺とも電極端子６が設けられ、
これに対応して第１の絶縁板２の窓の周囲の各辺
にもリード金属膜５の金属細線接続端部が設けら
れているので、第１の絶縁板２の窓の大きさ、す
なわち半導体素子４の装着面積に制限がある。半
導体素子４のチツプサイズは大きくなる傾向にあ
り、一方、パツケージ９は実装密度を上げるため
に小さいものを使用する要求があるが、上述のよ
うに半導体素子４の装着面積に制御があるので、
チツプサイズが大きくなつた場合、規格のパツケ
ージ９には装着できなくなる。殊に上記パツケー
ジ９の幅方向の寸法の制約が大きい。
この考案はこのような点に鑑みてなされたもの
で、パツケージの長手方向に沿う辺にはリード金
属膜の金属細線接続部と電極端子を設けず、これ
と直角方向の辺にのみリード金属膜の金属細線接
続部と電極端子を設けるようにすることによつ
て、同一外形のパツケージに収納できる半導体素
子のチツプサイズを大きくできるようにすること
を目的とするものである。
第３図はこの考案の一実施例を示す平面図、第
４図は第３図の−線での断面図、第５図は同
じく−線での断面図である。この装置の構成
部品および製造方法は前述の従来装置と殆んど同
じであるが、パツケージの長手方向に沿う辺には
リード金属膜５の金属細線接続部と電極端子６が
設けてない。このような構成によれば、第１の絶
縁板２の上記長手方向に沿う辺にはリード金属膜
５の電極端子６への接続端部を設ける必要がない
ので、第４図に示すように第１の絶縁板２の窓の
幅方向の寸法を第２の絶縁板８のそれと同一にま
で大きくでき、この第１の絶縁板２の窓の面積を
増大できる。従つて基板１上の半導体素子４の装
着面積を広くとれるので、半導体素子４の大きさ
に対する制約は大幅に改善される。
以上詳述したように、この考案によれば絶縁基
板の短辺に沿う方向の辺にのみリード金属膜の金
属細線接続端部と電極端子を設けるようにしたの
で、同一外形のパツケージに装着できる半導体素
子の大きさを大きくでき、従来のパツケージに装
着される半導体素子に比してその寸法上の制約が
大幅に緩和できる。
【図面の簡単な説明】
第１図は従来の半導体装置の一例を示す平面
図、第２図は第１図の−線での断面図、第３
図はこの考案の一実施例を示す平面図、第４図は
その−線での断面図、第５図は同じく−
線での断面図である。 図において、１は絶縁物基板、２は第１の絶縁
板、４は半導体素子、５はリード金属膜、６は電
極端子、７は金属細線、８は第２の絶縁板、１０
は外部リード導体である。なお、図中同一符号は
同一または相当部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 長方形をなしその互いに対向する長辺にのみそ
    れぞれ複数個の外部リード導体が配設された絶縁
    基板と、この絶縁基板上にその長辺に対向２辺が
    平行になるように装着された直方形の半導体素子
    と、上記絶縁基板上に重ねて設けられ上記半導体
    素子を収容する窓を有する第１の絶縁板と、この
    第１の絶縁板上に設けられ一端が上記半導体素子
    の電極端子とそれぞれ金属細線で接続され他端が
    上記外部リード導体へそれぞれ接続されるリード
    金属膜と、上記第１の絶縁板上に重ねて設けられ
    上記リード金属膜の金属細線接続端部を露出する
    窓を有する第２の絶縁板とを有するものにおい
    て、上記絶縁基板の短辺に沿う方向の辺にのみ上
    記リード金属膜の金属細線接続端部と上記電極端
    子を設けたことを特徴とする半導体装置。
JP1977030940U 1977-03-14 1977-03-14 Expired JPS6130286Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977030940U JPS6130286Y2 (ja) 1977-03-14 1977-03-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977030940U JPS6130286Y2 (ja) 1977-03-14 1977-03-14

Publications (2)

Publication Number Publication Date
JPS53124649U JPS53124649U (ja) 1978-10-04
JPS6130286Y2 true JPS6130286Y2 (ja) 1986-09-05

Family

ID=28881545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977030940U Expired JPS6130286Y2 (ja) 1977-03-14 1977-03-14

Country Status (1)

Country Link
JP (1) JPS6130286Y2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58138055A (ja) * 1982-02-12 1983-08-16 Nec Corp 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5110066A (ja) * 1974-07-11 1976-01-27 Takao Nishikawa Kokumotsusenbetsusochi

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5110066A (ja) * 1974-07-11 1976-01-27 Takao Nishikawa Kokumotsusenbetsusochi

Also Published As

Publication number Publication date
JPS53124649U (ja) 1978-10-04

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