JPS6129963A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS6129963A
JPS6129963A JP15057084A JP15057084A JPS6129963A JP S6129963 A JPS6129963 A JP S6129963A JP 15057084 A JP15057084 A JP 15057084A JP 15057084 A JP15057084 A JP 15057084A JP S6129963 A JPS6129963 A JP S6129963A
Authority
JP
Japan
Prior art keywords
data
line
volatile storage
storage unit
volatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15057084A
Other languages
Japanese (ja)
Inventor
Hiroshi Tomita
弘 富田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15057084A priority Critical patent/JPS6129963A/en
Publication of JPS6129963A publication Critical patent/JPS6129963A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To decrease cost by using one set of a controller in common in relation to transmission of data between an upper device and a volatile memory and or transmission of data between a volatile memory and a non-volatile memory. CONSTITUTION:A controller 200 writes the data sent from the upper device 260 through a line 250 into the volatile memory 210 through a line 252, and when the data are sent to the device 260 from a device 210, the data are sent out through a line 253 and a line 251. When the data sent from the device 260 are requested to be kept, the controller 200 writes the data read out from the memory 210 through the line 253 in the non-volatile memory 220 through a line 254, and when read-out is made, the data are read out through a line 255. Thus, it is possible to decrease the cost by using one set of the controller in common concerning to the transmission of data between the upper device and the volatile memory and the transmission of data between the volatile memory and the non- volatile memory.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、揮発性及び不揮発性記憶部を使って上位装置
との間でデータ処理を行なう半導体記憶装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that performs data processing with a host device using volatile and nonvolatile memory sections.

〔従来技術〕[Prior art]

従来、この種の半導体記憶装置は・以下のようなもので
あった。Conventionally, this type of semiconductor memory device has been as follows.

すなわち、第２図に示すように制御部１００は線１５０
を通して上位装置から送られてきたデータを線１５２を
通して揮発性記憶部１２０に書込み、また゛線１５３を
通して該揮発性記憶部１２０から読出したデータを線１
５１を通して上位装置に送ることができる。しかし、前
記揮発性記憶部１２０は障害などで電源が解放してしま
った場合に、記憶しておいたデータを消失してしまうの
で、データを保存したいときには制御部１１０を駆動さ
せる。前記制御部１１０は、線１５４を通して前記揮発
性記憶部１２０かも読出しだデータを線１５５を通して
不揮発性記憶部１３０に書込み、一方線１５６を通して
該不揮発性記憶部１３０からデータを読出すようにしで
ある。That is, as shown in FIG.
The data sent from the host device through the line 152 is written into the volatile storage unit 120 through the line 152, and the data read from the volatile storage unit 120 through the line 153 is written into the volatile storage unit 120 through the line 153.
51 to the host device. However, if the volatile storage section 120 loses power due to a failure or the like, the stored data will be lost, so when it is desired to save data, the control section 110 is activated. The control unit 110 writes data read from the volatile storage unit 120 through a line 154 to the nonvolatile storage unit 130 through a line 155, and reads data from the nonvolatile storage unit 130 through a line 156. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来、データを保存しておくには、第２図から明らかな
ように２つの制御部１００、制御部１１０を必要とする
ため、コスト高となった。Conventionally, in order to store data, two control sections 100 and 110 are required as shown in FIG. 2, resulting in high costs.

本発明の目的は１．上位装置と揮発性記憶部とのデータ
転送を行い、さらに該揮発性記憶部と不揮発性記憶部と
の間でデータ転送を行うことができる１台制御部をもつ
ことにより、上記欠点を除去した半導体記憶装置を提供
することにある。The purpose of the present invention is 1. The above drawbacks are eliminated by having one control unit that can transfer data between the host device and the volatile storage unit, and also between the volatile storage unit and the nonvolatile storage unit. An object of the present invention is to provide a semiconductor memory device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は揮発性記憶素子により構成される揮発性記憶部
をもつ半導体記憶装置において、上位装置から送られて
くるデータを一時的に記憶する揮発性記憶部２１０と、
前記データを保存する不揮発性記憶部２２０と、前記デ
ータを前記揮発性記憶部２１０に書込み、該揮発性記憶
部２１０から読出したデータの上位装置への送出を行い
、さらに前記揮発性記憶部２１０と前記不揮発性記憶部
２２０との間でデータの転送を行う制御部２００から構
成される。The present invention provides a semiconductor memory device having a volatile memory section composed of volatile memory elements, including a volatile memory section 210 that temporarily stores data sent from a host device;
A non-volatile storage unit 220 that stores the data; a non-volatile storage unit 220 that writes the data into the volatile storage unit 210; sends the data read from the volatile storage unit 210 to a host device; The control unit 200 transfers data between the storage unit 200 and the nonvolatile storage unit 220.

〔作用〕 １台の制御部２００を両記憶部２１０，２２０に対し共
用し、上位装置２６０と揮発性記憶部２１０との間、及
び両記憶部２１０，２２０間のデータ転送を行なう。[Operation] One control unit 200 is shared by both storage units 210 and 220, and data is transferred between host device 260 and volatile storage unit 210 and between both storage units 210 and 220.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明する・ 本発明の第一の実施例を示す第１図において、本発明の
半導体記憶装置は、制御部２００、揮発性記憶部２１０
、不揮発性記憶部２２０とから構成されている。制御部
２００は線２５０を通して上位装置２６０から送られて
きたデータを線２５２を通して揮発性記憶部２１０に書
込み、該揮発性記憶部２１０に書込まれたデータを上位
装置２６０に送るときは、線２５３を通して読出したデ
ータを線２５１を通して上位装置２６０に送出する。ま
た上位装置２６０より送られてきたデータを保存したい
ときに制御部２００は線２５３を通して揮発性記憶部２
１０から読出したデータを線２５４を通して不揮発性記
憶部２２０に書込み、一方線２５５を通して該不揮発性
記憶部２２０からデータを読出す・ 本実施例では、データ転送線を単方向性（線２５〇−２
５１、線２５２−２５３　、線２５４−２５５　）とし
て扱ったが、双方向性でも良い。Next, the present invention will be described in detail with reference to the drawings. In FIG. 1 showing a first embodiment of the present invention, the semiconductor memory device of the present invention includes a control section 200, a volatile storage section 210,
, and a nonvolatile storage unit 220. The control unit 200 writes data sent from the host device 260 through the line 250 to the volatile storage unit 210 through the line 252, and when sending the data written to the volatile storage unit 210 to the host device 260, The data read out through line 253 is sent to host device 260 through line 251. Furthermore, when it is desired to save data sent from the host device 260, the control section 200 sends data to the volatile storage section 2 through the line 253.
Data read from 10 is written to the non-volatile storage unit 220 through the line 254, and data is read from the non-volatile storage unit 220 through the line 255. In this embodiment, the data transfer line is unidirectional (line 250- 2
51, lines 252-253, and lines 254-255), but they may be bidirectional.

〔発明の効果〕〔Effect of the invention〕

本発明には以上説明したように、上位装置と揮発性記憶
部とのデータ転送、および揮発性記憶部と不揮発性記憶
部との間のデータ転送を、１台の制御部を共用して行な
うようにしたので、コストを低減できるという効果があ
る。As explained above, in the present invention, data transfer between a host device and a volatile storage unit, and data transfer between a volatile storage unit and a non-volatile storage unit are performed by sharing one control unit. This has the effect of reducing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

一第１図は本発明の一実施例を示すブロック図、第２図
は従来装置のブロック図である。 ２００・・・制御部　　　　　２１０・・・揮発性記憶
部２２０・・・不揮発性記憶部　２６０・・・上位装置
特許出願人　　日本電気株式会社 馬１図1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional device. 200...Control unit 210...Volatile storage unit 220...Nonvolatile storage unit 260...Upper device patent applicant NEC Corporation Ma 1 Figure

Claims (1)

【特許請求の範囲】[Claims] （１）揮発性記憶素子により構成される揮発性記憶部を
もつ半導体記憶装置において、データを一時的に記憶す
る揮発性記憶部と、前記データを保存する不揮発性記憶
部と、上位装置より送られてきたデータを前記揮発性記
憶部に書込み、該揮発性記憶部から読出したデータの上
位装置への送出を行い、さらに前記揮発性記憶部と前記
不揮発性記憶部との間でデータの転送を行う制御部とを
有することを特徴とする半導体記憶装置。(1) In a semiconductor memory device having a volatile memory section composed of volatile memory elements, the volatile memory section temporarily stores data, the non-volatile memory section stores the data, and the data is sent from the host device. writing the received data into the volatile storage section, sending the data read from the volatile storage section to a host device, and further transferring data between the volatile storage section and the non-volatile storage section. What is claimed is: 1. A semiconductor memory device comprising: a control section that performs the following operations.
JP15057084A 1984-07-20 1984-07-20 Semiconductor memory device Pending JPS6129963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15057084A JPS6129963A (en) 1984-07-20 1984-07-20 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15057084A JPS6129963A (en) 1984-07-20 1984-07-20 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6129963A true JPS6129963A (en) 1986-02-12

Family

ID=15499774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15057084A Pending JPS6129963A (en) 1984-07-20 1984-07-20 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6129963A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9017769B2 (en) 2009-12-14 2015-04-28 Pro-Teq Surfacing (Uk) Ltd Method and apparatus for applying a coating to a surface

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184529A (en) * 1975-01-21 1976-07-23 Omron Tateisi Electronics Co
JPS58180000A (en) * 1982-04-14 1983-10-21 Toshiba Corp Computer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184529A (en) * 1975-01-21 1976-07-23 Omron Tateisi Electronics Co
JPS58180000A (en) * 1982-04-14 1983-10-21 Toshiba Corp Computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9017769B2 (en) 2009-12-14 2015-04-28 Pro-Teq Surfacing (Uk) Ltd Method and apparatus for applying a coating to a surface

Similar Documents

Publication Publication Date Title
KR20040054936A (en) Composite memory device
JPS6129963A (en) Semiconductor memory device
JPS61144789A (en) Semiconductor storage device
JPS6198469A (en) Inter-microprocessor communications system
JP2904266B2 (en) Memory connection controller that can cope with bus degradation
JPS6126162A (en) Input/output control method
JPS6269347A (en) Direct memory access controller
JP3323430B2 (en) Communication control device
JPH02132566A (en) Image data transferring device
JP2884943B2 (en) Address arbitration circuit
JPS61134859A (en) Backup controlling system of memory
JPS6121542A (en) Data transfer device
JP2000132498A (en) Dma transfer controller
JPS63245745A (en) Buffer storage controller
JPS63301348A (en) External memory controller
JPS61248149A (en) Data transfer controlling system between memories
JPH047771A (en) Composite system
JPS62281042A (en) Semiconductor memory device
JPS61272853A (en) Data transfer system
JPS62250574A (en) Magnetic disk controller with automatic journal function
JPS61210464A (en) Data buffer device
JPS6125260A (en) Double storage processing system using incorporated program
JPH03266052A (en) Information processing system
JPH04192197A (en) Semiconductor memory device
JPH01300358A (en) Information transfer system