JPS58180000A - Computer system - Google Patents

Computer system

Info

Publication number
JPS58180000A
JPS58180000A JP57061991A JP6199182A JPS58180000A JP S58180000 A JPS58180000 A JP S58180000A JP 57061991 A JP57061991 A JP 57061991A JP 6199182 A JP6199182 A JP 6199182A JP S58180000 A JPS58180000 A JP S58180000A
Authority
JP
Japan
Prior art keywords
external storage
storage device
power supply
semiconductor
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57061991A
Other languages
Japanese (ja)
Inventor
Tatsuo Ishikawa
達夫 石川
Yasuo Kaneko
金子 泰郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57061991A priority Critical patent/JPS58180000A/en
Publication of JPS58180000A publication Critical patent/JPS58180000A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To hold assuredly the contents of storage of an external conductor storage device with an auxiliary power supply of small capacity, by providing a power supply state detecting circuit to an external storage controller and setting the capacity of the auxiliary power supply at a level for transfer of data when the power supply is cut off. CONSTITUTION:A nonvolatile external storage device 8 is connected to a semiconductor external storage device 5 via an external storage controller 7. At the same time, a power supply detecting circuit 20 is provided to the controller 7 to detect the make/break state of the system power supply. The controller 7 transfers a data on the storage contents of the device 5 to the device 8 on the basis of a power supply detecting signal which is delivered when the power supply is cut off. The capacity of the auxiliary power supply is set at least at a level for transfer of data when the power supply is cut off.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、電子計II!!I休あるいけ電子計算機を利
用した各種システムに係り、%に電源の供給がしゃ断さ
れた場をに外部記憶懐贋の格納内容を自動的に保持しう
るようにした電子計算機システムf関する、 〔発明の技術的背景〕 従来、電子計算機システムにおける外部記憶装FIKは
、磁気ディスク、磁気ドラム等の回転系の記憶装置が用
いられていた。一方、今日では情報量の増大、事務処理
の能事化#−より電子計*鴫システムの処gJ能力、#
PK処理達廖の向上が要求されている、しかしながら、
上述の口転系の1情4!−のアクセス時間は一般に数t
ormt4〕稈電であって決して高速なものでけ々い。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electronic meter II! ! Regarding various systems using electronic computers, it is related to computer systems that are capable of automatically retaining the stored contents of external memory in the event that the power supply is cut off. TECHNICAL BACKGROUND OF THE INVENTION Conventionally, as an external storage device FIK in a computer system, a rotating storage device such as a magnetic disk or a magnetic drum has been used. On the other hand, today, with the increase in the amount of information and the fact that administrative processing has become a formality, the processing ability of electronic meter systems has increased.
Improvement of PK processing efficiency is required, however,
The above-mentioned oral story 4! - access time is generally several t
ormt4] It's a culvert, so it's definitely not a high-speed one.

そこで、最近では#!榊的アクセス動作を伴わす、!貴
的にアクセス時間のないeI)、型外s1情装Wとして
、半導体記憶1子を用いた、いわゆる半導体外部記憶装
置が採用されるようになってきた、ここで、従来の電子
計算轡システムの一般的な析1[成を哨1Δに示す。隼
1闇にシいて、中央処fMIIII(以下、cpU)l
trはバヌ2を介し、て主記憶装+11’lが接続され
ている。さらに、パス2KFi外部紀憶1vIl−装置
1F4を介【て平導体外部紀情装置F3が接続されてい
る、外部1憧制制装豐4け、CPUIの指令に基づき半
導体外部配憶装置F5と主記憶装!F3間のデータ転送
を制御するもめである、 〔背景技術の間頭点〕 上述しtk#導体外剖F憶肺臂4け、高速アクセス、大
容量化等の点で優れているが、その1情原理より供給電
源が御所されると記憶自答が揮発してし重うという欠点
を有する。かかる欠点を補うtめに、従来ではバッテリ
ー等の補助wagを予め設けておき、停電と同時に自動
的にバッテリー電源に切換ねるようにしている。しかし
、バッテリー電、源のW、a供給能力にけ隅間があり、
記憶装置が大容量であったり、停電が長時間に及ぶ場合
KFi配憶内容を消失することがある。
So recently, #! Accompanied by Sakaki-like access behavior! (eI) with no access time, so-called semiconductor external storage devices using one semiconductor memory have come to be adopted as non-standard S1 information W. Here, conventional electronic computing systems A general analysis of 1 [formation is shown in 1Δ. Hayabusa 1 In the darkness, Central Office fMIII (hereinafter referred to as cpU)
The main storage unit +11'l is connected to tr via Vanu2. In addition, the external 1 external storage device F3 is connected via the path 2KFi external storage device 1vIl-device 1F4, and the semiconductor external storage device F5 is connected to the external storage device F3 based on the CPU command. Main memory! It is a problem to control data transfer between F3s. [Highlights of background technology] Although the above-mentioned TK# conductor has four external memory arms, high-speed access, and large capacity, etc. Due to the principle of one-sidedness, it has the disadvantage that when the power supply is controlled, the memory becomes volatile. In order to compensate for this drawback, conventionally, an auxiliary power supply such as a battery is provided in advance so that the system automatically switches to battery power at the same time as a power outage occurs. However, there is a gap in the battery power source's W and A supply capacity.
If the storage device has a large capacity or if the power outage lasts for a long time, the KFi storage contents may be lost.

〔発明の目的〕[Purpose of the invention]

したがって、本発明は小容量の補助電源で確実に半導体
外部記憶装置の格納内容を保持しうるよう構成され+W
子針gmシステムを提供することを目的とする、 〔発明の概要〕 上記目的を達成するために、本発明による電子計X帰シ
ステムは、半導体外部P憶装置に対し外部記憶制御ll
I装菅を介して接続された不揮発性の外部記憶装置を設
け、かつ、外部記憶装置装WIIKけシステムのW源の
状9(投入または速断)を検出す石W脣衿出回路を設け
、W渾漉断時にお0て1(」力される電源検出信号KJ
cづき々(部鼾憧制机装胃により半導体外!記憶装置の
格納内容を不揮発性外部記憶装置iKデータ転送するよ
うにし1、補助電源の容量は少なくともW―遮断時にお
けるご−々転送晰作に必要な本のとした点に特徴を有す
る〔′発明の実施例−1 す下、本P明を図示する実施例C(J?′づ+−,−)
’r、1ll15町する、 〈システムの全体構成、\ 杭2図に本発明による市1子計算轡7・ステ・、d)全
体構成の概要を示す、なお、@2ダC(おいて−1図と
重複する部分にけ同一の符号を付L7てそf′駁明は省
略する 第2図において、パス2に接続された外部記憶制(資)
装#7には不揮発性外部F情装置8が枡絆さhている。
Therefore, the present invention is configured so that the contents stored in the semiconductor external storage device can be reliably retained with a small capacity auxiliary power supply.
[Summary of the Invention] In order to achieve the above object, an electronic counter system according to the present invention provides an external memory control system for a semiconductor external memory device.
A non-volatile external storage device connected through the I system is provided, and a power output circuit for detecting the state of the W source (on or quick disconnection) of the external storage device system is provided; The power supply detection signal KJ that is output at 0 and 1 (" when W pumping is cut off)
The storage contents of the storage device are transferred to the non-volatile external storage device iK, and the capacity of the auxiliary power supply is at least W. It is characterized by the fact that it is a book necessary for the production of the invention.
'r, 1ll15 Machi, <Overall system configuration, \ Figure 2 shows an overview of the overall configuration of the city 1 child calculation according to the present invention. In Figure 2, parts that overlap with those in Figure 1 are given the same reference numerals and L7 and f' are omitted.
A non-volatile external information device 8 is connected to the device #7.

この接続により不揮発性外剖計“情装降□8と半導体P
憶装F5とけ外部P憧制臀装聞7を通じて接続関係1て
あり、外剖記憶制Pi11!紡贅7の一1飢により双方
向にデータ転送が可能となっ(L、−+ Rこれらの半
導体配憶装#5、外部1憧制制装豐7シよび不揮発性外
部記憶装置8にはシステム電源の辿断時において電源を
供給する補助電lW9が接続されている。
With this connection, the non-volatile external analyzer “Insou □8” and the semiconductor P
There is a connection relationship 1 through memory F5 and external P yearning system buttock hearing 7, and external memory system Pi11! Data transfer is now possible in both directions due to the first and second functions of spindle 7 (L, -+R). An auxiliary power supply IW9 is connected to supply power when the system power supply is disconnected.

く各構成要、素〉 外S配憶制御装置Ii7の具体例を杭3図に示す。Each component, element A specific example of the external S storage control device Ii7 is shown in Figure 3.

躯3図において、IOはデータ転送制御の中枢機能を果
たすデータ転送コントローラを示している。
In the 3-dimensional diagram, IO indicates a data transfer controller that performs the central function of data transfer control.

このコれトローラ10はパスライン11およびアダプタ
12 、13 、14を介してO’PtT1、半導体外
部記憶装置5、不揮発性外部記憶装置8とそれぞfL接
続されている。tた、コントローラ10は半導体外部配
憶1!115と不揮発性外部記憶装デ8間の転送データ
を一旦格納するデータバッファメモリ15ヲ備λてシリ
、パスライン11を介して接続されている。
The controller 10 is fL connected to the O'PtT 1, the semiconductor external storage device 5, and the nonvolatile external storage device 8 via the pass line 11 and adapters 12, 13, and 14, respectively. In addition, the controller 10 includes a data buffer memory 15 for temporarily storing data transferred between the semiconductor external storage 1!115 and the nonvolatile external storage device 8, and is connected via a path line 11.

16.1)、 18 、19け各要緊の動作を制御する
ための制御信号を伝達する制御線を示している。
16.1), 18, and 19 show control lines for transmitting control signals for controlling each important operation.

コントローラ1(ltjシステム1に源(一般tut、
AC商用電gりの状!(投入または遮断)を検出する電
源検出回路かを備えている、この電源検出!i5′回路
加け、アダプタ12を介して入力さすするCPU1@か
らのWL源湾断に牟づ〈割込信号を検索し、内容が電源
−断f基づ〈呪のである場合に輸出信秀を発生する。こ
の檜出信号忙よりコントローラIOは後述するデータ転
送動作介開始する不m発性外部記憶装WjI8としては
、半導体外部1憶斐It’sの1憶容量を有する必要が
あり、堅9時での使用という点を考えればアクセス時間
の短い本のがよい、具体的には磁気ディスク、磁気テー
プを用いた配憶装置を用いることができる、補助W#9
としては、少なくとも停電時において外部記憶制御装置
7、半導体外部1憶装W5、不揮発性外部記憶制御装#
8を駆動し、かつ半導体外mt’ff寝贋5から不揮発
性外部紀情制膏装聞8へのデータ転送が完Tするまで動
作を継続しつる電力を供給しつる能力を有することが必
要とされる。具体的には、バッチl−1自家発!設備鴫
が弔いらねみ、 〈動作〉 次に動作′gr説明する。重ず、通常時(雫澤市営時)
においては、その電子計算磯システムに与えられた仕事
を興行しており、配憶データの転送動作に着目すれば、
外部記憶制御装WI7は先にも述べた如く、0PUIの
指令に基づいて転送制御を行う。
controller 1 (ltj system 1 source (general tut,
AC commercial electricity condition! This power supply detection circuit is equipped with a power supply detection circuit that detects (on or off)! i5' circuit is added, the WL source from CPU 1 inputted via adapter 12 is searched for the interrupt signal, and if the content is based on the power supply disconnection f, it is exported by Nobuhide. Occur. From this signal, the controller IO must have a memory capacity of 1 memory external to the semiconductor as the non-volatile external memory WjI8 that starts via the data transfer operation described later. Considering the use of books, books with short access times are better.Specifically, storage devices using magnetic disks and magnetic tapes can be used.Auxiliary W#9
At least during a power outage, the external storage control device 7, the semiconductor external storage W5, and the non-volatile external storage control device #
It is necessary to have the ability to drive the non-semiconductor mt'ff board 5 and continue operation until the data transfer from the non-volatile external data transfer device 8 is completed. It is said that Specifically, Batch 1-1 in-house production! I am sorry for the inconvenience. <Operation> Next, I will explain the operation. Heavy, normal time (Shizuzawa City time)
, the electronic computing system is performing the work given to it, and if we focus on the transfer operation of the stored data,
As mentioned above, the external storage control device WI7 performs transfer control based on the command of 0PUI.

次に1何らかの原因によりシステムに電源が供給されな
くなったとするうこの場合の動作を第48iQK示すフ
ローチャートを参照して以下説明する、コントローラ1
0は常時0PUIからの割込の有無を検索している(第
4図、ステップ100)、いま、アダプタ12を介して
割込みが入力され+4のとし、その割込信号の内容は電
源検出回路かにより判断される(ステップ200)。判
断の結果、電源−断である場合(ステップ200. Y
]ff18 ’)、コントローラ10は制御ll11s
18を通じてアダプタ13に読取命令を与え、半導体外
部記憶装置15に格納されているデータを順次読み出し
て−1データバツファメモリLSK格納する(ステップ
400)。次いでコントローラ10は制御線19を通じ
てアダプタ14に書込み命令を与え、データバッファメ
モリ15 K @納されたデータを読力、出L7て不呵
7住外部紀憧勢・智8に転送し、格納するでステップ5
00)、そσ)閣の転速回数Yけカウントさねでおり(
ステラ1゜600)、全データ転速回数(y、、n)に
4しないmnはステップ700を介して十Fステップ4
00と500が一邂される7、ステップ700け 種の
カウンタであり、転送(ロ)a]i伊ごとにデクリメン
ト川・Zルスを発生する、なお、このY傭はステップ3
00でセットされる。
Next, controller 1 will be described below with reference to a flowchart showing the 48th iQK operation in the case where power is not supplied to the system for some reason.
0 is constantly searching for the presence or absence of an interrupt from 0PUI (Fig. 4, step 100). Now, an interrupt is input via the adapter 12 and the value is +4, and the content of the interrupt signal is determined by the power supply detection circuit. (Step 200). If the result of the judgment is that the power is turned off (step 200. Y
]ff18'), the controller 10 controls ll11s
A read command is given to the adapter 13 through the adapter 18, and the data stored in the semiconductor external storage device 15 is sequentially read out and stored in the -1 data buffer memory LSK (step 400). Next, the controller 10 gives a write command to the adapter 14 through the control line 19, and transfers the stored data to the data buffer memory 15K, output L7, and stores it in the data buffer memory 15K. Step 5
00), σ) The number of rotations of the cabinet Yke count Sanedori (
Stella 1゜600), mn that is not 4 in the total data rotation number (y,, n) is passed through step 700 to 10F step 4
00 and 500 are collided in step 7. It is a counter of 700 kinds, and it generates a decrement river/Zrus for every transfer (b)a]i. Note that this Y is a counter of step 700.
Set to 00.

このようにし7て、全データの転送が終了するとカウン
タ(ステップ600)の伊yFiy−0となり、転送動
作が終了する(ステップ800)っかくして、システム
電源が御所され石と、半導体外部1憶装#5の格納デー
タは全て不!を性れl!を記憶襞j8に転送路K(され
るので、消失することはなく、確実に保持さねるっ 〈変形例〉 以上の説明けW源−断時について説明し★が、本発明は
一旦W源が連断し、次いで回復したとき(つまり、投入
IB)K格納データを再び半導体外部記憶装置5側に戻
すよう構成することが町靜である。
In this manner, when all data transfer is completed, the counter (step 600) becomes yFiy-0, and the transfer operation is completed (step 800). All stored data in #5 is invalid! Have a good time! is stored in the transfer path K (in the storage fold j8), so it will not disappear and will be reliably retained. (Modification) The above explanation describes the case when the W source is disconnected, but in the present invention, once the W source is It is best to configure the K storage data to be returned to the semiconductor external storage device 5 side when it is disconnected and then recovered (that is, input IB).

その場合には、電源検出回路Iを投入時割込みの検出を
可能ならしめ、かつそれに応じて上記実施例の逆の動作
を行うプログラムをコントローラ10に股!しておけば
よい。
In that case, a program can be installed in the controller 10 that enables the power supply detection circuit I to detect an interrupt when turned on, and that performs the reverse operation of the above embodiment accordingly. Just do it.

〔発明の効果〕〔Effect of the invention〕

v上の通り、本発明によれば、半導体外部1憶碑贋の格
納データを格納可能な不揮発性外部記憶伸管を外部記憶
制御装置を介してm続し、外部記憶制御装置に#11j
y!、状聾を検出する市、源檜出回路を設けるとと本に
少々くとも〒混溶断時に半導体外部1憶itの格納デー
タを不揮発性外部記憶装ドに転送制御する帰能をもたせ
、力・つ少なくと龜とわらの4!!−碑WIを駆動し、
そして上記データ転送が終了す石までの間電力供給しう
る補助電源を備えたことにより、次の如き効果を奏する
As described above, according to the present invention, a non-volatile external storage tube capable of storing data stored in a semiconductor external storage memory is connected via an external storage control device, and #11j is connected to the external storage control device.
Y! By providing a circuit that detects the state of deafness, it is possible to at least have the ability to control the transfer of 100 million liters of data stored outside the semiconductor to a non-volatile external storage device in the event of a mixed fuse.・4 of the few and the bell and the straw! ! - drive the monument WI;
By providing an auxiliary power source that can supply power until the end of the data transfer, the following effects are achieved.

■ 電源異常時における格納データの保存は上位システ
ムのcpaの制御かし虻、外訂装彎側で単独で行うこと
がで!石。このこと#′:tタヌテム設計、製作上上位
装置IFIIllKwg1.異常忙よる格納データ保存
の面を考膚しなくてよいことを11F味す丞。したがっ
て、システム構成の製作が容具となり、かつ小型化も可
卵となる。
■ Saving stored data in the event of a power failure can be done independently by the host system's CPA control system or external system! stone. This #':t Tanutem design, production upper-level device IFIIllKwg1. Jo on the 11th floor realized that he didn't have to think about saving data because he was extremely busy. Therefore, the production of the system configuration becomes a problem, and miniaturization is also possible.

■ 駆動するのは外部装置側の与でよく、しtがって補
助電源の客量が小さくてよい。このことは、補助市、g
!、の小型化のみならず、システム−成のコンパクトイ
ヒ(で寄与し、製遺→ヌトの低域が可卵となる。
(2) It may be driven by an external device, and therefore the amount of auxiliary power supply may be small. This means that the subsidiary city, g
! This not only contributes to the miniaturization of the system, but also contributes to the compact size of the system, making the low range of the original → natural range more flexible.

かくして、本発明によれば、小容緊の補助W源にて確実
に半導体外部記憶装置の格納データを保持しうる1、子
計1[システムを枡供することができる。
Thus, according to the present invention, it is possible to provide a system that can reliably hold data stored in a semiconductor external storage device using a small-sized auxiliary W source.

【図面の簡単な説明】[Brief explanation of the drawing]

糖1図は従来一般の電子訓算祷ンステムのrt*ブロッ
ク図、蒙2!21Fi掌発明による電子針算燭システム
の概要ブロック瞑、輌3図は本発明における外部配憶制
m装胃の一成例を示すブロック闇、第4陶は爾源−断晴
における外部F憧制例装廖の動作を示すフローチャート
図である。 1・・CPU、3・・・主紀憧装冒、5・・・半導体配
憶@!1. 7・・・外部記憶制(資)装置、8・・・
不揮発性外部記憶装置、9・・・補助電源、15・・・
データノくラフアメモリ、
Figure 1 is an RT* block diagram of a conventional general electronic learning system, Figure 2 is an overview block diagram of an electronic candlestick system invented by the palm of the hand, and Figure 3 is a block diagram of an external memory system according to the present invention. The fourth example is a flowchart showing the operation of the external F admiration system in the block darkness and clear light. 1...CPU, 3...Shiki's dream adventure, 5...Semiconductor memory @! 1. 7... External storage system (capital) device, 8...
Non-volatile external storage device, 9... Auxiliary power supply, 15...
data nokura memory,

Claims (1)

【特許請求の範囲】 l システムの統括制御を行う中央処理装置と、前記中
央処理装置に接続された主記憶装置と、前記主記憶装置
の格納内容を格納可断な半導体外部配憶装置と、 #1半導体外部記憶装置の格納内容を格納可卵な不揮発
性外部配憶装置と、 前配中央処理装醍の指令に基づいて千配憶懐曾と半導体
外部記憶装置間のデータ転送を劃−し、かつシステムに
対する電源の投入tたは達断状紗を検出する電源検出回
路を有し、その検出信*に基づき前記半導体外部記憶装
置と不揮発性外部記憶装置間のデータ転11!管制御す
る外部V憶制御装置と、 システムに対する電源の連断時Ks?いて少なくとも前
1半導体外部記憶装置、不揮発性外部記憶at、シよび
外部記憶制御装@に対して爾fli、を供給する補助市
源と、 を備えたことを善徴とする電子計算機システム、2、特
許請求の範囲IIII項記軟のシステムにおいて、外部
紀憧制御装朦は、半導体外部記憶装置と不揮発性外部記
憶装置間の転送データを一旦格納するデータバッファメ
モリを有することを特徴とする電子計算機7ステム。
[Scope of Claims] l A central processing unit that performs overall control of the system, a main memory device connected to the central processing unit, and a semiconductor external storage device capable of storing the contents stored in the main memory device; #1 A non-volatile external storage device that can store the stored contents of the semiconductor external storage device, and data transfer between the semiconductor external storage device and the semiconductor external storage device based on instructions from the front-end central processing unit. It also has a power supply detection circuit that detects whether power is turned on or off to the system, and data transfer between the semiconductor external storage device and the nonvolatile external storage device is performed based on the detection signal*. Ks when disconnecting the power supply to the external V memory control device and the system? an auxiliary source for supplying at least the semiconductor external storage device, the non-volatile external storage at, and the external storage control device; , Claim III provides an electronic system characterized in that the external storage control device has a data buffer memory that temporarily stores data transferred between the semiconductor external storage device and the non-volatile external storage device. Calculator 7 stem.
JP57061991A 1982-04-14 1982-04-14 Computer system Pending JPS58180000A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57061991A JPS58180000A (en) 1982-04-14 1982-04-14 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57061991A JPS58180000A (en) 1982-04-14 1982-04-14 Computer system

Publications (1)

Publication Number Publication Date
JPS58180000A true JPS58180000A (en) 1983-10-21

Family

ID=13187166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57061991A Pending JPS58180000A (en) 1982-04-14 1982-04-14 Computer system

Country Status (1)

Country Link
JP (1) JPS58180000A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045857A (en) * 1983-08-24 1985-03-12 Hitachi Ltd Data holding system of semiconductor file
JPS6129963A (en) * 1984-07-20 1986-02-12 Nec Corp Semiconductor memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184529A (en) * 1975-01-21 1976-07-23 Omron Tateisi Electronics Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184529A (en) * 1975-01-21 1976-07-23 Omron Tateisi Electronics Co

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045857A (en) * 1983-08-24 1985-03-12 Hitachi Ltd Data holding system of semiconductor file
JPH0241776B2 (en) * 1983-08-24 1990-09-19
JPS6129963A (en) * 1984-07-20 1986-02-12 Nec Corp Semiconductor memory device

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