JPS6129553B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a load transistor is provided within a semiconductor substrate.

In general, traditional embedded load logic
Logic) type semiconductor devices, particularly integrated circuit devices of this type, are manufactured using a complementary type (C-MOS) process. (1980, IE ³ ISSCCC
SESSION IVP56) Complementary type (C-MOS)
Similar to semiconductor devices, the potential of the well layer (buried layer) was grounded. The reason why the buried layer potential is grounded in complementary semiconductor devices is that the well layers are formed separately, so if you try to apply a potential different from the ground, the ground line (Ground line) ) to achieve high packing
density) is not achieved. This is also because there is no problem even if the well layer is grounded.

However, embedded load logic (Buried Load logic)
Logic) uses a Junction Field Effect Transistor as a load, so if the well layer is grounded, the so-called load channel formed by the Junction Field Effect Transistor is narrowed. There is a problem in that the back bias (BaCk Bias) effect significantly deteriorates the load characteristics and reduces the delay time current consumption product (Power-Delay product). As a result, high-speed, high-efficiency operation of the integrated circuit is hindered.

The present invention has been made in view of these points,
The present invention provides a semiconductor device that achieves high-speed operation by improving the degree of integration and load characteristics.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1D is a cross-sectional view of one embodiment of the present invention. In the figure, 1 is a P conductivity type semiconductor substrate. A field oxide film 2 is formed in a predetermined region of a semiconductor substrate 1. As shown in FIG. Directly below the field oxide film 2 and in the entire area of the semiconductor substrate 1 partitioned by the field oxide film 2, a P conductivity type impurity region 3 is formed except for a region where a second impurity layer 5, which will be described later, is to be formed. A first impurity layer 4 of N conductivity type is formed in the impurity region 3 of the active region surrounded by the field oxide film 2 . A first impurity layer 5 of N conductivity type extends from the semiconductor substrate 1 surrounded by the impurity region 3 to the impurity region 3 . A gate electrode 7 is formed on the surface of the impurity region 3 sandwiched between the first and second impurity layers 4 and 5 with a gate oxide film 6 interposed therebetween. A CVD-SiO ₂ film 8 having a predetermined thickness is formed on the exposed surfaces of the gate electrode 7, the first and second impurity layers 4 and 5, and the field oxide film 2. In the impurity region 3 and the first and second impurity layers 4 and 5,
Respective lead electrodes 10, 11, and 12 are formed through contact holes 9 formed in the CVD-SiO ₂ film 8. Electrical extraction type 10, 11, 12 and
A protective film 13 is formed on the exposed surface of the CVD-SiO ₂ film 8.

According to the semiconductor device 14 configured in this way, the second impurity layer 5 and the impurity region 3 formed in the active region of the semiconductor substrate 1 drive the active region.
A junction field effect transistor serving as a load for the MOS transistor is formed, and the impurity region 3 is formed integrally over the entire semiconductor substrate 1 except for a predetermined region, so that the potential of the buried layer 3, which is different from the power supply potential, is specially controlled. It is possible to improve the degree of integration by eliminating the need for wiring and supplying it to the buried layer 3. Note that the gate of the junction field effect transistor serving as a load is in the impurity region 3, and the source is in the second impurity layer 5.
The drain is a portion of the semiconductor substrate 1, and the region of the semiconductor substrate 1 between the two impurity regions 3, 3 is a channel.

In addition, by setting the potential of the impurity region 3 to a negative potential, the influence of the electric field on the channel of the junction field effect transistor serving as the load is alleviated, and the so-called back bias effect is suppressed. ) Delay time current consumption product (Power-Delay)
It is possible to achieve high-speed operation by improving the

Furthermore, if the potential of impurity region 3 is applied by a substrate bias circuit, the load characteristics can be improved without using three power supplies.

Next, FIG. 1A shows a method for manufacturing a semiconductor device according to the present invention.
This will be explained with reference to FIG. As shown in FIG. 1A, boron B ions are implanted into the entire surface of the N-conductivity type semiconductor substrate 1 except for the region where the second impurity layer 5 constituting the junction transistor is to be formed. form. Next, a field oxide film 2 with a thickness of 1 μm is selectively formed in a predetermined region of the impurity region 3 by thermal oxidation.

Next, as shown in FIG.
An oxide film to be the gate oxide film 6 is formed to a thickness of approximately 800 Å on the active region and field oxide film 2 partitioned by
Forms 4000Å. Next, the polycrystalline silicon film is subjected to predetermined patterning by photolithography to form gate electrode 7. Using this gate electrode 7 as a mask, etching is performed so that the oxide film directly under it remains, thereby forming a gate oxide film 6. Next, using the field oxide film 2 and the gate electrode 7 as masks, phosphorus P impurity diffusion is performed to form a first impurity layer 4 of N conductivity type in the impurity region 3 of the active region.
A second impurity layer 5 of N conductivity type is formed in semiconductor substrate 1 surrounded by impurity region 3 .

Next, as shown in Figure C, CVD (Chemical
The field oxide film, the gate electrode 7 and the first and second impurity layers 4 and 5 are formed using the Vapor Deposition method.
A CVD-SiO ₂ film 8 with a thickness of 12000 Å is formed on the exposed surface of the substrate. Next, a predetermined region of this CVD-SiO ₂ film 8 is etched to form the first and second impurity layers 4,
Contact hole 9 leading to impurity region 5 and impurity region 3
A contact hole 9 is formed toward a predetermined region of the substrate. Furthermore, selective etching is separately performed to make the contact hole 9 facing the impurity region 3 reach the impurity region 3.

Thereafter, as shown in Figure D, an aluminum layer is coated within these contact holes 9 and the entire exposed surface of the CVD-SiO ₂ film 8, and this aluminum layer is patterned by photolithography to form impurity regions. 3, and extraction electrodes 10, 11, 12 which are connected to the first and second impurity layers 4, 5 are formed. Next, after baking is performed at about 450°C to form ohmic contact between the extraction electrodes 10, 11, 12 and the impurity region 3 and the first and second impurity layers 4, 5, the extraction electrodes 10, 11 , 12 and CVD-SiO ₂
A protective film 13 made of phosphorus silicate glass or the like is deposited on the exposed surface of the film 8, and pads (not shown) for taking out electrodes are formed on this protective film 13, thereby forming the semiconductor device 1.
Get 4.

As described above, according to this semiconductor device manufacturing method, it is possible to easily manufacture the semiconductor device 14 in which the drive MOS transistor and the junction field effect transistor serving as its load are provided in the active region to reduce the area required for the inverter configuration. be able to.

In the embodiment, P is applied to the N conductivity type semiconductor substrate 1.
Semiconductor device 14 in which conductive type impurity region 3 is formed
However, N is applied to a P conductivity type semiconductor substrate.
A conductive type impurity region may be formed.

As explained above, according to the semiconductor device according to the present invention, a drive MOS transistor and a junction field effect transistor serving as its load are formed in the active region, and a substrate bias circuit is formed in the impurity region constituting each transistor. Since a potential with a polarity different from that of the substrate is applied, it has remarkable effects such as improving the degree of integration and load characteristics and achieving high-speed operation.

[Brief explanation of the drawing]

1A to 1D are explanatory diagrams showing the manufacturing process of a semiconductor device according to the present invention in the order of steps, and FIG. 1A shows the formation of a buried layer in a semiconductor substrate provided with a field oxide film. Figure B is an explanatory diagram showing a gate electrode formed in the element region of the same semiconductor substrate, and Figure C is an explanatory diagram showing a gate _electrode formed on the exposed surface of the same semiconductor substrate. Figure D is a sectional view of an embodiment of the present invention. 1... Semiconductor substrate, 3... Impurity region, 4...
First impurity layer, 5... Second impurity layer, 7... Gate electrode, 14 ... Semiconductor device.

Claims (1)

[Claims] 1 A semiconductor substrate of one conductivity type, an impurity region of an opposite conductivity type extending from the surface of the substrate to a predetermined depth while selectively leaving a predetermined region of the substrate, and a semiconductor substrate formed within the impurity region. a first impurity layer having a conductivity type; and a second impurity layer having the same conductivity type as the first impurity layer and extending from a predetermined region of the substrate into the impurity region apart from the first impurity layer. , the first impurity layer, the second impurity layer, and a gate electrode provided on the substrate between these form a drive MOS transistor, and the substrate, the impurity region, and the second impurity layer form a load. 1. A semiconductor device comprising a junction field effect transistor, wherein a power supply potential applied to the substrate and a power supply potential applied to the impurity region are different.