JPS61294934A - 半導体装置およびデ−タ伝送路 - Google Patents
半導体装置およびデ−タ伝送路Info
- Publication number
- JPS61294934A JPS61294934A JP13660685A JP13660685A JPS61294934A JP S61294934 A JPS61294934 A JP S61294934A JP 13660685 A JP13660685 A JP 13660685A JP 13660685 A JP13660685 A JP 13660685A JP S61294934 A JPS61294934 A JP S61294934A
- Authority
- JP
- Japan
- Prior art keywords
- output
- cmos inverter
- inputs
- circuit
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000013500 data storage Methods 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 abstract description 9
- 238000013459 approach Methods 0.000 abstract 1
- 230000036039 immunity Effects 0.000 abstract 1
- 239000000872 buffer Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 5
- 230000000644 propagated effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Logic Circuits (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13660685A JPS61294934A (ja) | 1985-06-21 | 1985-06-21 | 半導体装置およびデ−タ伝送路 |
US06/875,551 US4785204A (en) | 1985-06-21 | 1986-06-18 | Coincidence element and a data transmission path |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13660685A JPS61294934A (ja) | 1985-06-21 | 1985-06-21 | 半導体装置およびデ−タ伝送路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61294934A true JPS61294934A (ja) | 1986-12-25 |
JPH0410251B2 JPH0410251B2 (enrdf_load_stackoverflow) | 1992-02-24 |
Family
ID=15179226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13660685A Granted JPS61294934A (ja) | 1985-06-21 | 1985-06-21 | 半導体装置およびデ−タ伝送路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61294934A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2768872A1 (fr) * | 1997-09-25 | 1999-03-26 | Sgs Thomson Microelectronics | Porte logique ou-exclusif a quatre entrees complementaires deux a deux et a deux sorties complementaires, et multiplieur de frequence l'incorporant |
-
1985
- 1985-06-21 JP JP13660685A patent/JPS61294934A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2768872A1 (fr) * | 1997-09-25 | 1999-03-26 | Sgs Thomson Microelectronics | Porte logique ou-exclusif a quatre entrees complementaires deux a deux et a deux sorties complementaires, et multiplieur de frequence l'incorporant |
EP0905907A1 (fr) * | 1997-09-25 | 1999-03-31 | STMicroelectronics SA | Porte logique OU-exclusif à quatre entrées complémentaires deux à deux et à deux sorties complémentaires, et multiplicateur de fréquence l'incorporant |
Also Published As
Publication number | Publication date |
---|---|
JPH0410251B2 (enrdf_load_stackoverflow) | 1992-02-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |