JPS61282939A - Online test system for distributed device - Google Patents

Online test system for distributed device

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Publication number
JPS61282939A
JPS61282939A JP60124159A JP12415985A JPS61282939A JP S61282939 A JPS61282939 A JP S61282939A JP 60124159 A JP60124159 A JP 60124159A JP 12415985 A JP12415985 A JP 12415985A JP S61282939 A JPS61282939 A JP S61282939A
Authority
JP
Japan
Prior art keywords
common bus
test
bidirectional common
data
bidirectional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60124159A
Other languages
Japanese (ja)
Other versions
JPH0719213B2 (en
Inventor
Masazumi Sawada
沢田 正純
Hideyuki Matsubara
秀幸 松原
Yoichi Kasai
笠井 洋一
Toshiharu Ueda
上田 敏晴
Tomiji Koike
小池 富司
Hiroshi Suzuki
弘 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK, Oki Electric Industry Co Ltd filed Critical Kokusai Denshin Denwa KK
Priority to JP60124159A priority Critical patent/JPH0719213B2/en
Publication of JPS61282939A publication Critical patent/JPS61282939A/en
Publication of JPH0719213B2 publication Critical patent/JPH0719213B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To test each controller in the online state by providing in addition a testing device on a bidirectional common bus and adding a test circuit part, which transmits and receives data to and from the bidirectional common bus synchronously with the testing device, to each of plural controllers. CONSTITUTION:A testing device 5 which tests the functions of controllers is connected to the bidirectional common bus 1, and each controller is provided with the test circuit part which transmits and receives data to and from the bidirectional common bus synchronously with the testing device, and specific time slots on the bidirectional common bus are used between the testing device and test circuit parts to test transmission and reception functions of controllers to the bidirectional bus. That is, the online test is performed without disconnecting controllers since transmission and reception functions of controllers are tested simultaneously with the operation of the other time slots.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は双方向共通バスに分散して接続される装置の
オンラインテスト方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an online test method for devices connected in a distributed manner to a bidirectional common bus.

(従来の技術) 従来、双方向共通バスに複数個の制御装置が接続され、
制御装置間でデータの送受信を行なうシステムにおいて
、複数個の制御装置の内の1つ以上の制御装置の双方向
共通バスへのデータの送受信機能を試験する場合、予め
制御装置に双方向共通バスの手前に折返し用の試験回路
を用意して、試験の時には制御装置をオンライン系から
切り離し、オフラインとして、折返し試験を行って双方
向共通バスへのデータの送受信機能を試験していた。
(Prior art) Conventionally, multiple control devices are connected to a bidirectional common bus.
In a system that transmits and receives data between control devices, when testing the data transmission and reception function to the bidirectional common bus of one or more of the plurality of control devices, the bidirectional common bus is connected to the control device in advance. A test circuit for loopback was prepared in front of the bus, and during testing, the control device was disconnected from the online system and the loopback test was performed offline to test the data transmission and reception function to the bidirectional common bus.

(発明が解決しようとする問題点) しかしながら、上記従来の技術では、試験対象の制御装
置をオンライン系から切り離さねばならない、かつ双方
向共通バスへ信号を乗り入れる事ができないという欠点
があった。
(Problems to be Solved by the Invention) However, the above-mentioned conventional technology has the disadvantage that the control device to be tested must be separated from the online system and that signals cannot be transferred to the bidirectional common bus.

また、双方向共通バスを2重化しである装置では、双方
向共通バスに接続される複数個の制御装置も2重化され
ているのが普通であり、この場合は双方向共通バスの片
系およびその片系のバスに接続される制御装置の幾つか
をオフラインにする事により、制御装置の双方向バスへ
のデータの送受信機能を試験していた。この場合も、試
験を行う制御装置および双方向共通バスの片系をオフラ
インにしなければならないという欠点があった。
Additionally, in devices with dual bidirectional common buses, the multiple control devices connected to the bidirectional common bus are also usually duplicated; in this case, one of the bidirectional common buses is By taking some of the control devices connected to the system and one side of the bus offline, we tested the control device's ability to send and receive data to the bidirectional bus. In this case as well, there is a drawback that the control device to be tested and one system of the bidirectional common bus must be taken off-line.

本発明は従来の技術の上記欠点を解決することを目的と
する。
The present invention aims to overcome the above-mentioned drawbacks of the prior art.

(問題点を解決するための手段) 上記目的を達成するための本発明の特徴は、双方向共通
バスに複数の制御装置が接続され、双方向共通バスを介
して制御装置の間でデータの送受信を行なう分散装置の
オンラインテスト方式において、前記双方向共通バスに
、制御装置の機能を試験する試験装置を接続し、各制御
装置の各々が前記試験装置と同期して双方向共通バスと
データの送受信を行なう試験回路部を有し、前記試験装
置と、前記試験回路部との間で、双方向共通バス上の特
定のタイムスロットを利用して、制御装置の双方向共通
バスとの送受信機能をテストする分散装置のオンライン
テスト方式にある。
(Means for Solving the Problems) A feature of the present invention for achieving the above object is that a plurality of control devices are connected to a bidirectional common bus, and data is exchanged between the control devices via the bidirectional common bus. In an online test method for a distributed device that performs transmission and reception, a test device for testing the functions of a control device is connected to the bidirectional common bus, and each control device synchronizes with the test device to connect data to the bidirectional common bus. The control device has a test circuit unit that performs transmission and reception between the test device and the test circuit unit, and uses a specific time slot on the bidirectional common bus to transmit and receive the control device to and from the bidirectional common bus. There is an online test method for the distributed device to test the functionality.

(作用) 試験装置と制御装置との間では特定のタイムスロットを
利用して、他のタイムスロットの動作と同時に制御装置
の送受信機能の試験が行われる。
(Function) Using a specific time slot between the test device and the control device, the transmission and reception functions of the control device are tested simultaneously with operations in other time slots.

従って制御装置を切り離さずにオンラインテストを行う
ことができる。
Therefore, online testing can be performed without disconnecting the control device.

(実施例) 第1図はこの発明の実施例を示す、1は双方向共通バス
であり、2,3.4は双方向共通バスに接続される制御
装置であり、最大N(Nは整数)個の制御装置が接続さ
れる。5は試験装置、6は該制御装置全体の監視、基本
クロックの分配を行う監視装置、7は監視装置から分配
される基本クロックのバスである。試験データは双方向
共通バス1を介して制御装置(2,3,4)と試験装置
5との間でデータの送受信を行う。
(Embodiment) FIG. 1 shows an embodiment of the present invention. 1 is a bidirectional common bus, 2, 3. 4 are control devices connected to the bidirectional common bus, and the maximum number is N (N is an integer. ) control devices are connected. 5 is a test device, 6 is a monitoring device that monitors the entire control device and distributes a basic clock, and 7 is a bus for basic clocks distributed from the monitoring device. Test data is transmitted and received between the control device (2, 3, 4) and the test device 5 via the bidirectional common bus 1.

第2図は制御装置の試験回路部分であり、10は制御装
置、11は基本クロックバス、12は1次カウンタ、1
3は2次カウンタ、14は双方向共通バス、15は装置
ナンバー、16は2次カウンタ出力、17は一致回路、
18は入力指示信号、19は一般データ入力指示信号、
20は入力ゲート、21は内部試験用ゲート、22は内
部試験用レジスタ、23は出力指示信号、24は出力デ
ータゲート、25は一般データ出力ゲート、26は出力
ゲート、27は一般データ出力指示信号、28は入力指
示信号18と出力指示信号23の論理和信号、29は一
般データである。
FIG. 2 shows the test circuit part of the control device, where 10 is the control device, 11 is the basic clock bus, 12 is the primary counter, and 1
3 is a secondary counter, 14 is a bidirectional common bus, 15 is a device number, 16 is a secondary counter output, 17 is a matching circuit,
18 is an input instruction signal, 19 is a general data input instruction signal,
20 is an input gate, 21 is an internal test gate, 22 is an internal test register, 23 is an output instruction signal, 24 is an output data gate, 25 is a general data output gate, 26 is an output gate, and 27 is a general data output instruction signal. , 28 is a logical sum signal of the input instruction signal 18 and the output instruction signal 23, and 29 is general data.

制御装置10は基本クロックバス11より基本クロック
受信し1次カウンタ12.2次カウンタ13を作成する
。1次カウンタ12はデータの第1次関門であり、2次
カウンタ13は双方向共通バス14に接続される最大の
制御装置数と同値の値をもつカウンタであり、かつ2次
カウンタ13の1タイムスロツトは、双方向共通バス1
4上でデータの送受信を1回行う基本タイムスロットと
なる。今、実施例では1次カウンタ12を480進に2
次カウンタ13を64進に設定する。1次カウンタ12
は2次カウンタ13が64をカウントする毎に1カウン
トアツプし・479の次はOに戻る様に作られている。
The control device 10 receives the basic clock from the basic clock bus 11 and creates a primary counter 12 and a secondary counter 13. The primary counter 12 is the first barrier to data, and the secondary counter 13 is a counter that has a value equal to the maximum number of control devices connected to the bidirectional common bus 14, and one of the secondary counters 13. The time slot is bidirectional common bus 1
This is a basic time slot in which data is sent and received once on 4. Now, in the embodiment, the primary counter 12 is converted into 480 base 2.
Next counter 13 is set to 64-decimal. Primary counter 12
is designed so that each time the secondary counter 13 counts 64, the count increases by 1 and returns to 0 after 479.

制御装置10は1次カウンタ12がカウント0から47
7までは一般のデータの送受信に使用され、カウント4
78.479を試験用として使用する。又、制御装置1
0は各々制御装置10同士で重複しない装置ナンバー1
5が与えられ、装置ナンバー15は2次カウンタ13の
計数の内の任意の1つの値が割り当てられる。
The control device 10 has the primary counter 12 count from 0 to 47.
Up to 7 are used for general data transmission and reception, and count 4
78.479 will be used for testing. Also, the control device 1
0 is the device number 1 that does not overlap between each control device 10
5 is given, and the device number 15 is assigned any one of the counts of the secondary counter 13.

制御装置10の2次カウンタ出力16は装置ナンバー1
5と一致回路17にて比較され同一値の時に一致回路1
7の出力が出される。この出力は1次カウンタ12のカ
ウンタ値478.479と論理積がとられ、カウントが
478の時との論理積がとられた時、双方向共通バス1
4からのデータを制御装置10に入力する入力指示信号
18を出す、入力指示信号18は一般時のデータ入力指
示信号19と論理和がとられ、双方向共通バス14の入
力ゲート20のゲートを開き、データを内部試験用ゲー
ト21を通して内部試験用レジスタ22のデータ入力端
子へ入力する。データは基本クロックにより内部試験用
レジスタ22ヘセソトされる。
The secondary counter output 16 of the control device 10 is device number 1.
5 and match circuit 17, and when the values are the same, match circuit 1
7 outputs are produced. This output is ANDed with the counter value 478.479 of the primary counter 12, and when the count is 478, the bidirectional common bus 1
The input instruction signal 18 is logically summed with the normal data input instruction signal 19 to output the input instruction signal 18 for inputting the data from 4 to the control device 10. data is input to the data input terminal of the internal test register 22 through the internal test gate 21. Data is transferred to the internal test register 22 by the basic clock.

一致回路17の出力と1次カウンタ12のカウント値4
79との論理積がとられた時、内部試験用レジスタ22
のデータを双方向共通バス14へ出力する出力指示信号
23を出す。出力指示信号23は内部試験用レジスタ2
2の出力データのゲート24を開き、出力データは一般
データ出力ゲート25のデータ出力と論理和がとられ双
方向共通バス14の出力ゲート26のデータ入力となる
。出力ゲート26のゲートは出力指示信号23と一般デ
ータ出力指示信号27との論理和でゲートが開かれ、双
方向共通バス14ヘデータが出力される。
Output of matching circuit 17 and count value 4 of primary counter 12
When the AND with 79 is taken, the internal test register 22
The output instruction signal 23 outputs the data to the bidirectional common bus 14. Output instruction signal 23 is internal test register 2
The output data gate 24 of No. 2 is opened, and the output data is ORed with the data output of the general data output gate 25 and becomes the data input of the output gate 26 of the bidirectional common bus 14. The gate of the output gate 26 is opened by the logical sum of the output instruction signal 23 and the general data output instruction signal 27, and data is output to the bidirectional common bus 14.

一般データの出力ゲート25は入力指示信号18と出力
指示信号23の論理和信号28がとられた時は、出力ゲ
ート25の出力は抑えられ、一般データ29は双方向デ
ータバス14へは出力されない。
When the general data output gate 25 receives the OR signal 28 of the input instruction signal 18 and the output instruction signal 23, the output of the output gate 25 is suppressed, and the general data 29 is not output to the bidirectional data bus 14. .

第3図は主に試験装置の内部回路であり、40は試験装
置、41は監視装置、42は基本クロック、43は1次
カウンタ、44は2次カウンタ、45は送信ゲート、4
6は双方向共通バス、47は試験データ、48は比較デ
ータ、49は受信ゲート、50は実装/未実装テーブル
、51は実装/未実装出力データ、52は試験ゲート、
53は一致回路、54はエラー情報である。ここで第2
図の双方向共通バス14は第3図の46と同一な双方向
共通バスを示す。試験装置40は監視装置41より基本
クロック42を受信し、1次カウンタ43.2次カウン
タ44を作成する。
FIG. 3 mainly shows the internal circuit of the test equipment, 40 is the test equipment, 41 is the monitoring device, 42 is the basic clock, 43 is the primary counter, 44 is the secondary counter, 45 is the transmission gate, 4
6 is a bidirectional common bus, 47 is test data, 48 is comparison data, 49 is a receiving gate, 50 is a mounted/unmounted table, 51 is mounted/unmounted output data, 52 is a test gate,
53 is a coincidence circuit, and 54 is error information. Here the second
Bidirectional common bus 14 in the figure represents a bidirectional common bus identical to 46 in FIG. The test device 40 receives the basic clock 42 from the monitoring device 41 and creates a primary counter 43 and a secondary counter 44.

基本クロック42.1次カウンタ43.2次カウンタ4
4は制御装置10の基本クロック、1次カウンタ12.
2次カウンタ13と各々同期して動作する。従って、制
御装置10の1次カウンタ12のカウンタ値0.2次カ
ウンタ13のカウンタ値が0の時、試験装置40の1次
カウンタ43のカウンタ値も012次カウンタ44のカ
ウンタ値も0である。試験装置40の1次カウンタ43
のカウンタ値478の時、送信ゲート45を有効にし、
双方向共通バス46へ試験データ47を出力する。試験
データ47は、2次カウンタ44の0〜63の2次カウ
ンタ出力(2”〜2!の6ビツト)とアース信号(2G
 、 2 ?の2ビツト)及びパリティピット(2”の
1ビツト)の9ビツトから成っている。又、試験データ
47からパリティピットを除いた8ビツトが比較データ
48として、別途受信用一致回路53へ入力される。
Basic clock 42. Primary counter 43. Secondary counter 4
4 is a basic clock of the control device 10, and a primary counter 12.4.
Each operates in synchronization with the secondary counter 13. Therefore, when the counter value of the primary counter 12 of the control device 10 is 0, and the counter value of the secondary counter 13 is 0, the counter value of the primary counter 43 and the counter value of the 2nd counter 44 of the test device 40 are also 0. . Primary counter 43 of test device 40
When the counter value is 478, the transmission gate 45 is enabled,
Test data 47 is output to the bidirectional common bus 46. The test data 47 includes the secondary counter outputs 0 to 63 of the secondary counter 44 (6 bits from 2" to 2!) and the ground signal (2G
, 2? It consists of 9 bits: 2 bits of 2") and a parity pit (1 bit of 2"). Also, the 8 bits from the test data 47 excluding the parity pit are separately input to the reception matching circuit 53 as comparison data 48. Ru.

1次カウンタ43のカウンタ値が479の時、双方向共
通バス46の受信ゲート49を開き、双方向共通バス4
6からデータを入力すると共に2次カウンタ44のカウ
ンタ出力値を順次、監視装置41へ送る。
When the counter value of the primary counter 43 is 479, the reception gate 49 of the bidirectional common bus 46 is opened, and the bidirectional common bus 4
6, and the counter output value of the secondary counter 44 is sequentially sent to the monitoring device 41.

監視装置41は、制御装[10の実装/未実装テーブル
50を有しており、実装時は実装/未実装テーブルの出
力データ51を有効にし、受信ゲート49を通して入力
した受信データを試験ゲート52を通して一致回路53
へ入力する。一致回路53は試験ゲート52を通して入
力したデータと比較データ48を比較し合致しない場合
は、エラー情報54を監視装置41へ送信する。監視装
置41は、エラー情報54と2次カウンタ44の値で、
どの制御装置10からのデータが不良であったかを知る
事が出来る。
The monitoring device 41 has a mounted/unmounted table 50 for the control device [10]. During mounting, the output data 51 of the mounted/unmounted table is enabled, and the received data input through the receiving gate 49 is sent to the test gate 52. Through the matching circuit 53
Enter. The matching circuit 53 compares the data input through the test gate 52 with the comparison data 48, and if they do not match, sends error information 54 to the monitoring device 41. The monitoring device 41 uses the error information 54 and the value of the secondary counter 44,
It is possible to know from which control device 10 the data was defective.

(発明の効果) この発明は以上説明したように、双方向共通バスに試験
専用の試験装置を設け、また、双方向共通バスに接続さ
れる複数の制御装置の各々に試験装置と同期して双方向
共通バスとデータの送受信を行う試験回路部を追加した
ことにより、オンライン状態で各制御装置の試験が可能
であるという利点がある。従って、双方向共通バスとデ
ータの送受信が間欠的な制御装置や時期予備でデータの
送受信の正常性が確認できない制御装置、2重化された
双方向共通バスの時期予備側の双方向共通バスとインタ
フェースを有した部分の制御装置のデータ送受信部分の
異常検出をオンラインで速やかに行う事ができる。
(Effects of the Invention) As explained above, the present invention provides a test device exclusively for testing on a bidirectional common bus, and also provides a test device for each of a plurality of control devices connected to the bidirectional common bus in synchronization with the test device. By adding a test circuit section that transmits and receives data to and from a bidirectional common bus, there is an advantage that each control device can be tested in an online state. Therefore, a control device that transmits and receives data to and from the bidirectional common bus intermittently, a control device that cannot confirm the normality of data transmission and reception due to a temporary backup, and a bidirectional common bus on the temporary backup side of a duplicated bidirectional common bus. Detection of abnormalities in the data transmission/reception part of the control device that has an interface can be quickly performed online.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例の概略ブロック図。 第2図は双方′向共通バスに接続される制御装置の試験
回路部分を示す図、第3図は試験装置の内部概略図であ
る。 1;双方向共通バス、 2,3,4 ;制御装置、5;
試験装置、    6;監視装置。 7;基本クロックバス。 第1図 第2図 第3図
FIG. 1 is a schematic block diagram of an embodiment of the invention. FIG. 2 is a diagram showing the test circuit portion of the control device connected to the bidirectional common bus, and FIG. 3 is an internal schematic diagram of the test device. 1; Bidirectional common bus, 2, 3, 4; Control device, 5;
Test equipment, 6; Monitoring equipment. 7; Basic clock bus. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 双方向共通バスに複数の制御装置が接続され、双方向共
通バスを介して制御装置の間でデータの送受信を行なう
分散装置のオンラインテスト方式において、前記双方向
共通バスに、制御装置の機能を試験する試験装置を接続
し、各制御装置の各々が前記試験装置と同期して双方向
共通バスとデータの送受信を行なう試験回路部を有し、
前記試験装置と、前記試験回路部との間で、双方向共通
バス上の特定のタイムスロットを利用して、制御装置の
双方向共通バスとの送受信機能をテストすることを特徴
とする分散装置のオンラインテスト方式。
In an online test method for a distributed device in which a plurality of control devices are connected to a bidirectional common bus and data is sent and received between the control devices via the bidirectional common bus, the functions of the control devices are connected to the bidirectional common bus. A test device to be tested is connected to the control device, and each control device has a test circuit unit that transmits and receives data to and from a bidirectional common bus in synchronization with the test device;
A distributed device that tests the transmitting/receiving function of a control device to and from a bidirectional common bus by using a specific time slot on the bidirectional common bus between the test device and the test circuit section. online test method.
JP60124159A 1985-06-10 1985-06-10 Online test method for disperser Expired - Lifetime JPH0719213B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60124159A JPH0719213B2 (en) 1985-06-10 1985-06-10 Online test method for disperser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60124159A JPH0719213B2 (en) 1985-06-10 1985-06-10 Online test method for disperser

Publications (2)

Publication Number Publication Date
JPS61282939A true JPS61282939A (en) 1986-12-13
JPH0719213B2 JPH0719213B2 (en) 1995-03-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP60124159A Expired - Lifetime JPH0719213B2 (en) 1985-06-10 1985-06-10 Online test method for disperser

Country Status (1)

Country Link
JP (1) JPH0719213B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02165356A (en) * 1988-12-20 1990-06-26 Fujitsu Ltd System for preventing typeface information from being copied

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619248A (en) * 1979-07-24 1981-02-23 Fujitsu Ltd Loop circuit diagnosing system for communication control device
JPS58154950A (en) * 1982-03-10 1983-09-14 Fujitsu Ltd Bus monitoring system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619248A (en) * 1979-07-24 1981-02-23 Fujitsu Ltd Loop circuit diagnosing system for communication control device
JPS58154950A (en) * 1982-03-10 1983-09-14 Fujitsu Ltd Bus monitoring system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02165356A (en) * 1988-12-20 1990-06-26 Fujitsu Ltd System for preventing typeface information from being copied

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