JPH04321140A - Method and device for pointing error occurring part - Google Patents

Abstract

PURPOSE:To recognize an exchange unit having the largest count value of a counter as a part where an error occurred by detecting the error at the earliest stage. CONSTITUTION:The component parts of a computer system consist of the exchange units 1 that can be replaced with others. An error detecting means 2 detects the errors of the component elements for each unit 1. An error signal holding means 5 holds an error detecting signal. Then a counter 4 starts its counting operation with the error signal outputted from the means 3. An error control means 5 transmits simultaneously the count stop signals to the counters 4 based on the first transmitted error signal. A deciding means 6 checks the count value of each counter 4 and decides that the unit 1 showing the counter 4 having the largest count value has an error.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a method for pointing out parts to be replaced when an error occurs in a device composed of multiple LSIs (Large Scale Integrated Circuits), printed circuit boards, etc. and regarding equipment.

0002

2. Description of the Related Art When an error occurs in a computer system, there is a need to shorten the time required to repair the error. To do this, it is first necessary to identify the error occurrence part, and there are several methods, one of which is a program that locates the error occurrence part. This includes a checker that detects the occurrence of an error in the replacement part, and a region code (Region Code) that is a latch that self-holds the error detection signal of this checker.
System Console Interface
M Console Interface),
It is located between the VP (Service Processor) and the devices that make up the system, and controls the interface between the SVP and each device. Check whether error information is latched in the region code from the region code collected by SVP (SVP reads and sets the status of each device via SCI), and if latched, the first latched region code This is a program that identifies replacement parts with that region code as having an error.

[0003] Link information is used for this identification, and this indicates the spread of the error to related parts.
It correlates the cause and effect of each RC (region code). FIG. 8 shows an example of link information, and (a) shows the link node of the RC provided for each replacement part. RCA is the RC installed in replacement part A
This shows that replacement part A is connected to replacement parts B and G, and replacement part B is connected to replacement parts C and D.

[0004] If an error occurs in replacement part A,
Naturally, the error detection signal is latched in the RCA, but since the error spreads to the connected RCB and RCG, the error signal is also latched in the RCB and RCG. Since the error spreads in this way, by checking the RC in which the error signal is latched and using the link information shown in Figure (b), it is possible to trace back to the replacement part where the error occurred.

[0005]

[Problems to be Solved by the Invention] This link information is created manually, and must be created with all kinds of error patterns in mind, but it is not necessarily perfect. In other words, because they are created manually, human errors often result in omissions or errors in link information, which can lead to incorrect identification of error locations, prolonging the time it takes to repair the problem.

Furthermore, in order to check whether there are any errors or omissions in the created link information, it is necessary to generate a pseudo failure and verify whether the error occurrence part is correctly pointed out. The time required for the work was also enormous. Furthermore, as the system becomes larger, the amount of link information to be created increases, and with this increase, the number of omissions and errors in link information increases, creating a vicious cycle in which verification time further increases.

The present invention has been made in view of the above-mentioned problems, and detects an error as soon as possible, and thereby detects an error by incrementing a counter and pointing out the exchange unit with the largest count value as the error occurrence part. The purpose of the present invention is to provide a method and device for pointing out the occurrence area.

[0008]

[Means for Solving the Problems] FIG. 1 shows a principle diagram of an error occurrence point indicating device according to the present invention. In the figure, 1 is a replaceable unit of parts constituting a computer system, 2 is an error detection means for detecting errors in the components provided for each replacement unit 1 and outputting an error detection signal, and 3 is an Error signal holding means 4 for holding this error detection signal is a counter that starts counting with a common clock in response to the error signal output from error signal holding means 3. 5 is an error control means for simultaneously transmitting a count stop signal to each of the counters 4 based on the error signal transmitted first; 6 is an error control means for transmitting an error to the exchange unit 1 having the maximum count value among the count values of the counters 4; This is the determining means 6 that determines that the event has occurred.

Furthermore, a plurality of the replacement units 1 are mounted on the same panel board, and the error control means 5 is provided for each panel board.

0010

[Operation] When the error detection means 2 detects an error in a component, it outputs an error detection signal. Error signal holding means 3
outputs an error signal after holding this error detection signal. In response to this error signal, the counter 4 starts counting using a clock common to this error occurrence point pointing device. Further, this error signal passes through a predetermined communication path and arrives at the error control means 5 with a delay. A communication channel is provided with a delay time set so that the counter stop signals arrive from the error control means 5 to each counter 4 at the same time, so when the counter stop signal is transmitted from the error control means 5, each counter 4 simultaneously receives the counter stop signals. Stop counting. As a result, each counter 4 is assigned to the exchange unit 1 to which it belongs.
The counter counts and stops during the time during which the error signal is sent from the error signal holding means 3 to the error control means 5 and the time during which the counter stop signal is sent from the error control means 5 to the counter 4. Therefore, the count value at which the error signal is first transmitted and counting is started becomes the largest value. The determining means 6 checks the count value of each counter 4 and identifies the exchange unit 1 to which the counter 4 having the largest count value belongs as the error occurrence part.

By mounting a plurality of replacement units 1 on the same panel board and providing the error control means 5 for each panel board, it becomes easy to detect the replacement unit 1 in which an error has occurred.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows an example of a block diagram representing the configuration of a computer that implements an embodiment of the present invention. This device consists of a main unit and an input/output device, and the main unit includes a main memory MSU,
Extended storage SSU, memory control unit MCU that controls these, vector unit VU that performs vector operations
, a scalar unit SU that performs scalar operations, an input/output processor IOP, and a channel CH. The service processor SVP is a computer subsystem independent of the main unit, and has an operator console function, a system control function, and the like. In addition, the interface control SCI is located between the SVP and the devices that make up the computer system.
and the interface between each component device. SVP
reads and sets the status of each component device via the SCI. The input/output device is the input/output controller IOC
It consists of an input/output section IO.

FIG. 3 is a diagram showing an example in which component devices are mounted on each panel board. A CPU is installed on board A,
Board B is equipped with a memory control unit MCU, board C is equipped with an input/output processor IOP, and board D is equipped with a main memory MSU. Each board is provided with a plurality of LSIs and one error control unit EC, which serve as replacement units when an error is discovered. Some LSIs on each board are connected to LSIs on other boards, and when an error occurs, the error spreads to the connected LSIs. The "US" mark in the diagram indicates a situation in which an error occurs and spreads. The LSI to which these errors have spread is
An error signal is output to the error control unit EC of the board to which I belongs, indicating that the error control unit EC will start counting. In addition, the line connecting the ECs of each board is such that the EC that received the error signal from the LSI of its own board connects to the LSI of its own board.
This indicates that a counter stop signal is output to stop the counter of the other board, and the EC of the other board is caused to output a counter stop signal.

FIG. 4 is a diagram showing an error detection mechanism of an LSI mounted on each board and serving as a replacement unit. LSI
The components that make up can be broadly divided into gates, latches, and RAM. A register is a collection of latches, and in addition to registers, there are various things that can be constructed from latches, such as counters and shifters. When checking for normal errors,
Check timing is required and the gate cannot be checked directly. Also, RAM is R for its purpose.
AM You can't check it yourself. Therefore, such gates, RAM, etc. should be checked once they are latched and synchronized. Therefore, LSI
Error checking components include registers and latches, which are indicated by R in FIG.

A checker CHK for checking the error detection signal of the register R is provided for every one or several registers R, and is a latch that self-holds the error detection signal detected by the checker CHK by ORing the checkers CHK. A certain region code RC is provided. This region code RC holds the error detection signal until a reset signal is received. LSI-
Region code RC-B, which is the logical sum of the individual region codes RC provided in LSI-B, starts counting on counter B provided in LSI-B, and
An error signal is output to the error control unit EC within the own board on which LSI-B is implemented. Furthermore, the register R spreads the error to the connected LSI-C.

Normally, in the case of register R, one checker CHK is provided for each byte of signal data. In some cases, the region code RC is provided in a ratio of 1:1 to checker CHK, and in other cases, the region code RC is provided in a ratio of CHK n to 1 region code. The value of n is determined based on physical limitations depending on the number of gates used in the logic of each LSI, or depending on the importance of the circuit. However, since the checker CHK and region code RC do not directly assist the logic, it is desirable to minimize them.

FIG. 5 shows details of the error control section EC5 of board B. The error reception circuit 51 is an LSI in board B.
-B, LSI -C, LSI -X error signals, error B, error C, error
Output to C and D as a counter stop signal. LSI
The receiving section 52 outputs a count stop signal using OR logic of error signals received from each LSI on its own board.

The counter stop circuit 53 receives a counter stop request from its own board B or from other boards A, C, and D, and operates LSI-B, LSI-C, and LSI-X.
instructs the counter to stop counting. The board reception delay unit 54 compensates for the difference in delay values between the counter stop signal from the error reception circuit 51 of its own board and the counter stop signals from boards A, C, and D, and
A counter stop signal is generated to be output to the transmission delay unit 55. The LSI transmission delay section 55 is LSI −
B, LSI-C, and LSI-X are compensated with different delay values for each LSI, and a counter stop signal is output to synchronize and stop the counting operation of the counter of each LSI.

The counter stop signal to each LSI is
Each transmission path has a different delay value. Therefore, the difference is added to the counter stop signal having a delay value smaller than the counter stop signal having the maximum delay value. In the example of FIG. 5, if LSI-B has a delay value smaller than LSI-X by β, and LSI-C has a smaller delay value by α, then LSI-B has a delay value of β, LSI-C
shows that each counter stop signal is synchronized by adding an α delay value.

FIG. 6 shows an LSI that is a replacement unit within the board.
3 is a diagram showing the connection relationship between LSI -B, LSI -C, and error control unit EC5. Here, the counter stop request between boards is omitted. An error signal is sent from the region code RC of each LSI to the error reception circuit 51, and based on this error signal, the counter stop circuit 53
outputs a counter stop signal to LSI-B and LSI-C. This causes each counter to stop counting. Further, the counter reset circuit 56 is connected to the S
After the CI completes a scanout in which the internal states of the main unit and input/output devices are collected as a series of data, the region code RC and counter are reset by an error reset request sent to those devices.

FIG. 7 is a timing chart showing the operation of this embodiment. This timing chart shows a timing chart when an error occurs in LSI-A of board A shown in FIG. 3 and this spreads to LSI-B of board B. An error occurs in register R of LSI-A, an error detection signal is output from the corresponding checker CHK, and this error detection signal is latched in region code RC-A. This is shown in region code A. At the next clock, a count start signal is issued to counter A from region code RC-A. This is indicated by counter-A start. Simultaneously with this count start signal, the board A outputs an error signal A requesting another error control section EC5 to stop the counter. This is shown in error A.

[0022] The region code RC-B of LSI-B on board B detects errors that spread from LSI-A.
The error detection signal detected and transmitted by CHK of I-B is received one clock later than region code A, and counter B is started. This is shown in Region Code B and Counter-B Start. Also, region code RC-B outputs error signal B one clock later than error signal A, similar to RC-A. This is shown in error B. The delay time is the delay time required for the error control section 5 to synchronize and stop all counters after recognizing the first error signal, and is the delay time required for the error control section 5 to synchronize and stop all counters, and is the delay time required for the error control section 5 to synchronize and stop all counters.
This is the total value of the delay values compensated for by each of the board reception delay section 54 and the board reception delay section 54. Counter reset is shown in Figure 6.
Indicates that it is reset by the error reset request explained in .

As described above, when an error occurs in LSI-A, region code RC-A is set and counter A starts counting up. Also LS
The error that occurred in I-A spreads to LSI-B,
If the region code RC-B is also set, the LSI
The counter of LSI-B starts counting up later than that of -A. Then region code RC-A
The error acceptance circuit 51 of the error control circuit 5 sends a counter stop signal to the counter stop circuit 53 in response to the error signal reported from the error control circuit 5, which simultaneously stops counter A of LSI-A and counter B of LSI-B to fix the count value ( To freeze. Note that, if there is an error signal that arrives earlier than the error signal reported from the region code RC-A, the error control circuit 5 operates based on the error signal that arrived earlier.

[0024] Next, in a machine check process, a scanout is taken, and each frozen counter value is compared by the SVP. Since the count values of counter A and counter B are "n" and "m=n-1", respectively, the SVP points out that LSI-A is the error generating part. Furthermore, all counters are reset by an error reset signal issued during machine check processing.

Although the above-mentioned machine check processing has a large number of functions, the functions related to this embodiment are limited to the following. Scalar unit SU or extended storage SS
When the U recognizes the occurrence of a machine check, it issues an ERROR RECORD REQUEST to the SCI,
This causes the SCI to store the latch states of all devices in the scan memory within the SCI. And scalar unit S
Responds ERROR RECORDEND to U and sends SCI
ERROR LOGOUT REQ to SVP via
Issue UEST. Taking this as an opportunity, the machine check process starts the program that implements this embodiment, uses the counter value held in each LSI in the scanout information collected to proceed with the analysis, and finally determines the cause of the error. Create a flag code that encodes the LSI that has become .

[0026]

As is clear from the above explanation, the present invention provides a counter that starts when an error occurs for each replacement unit, instructs each counter to stop counting by the first error signal that arrives, and then changes the count value. Since the maximum exchange unit is set as the error occurrence part, the link information used in the prior art is unnecessary, and the accompanying link information creation and verification work is also unnecessary, eliminating mistakes.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing an example of the configuration of a computer that implements an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of component devices arranged on a board.

FIG. 4 is a diagram showing an error detection function of LSI-B, which is a replacement unit.

FIG. 5 is a diagram illustrating the configuration of an error control section.

FIG. 6 is a diagram showing a connection between an LSI, which is a replacement unit, and an error control section.

FIG. 7 is a timing chart of this embodiment.

FIG. 8 is an explanatory diagram of link information.

[Explanation of symbols]

5 Error control section 51 Error reception circuit 52 LSI receiving section 53 Counter stop circuit 54 Board reception delay section 55 LSI transmission delay section 56 Counter reset circuit

Claims (2)

[Claims] Claim 1: The parts constituting a computer system are composed of an exchangeable exchange unit (1), and the exchange unit (1) is
1), an error detecting means (2) for discovering errors in components and outputting an error finding signal, an error signal holding means (3) for holding this error finding signal, and an error signal holding means (3) for holding this error finding signal. 3) a counter (4) that starts counting with a common clock based on the error signal output from the above, and an error control means that simultaneously transmits a count stop signal to each of the counters (4) based on the error signal transmitted first. (5) and the exchange unit (1) having the maximum count value among the count values of the counter (4).
An error occurrence part pointing device characterized by comprising a determining means (6) for determining that an error has occurred. 2. The error control device according to claim 1, wherein a plurality of the replacement units (1) are mounted on the same panel board, and the error control means (5) is provided for each panel board. Occurrence point pointing device.