JPS61280608A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61280608A
JPS61280608A JP11574285A JP11574285A JPS61280608A JP S61280608 A JPS61280608 A JP S61280608A JP 11574285 A JP11574285 A JP 11574285A JP 11574285 A JP11574285 A JP 11574285A JP S61280608 A JPS61280608 A JP S61280608A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
single crystal
substrate
structural layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11574285A
Other languages
Japanese (ja)
Other versions
JPH0834170B2 (en
Inventor
Tadao Toda
忠夫 戸田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP60115742A priority Critical patent/JPH0834170B2/en
Publication of JPS61280608A publication Critical patent/JPS61280608A/en
Publication of JPH0834170B2 publication Critical patent/JPH0834170B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To generate tunnel current in a super grid structural layer by providing specific super grid structural layer between a substrate and a ZnSe layer. CONSTITUTION:A semiconductor device is composed of the first layer 1 comprising the first semiconductor, a super grid structural layer 2 composed of multiple layers alternately laminating the first thin layers 3 comprising the first semiconductor laminated on the first layer 1 and the second thin layers 4 comprising the second semiconductor with different composition from that of the first semiconductor, and the second layer 5 comprising the second semiconductor laminated on the super grip structural layer 2. The super grid structural layer 2 containing the second thin layers 4 can generate tunnel current therein, making current voltage characteristics ohmic.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は半導体装置に関する。[Detailed description of the invention] (b) Industrial application fields The present invention relates to a semiconductor device.

(ロ)従来の技術 現在、G aA uA s(ガリウムアルミ砒素)、Z
n5(硫化亜鉛)、Z n S e(ジンクセレン)の
ように単結晶基板が得難い半導体単結晶は格子定数が近
似する単結晶基板上に形成している。
(b) Conventional technology Currently, GaA uAs (gallium aluminum arsenide), Z
Semiconductor single crystals, such as n5 (zinc sulfide) and ZnSe (zinc selenium), for which it is difficult to obtain a single crystal substrate, are formed on a single crystal substrate with similar lattice constants.

ところが第4図に示す如く、Zn5e単結晶(6)を斯
る単結晶(6)と格子定数が近似するGaAs5結晶(
7)上に形成したとしても上記両車結晶のエネルギーギ
ャップが異なるため形成されたベテロ接合(8)は整流
障壁となりその電流電圧特性は第5図に示す如く非オー
ミツクとなるという問題があった。
However, as shown in FIG.
7) Even if it were formed above, the difference in the energy gap between the two vehicle crystals caused the problem that the formed betarojunction (8) would act as a rectification barrier and its current-voltage characteristics would become non-ohmic as shown in Figure 5. .

そこで、ジャーナル オブ バキューム サイエンス 
アンド チク・′ロジ(Journal of Vac
uumScience and Technology
) 、 19(3) r 5ept、10ct。
Therefore, the Journal of Vacuum Science
Journal of Vac
uumScience and Technology
), 19(3) r 5ept, 10ct.

1981 、 P626−627に開示されている如き
技術を応用して上記単結晶基板と上記半導体単結晶との
間にバンドギャップが連続的に変化し、かつ上記単結晶
基板及び半導体単結晶と格子定数が近似するグレード層
を配する構成とし、オーミックを取る方法が一般的に採
用されている。
1981, P626-627, the band gap between the single crystal substrate and the semiconductor single crystal changes continuously, and the lattice constant of the single crystal substrate and the semiconductor single crystal changes. Generally, a method is adopted in which a grade layer having a similar value is arranged to obtain ohmic properties.

(ハ〉 発明が解決しようとする問題点熱るに例えばG
aAs(ガリウム砒素)単結晶基板上に断る基板と格子
定数が略等しいZn5e単結晶を形成する際には上述の
ようなグレード層に最適な単結晶が未だ発見されていな
いため上記従来方法を用いることは不可能である。
(C) The problem that the invention aims to solve is, for example, G.
When forming a Zn5e single crystal having approximately the same lattice constant as the substrate on an aAs (gallium arsenide) single crystal substrate, the above conventional method is used because the optimal single crystal for the above-mentioned grade layer has not yet been discovered. That is impossible.

(ニ)問題点を解決するための手段 本発明は斯る点に鑑みてなされたものでその構成的特徴
は第1半導体からなる第1Ji、該第1層上に積層され
上記第1半導体からなる第1薄層と上記第・1半導体と
は組成の異なる第2半導体からなる第2薄層とを交互に
複数着積層してなる超格子構造層、該超格子構造肩上に
積層され上記第2半導体からなる第2層を備えたことに
ある。
(d) Means for Solving the Problems The present invention has been made in view of the above points, and its structural features include a first layer made of a first semiconductor, a layer laminated on the first layer and made of the first semiconductor. A superlattice structure layer formed by alternately stacking a plurality of first thin layers consisting of a first thin layer consisting of a second semiconductor having a composition different from the first semiconductor; The present invention includes a second layer made of a second semiconductor.

(ホ)作用 このような構成では、超格子構造層においてトンネル電
流が流れる。
(E) Effect In such a configuration, a tunnel current flows in the superlattice structure layer.

くべ)実施例 第1図は本発明の実施例を示し、(1)は−主面が(1
00)面のD型GaAs単結晶基板であり、該基板は1
018/aT+3のキャリア濃度を有する。
Example) Figure 1 shows an example of the present invention.
00) plane, the substrate is a D-type GaAs single crystal substrate with 1
It has a carrier concentration of 018/aT+3.

(2)は上記基板(1)の−主面上に形成された超格子
構造層であり、該構造層はノンドープもしくはキャリア
濃度I Q 14〜l Q I S / c1113の
n型GaAs単結晶からなる層厚10〜20人の第1薄
層(3)とキャリア濃度10”−1017/am’のn
型Zn5e単結晶からなる層厚10〜20人の第2薄層
(4)とを交互に例えば5層ずつ積層してなる。
(2) is a superlattice structure layer formed on the -main surface of the substrate (1), and the structure layer is made of non-doped or n-type GaAs single crystal with carrier concentration IQ 14~lQIS/c1113. The first thin layer (3) has a layer thickness of 10 to 20 people and a carrier concentration of 10"-1017/am'n
A second thin layer (4) of 10 to 20 layers made of type Zn5e single crystal is alternately laminated, for example, five layers at a time.

また、斯る両薄層(3)(4)は例えばMBE(分子線
エピタキシャル)成長法を用いて形成できる。
Furthermore, these thin layers (3) and (4) can be formed using, for example, MBE (molecular beam epitaxial) growth.

具体的には上記基板(1)を超高真空中(10−”T。Specifically, the substrate (1) was placed in an ultra-high vacuum (10-''T).

rr以下)で630℃10分間熱エツチングする。その
後上記基板く1)を400〜450℃の一定温度に保持
し、(i)Znセル温度300℃、Seセル温度220
℃として第2薄層(4)を形成する第1工程、(i )
Gaセル温度1020℃、Asセル温度220℃として
第1薄層(3)を形成する第2工程を交互に繰返すこと
により形成できる。
Heat etching is performed at 630°C for 10 minutes. Thereafter, the above substrate 1) was maintained at a constant temperature of 400 to 450°C, and (i) Zn cell temperature was 300°C, Se cell temperature was 220°C.
A first step of forming a second thin layer (4) as (i)
It can be formed by alternately repeating the second step of forming the first thin layer (3) at a Ga cell temperature of 1020° C. and an As cell temperature of 220° C.

(5)は上記超格子構造層(2)上に積層きれたn型Z
n5e層であり、該Zn5e層は1g16〜1017 
/cIT13のキャリア濃度を有する。
(5) is an n-type Z layer laminated on the superlattice structure layer (2).
n5e layer, the Zn5e layer is 1g16~1017
/cIT13.

第2図は本実施例半導体装置のバンド構造を示し、第2
図(a)は電圧非印加時の状態を、同図(b)は基板(
1)を負極、21136層(5)を正極として電圧を印
加した際の状態を示す、尚第2図中Ec、 Evは夫々
伝導バンド及び価電子バンドである。
FIG. 2 shows the band structure of the semiconductor device of this example.
Figure (a) shows the state when no voltage is applied, and Figure (b) shows the state when no voltage is applied.
The state is shown when a voltage is applied using 1) as the negative electrode and the 21136 layer (5) as the positive electrode. In FIG. 2, Ec and Ev are the conduction band and the valence band, respectively.

また、第3図は未実施例装置のtfIc電圧特性を示す
Moreover, FIG. 3 shows the tfIc voltage characteristics of an unexampled device.

第3図からも明らかな如く、本実施例装置ではオーミン
クとなる。これは超格子構造層(2)における第2薄層
(4)が10人〜20人と薄いために斯る構造層(2)
中でトンネル電流が生じるためである。
As is clear from FIG. 3, the device of this embodiment exhibits ohmink. This is because the second thin layer (4) in the superlattice structure layer (2) is as thin as 10 to 20 people.
This is because a tunnel current is generated inside.

本実施例では超格子構造層(2)の第1、第2薄層(3
)(4)をMBE成長法を用いて形成したが、MOCV
D(有機金属気相成長)法、低温気相成長法等の他の薄
膜成長法を用いて形成することも可能である。また、超
格子構造層(2)を第1、第2薄層(3)(4)を夫々
sm交互に積層した構成としたが、基板(1)を負極と
しZn5e層(5)を正極として数ボルト以下の電圧を
印加した際にZn5e層(5)の伝導バンドが基板(1
)のそれより下がるものであれば上記積層数は何層であ
っても良い。
In this example, the first and second thin layers (3) of the superlattice structure layer (2)
)(4) was formed using the MBE growth method, but MOCV
It is also possible to form using other thin film growth methods such as D (organometallic vapor phase epitaxy) method and low temperature vapor phase epitaxy method. In addition, the superlattice structure layer (2) has a structure in which the first and second thin layers (3) and (4) are laminated alternately in sm, respectively, with the substrate (1) as the negative electrode and the Zn5e layer (5) as the positive electrode. When a voltage of several volts or less is applied, the conduction band of the Zn5e layer (5) changes to the substrate (1).
) The number of laminated layers may be any number as long as it is lower than that of ).

(ト)発明の効果 本発明を用いれば、単結晶基板が得難い半導体単結晶を
斯る半導体単結晶と格子定数が近似し、バンドギヤ・/
ブエネルギが異なる半導体単結晶上に形成しても電流電
圧特性をオーミックとすることで可能である。
(G) Effects of the Invention By using the present invention, the lattice constant of a semiconductor single crystal for which a single crystal substrate is difficult to obtain is similar to that of such a semiconductor single crystal, and a band gear//
Even if it is formed on a semiconductor single crystal having a different energy, it is possible to make the current-voltage characteristics ohmic.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す断面図、第2図(a)(
b)は本実施例装置のバンド構造を示す模式図、第3図
は本実施例装置の電流電圧特性を示す特性図、第4I3
0は従来例を示す断面図、第5図は従来例の電流電圧特
性を示す特性図である。 (1)・・・基板(第口1、(2)・−・超格子構造層
、(3)・・−第1薄届、<4)・−第2薄層、(5)
・=ZnSe層(第2層)。
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2(a) (
b) is a schematic diagram showing the band structure of the device of this embodiment, FIG. 3 is a characteristic diagram showing the current-voltage characteristics of the device of this embodiment, and 4I3
0 is a sectional view showing a conventional example, and FIG. 5 is a characteristic diagram showing current-voltage characteristics of the conventional example. (1)...Substrate (first opening, (2)...superlattice structure layer, (3)...-first thin layer, <4)...-second thin layer, (5)
・=ZnSe layer (second layer).

Claims (1)

【特許請求の範囲】[Claims] (1)第1半導体からなる第1層、該第1層上に積層さ
れ上記第1半導体からなる第1薄層と上記第1半導体と
は組成の異なる第2半導体からなる第2薄層とを交互に
複数層積層してなる超格子構造層、該超格子構造層上に
積層され上記第2半導体からなる第2層を備えたことを
特徴とする半導体装置。
(1) A first layer made of a first semiconductor, a first thin layer laminated on the first layer and made of the first semiconductor, and a second thin layer made of a second semiconductor having a different composition from the first semiconductor. 1. A semiconductor device comprising: a superlattice structure layer formed by alternately laminating a plurality of layers; and a second layer laminated on the superlattice structure layer and made of the second semiconductor.
JP60115742A 1985-05-29 1985-05-29 Semiconductor device Expired - Fee Related JPH0834170B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60115742A JPH0834170B2 (en) 1985-05-29 1985-05-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60115742A JPH0834170B2 (en) 1985-05-29 1985-05-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61280608A true JPS61280608A (en) 1986-12-11
JPH0834170B2 JPH0834170B2 (en) 1996-03-29

Family

ID=14669938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60115742A Expired - Fee Related JPH0834170B2 (en) 1985-05-29 1985-05-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0834170B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028268A (en) * 1983-07-26 1985-02-13 Agency Of Ind Science & Technol Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028268A (en) * 1983-07-26 1985-02-13 Agency Of Ind Science & Technol Semiconductor device

Also Published As

Publication number Publication date
JPH0834170B2 (en) 1996-03-29

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