JPH0815212B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0815212B2 JPH0815212B2 JP60191717A JP19171785A JPH0815212B2 JP H0815212 B2 JPH0815212 B2 JP H0815212B2 JP 60191717 A JP60191717 A JP 60191717A JP 19171785 A JP19171785 A JP 19171785A JP H0815212 B2 JPH0815212 B2 JP H0815212B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- alas
- superlattice
- phonon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 36
- 150000001875 compounds Chemical class 0.000 description 12
- 239000013078 crystal Substances 0.000 description 9
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 238000001237 Raman spectrum Methods 0.000 description 5
- 238000005247 gettering Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置、特にGaAs基板上に化合物半導体
層をエピタキシャル成長して動作領域を形成する種々の
化合物半導体装置例えば2次元電子ガスチャンネルによ
るFET、いわゆるHEMT等の化合物半導体装置に係わる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, in particular, various compound semiconductor devices for epitaxially growing a compound semiconductor layer on a GaAs substrate to form an operating region, for example, a FET using a two-dimensional electron gas channel. , Related to compound semiconductor devices such as so-called HEMT.
〔発明の概要〕 本発明はGaAs基板上に(AlAs)m(GaAs)nの超格子
構造のバッファを形成し、これの上に化合物半導体例え
ばAlGaAs系化合物半導体をエピタキシャル成長させるこ
とによって高品位の化合物半導体層を形成する。SUMMARY OF THE INVENTION The present invention forms a high-quality compound by forming a buffer of (AlAs) m (GaAs) n superlattice structure on a GaAs substrate and epitaxially growing a compound semiconductor, for example, an AlGaAs-based compound semiconductor on the buffer. A semiconductor layer is formed.
HEMT等の化合物半導体装置においては、例えばCrがド
ープされた半絶縁性GaAs基板上にAlGaAs系の各半導体
層、例えばアンドープのGaAs半導体層、n型のAlGaAs半
導体層、さらにその上にGaAs半導体層が順次例えばMOCV
D(Metalorganic Chemical Vapor Deposition)法或い
はMBE(Molecular Beam Epitaxy)法等によって、順次
エピタキシャル成長してその動作領域、即ちHEMTにおい
ては、2次元電子ガスチャンネルを形成する領域を含む
各領域の形成を行う。この場合、高品質のエピタキシャ
ル層を得るためには、その動作領域を形成する部分例え
ば前述したHEMTにおけるアンドープのGaAs層は数十μm
程度の厚さまで成長させる必要があった。これはGaAs基
板からのCr等の不純物の拡散や結晶欠陥の伝播がGaAs基
板の界面側から生ずることがないようにバッファ層とし
ての機能をもたらしめるために厚い成長膜を形成すると
か或いは実質的にバッファ層の介在を行わしめるもので
ある。In a compound semiconductor device such as HEMT, for example, each AlGaAs semiconductor layer on a semi-insulating GaAs substrate doped with Cr, for example, an undoped GaAs semiconductor layer, an n-type AlGaAs semiconductor layer, and a GaAs semiconductor layer further thereon. Are, for example, MOCV
By the D (Metalorganic Chemical Vapor Deposition) method or the MBE (Molecular Beam Epitaxy) method, epitaxial growth is sequentially performed to form its operation region, that is, in the HEMT, each region including a region for forming a two-dimensional electron gas channel is formed. In this case, in order to obtain a high-quality epitaxial layer, the undoped GaAs layer in the portion forming the operating region, such as the HEMT described above, is several tens of μm.
It was necessary to grow it up to a certain thickness. This is because a thick growth film is formed in order to provide a function as a buffer layer so that diffusion of impurities such as Cr from the GaAs substrate and propagation of crystal defects do not occur from the interface side of the GaAs substrate. The buffer layer is intervened.
近年このエピタキシャル成長層を薄くしても高品質な
エピタキシャル層を得る対策して超格子の構造のバッフ
ァ層を介してエピタキシャル成長をさせる試みがなされ
ている。例えば超格子構造のバッファ層上に連続して成
長させた量子井戸層の光学的特性が改善されるという報
告がある(藤井他;昭和59年春応用物理学会予稿集29P
N−1,アーノルド(D.Arnold)他;アイ・イー・イー・
イー・エレクトロンデバイスレターズ(IEEE Electron
Device Letters)Vol.EDL−5,No.3,82(1984)参照)。
しかしながらこれらの報告においても、その超格子バッ
ファ層の、バッファ層として作用する機構や最適構造に
関する究明、知見等の報告は未だなされていない。In recent years, attempts have been made to perform epitaxial growth through a buffer layer having a superlattice structure as a measure to obtain a high-quality epitaxial layer even if the epitaxial growth layer is thinned. For example, it has been reported that the optical properties of quantum well layers continuously grown on a superlattice buffer layer are improved (Fujii et al .; Spring 1984, Applied Physics Society, Proceedings 29P).
N-1, Arnold and others;
E-Electron Device Letters (IEEE Electron
Device Letters) Vol. EDL-5, No. 3, 82 (1984)).
However, in these reports as well, no report has been made on the investigation and knowledge of the mechanism of the superlattice buffer layer acting as a buffer layer and the optimum structure.
本発明においては、特にGaAs基板上に化合物半導体層
のエピタキシャル成長を形成する場合における化合物半
導体の超格子バッファ層としての機能の究明に基づいて
その有効な構造を提供するものであり、これに基づいて
各種半導体装置、例えばHEMT等の化合物半導体において
その高純度、高品質のエピタキシャル層の形成を可能に
し各種半導体装置例えばHEMTにおける特性改善を図るも
のである。The present invention provides an effective structure based on the investigation of the function of the compound semiconductor layer as a superlattice buffer layer particularly when the compound semiconductor layer is epitaxially grown on a GaAs substrate. It is possible to form a high-purity and high-quality epitaxial layer in various semiconductor devices, for example, compound semiconductors such as HEMT, and improve the characteristics in various semiconductor devices, for example, HEMT.
本発明においては第1図に示すように例えばCrがドー
プされた半絶縁性のGaAs基板(1)上に特定された構造
による超格子バッファ層(2)を介して目的とする動作
領域を形成する半導体層例えばAlGaAs系或いはAlGaInP
系等の半導体層(5)を連続的にMOCVD或いはMBE法等に
よる一連のエピタキシャル工程で形成する。In the present invention, as shown in FIG. 1, a desired operating region is formed on a semi-insulating GaAs substrate (1) doped with Cr, for example, through a superlattice buffer layer (2) having a specified structure. Semiconductor layer such as AlGaAs or AlGaInP
A semiconductor layer (5) of a system or the like is continuously formed by a series of epitaxial processes such as MOCVD or MBE.
超格子バッファ層(2)は(AlAs)m(GaAs)nで、
6≦m≦12,6≦n≦12とする1周期以上の超格子構造と
する。すなわち、不純物は選択的にAlAs層にゲッタさ
れ、そのゲッタリングのためには、AlAs層厚が6原子層
以上(m≧6)必要である事がわかった。この様にする
と、はさまれたGaAsの純度は向上し、従って超格子上の
GaAsの純度も向上する事になる。AlAsのm原子層(3)
とGaAsのn原子層(4)の繰り返し積層した構成とす
る。AlAs層とGaAsとはn=mに選定し得る。The superlattice buffer layer (2) is (AlAs) m (GaAs) n ,
A superlattice structure having one period or more, with 6 ≦ m ≦ 12 and 6 ≦ n ≦ 12. That is, it was found that impurities are selectively gettered in the AlAs layer, and the thickness of the AlAs layer must be 6 atomic layers or more (m ≧ 6) for gettering. This improves the purity of the sandwiched GaAs and therefore the
The purity of GaAs will also be improved. AlAs m atomic layer (3)
And a n-atom layer (4) of GaAs are repeatedly laminated. The AlAs layer and GaAs can be selected so that n = m.
上述したように半絶縁性のGaAs基板上に(AlAs)m及
び(GaAs)nの各原子層の1周期以上の積層による超格
子バッファ層(2)を形成し、これの上に半導体層
(5)をエピタキシャル成長させる場合、この半導体層
(5)としては、高品質で高純度の即ち基板からの例え
ばCr不純物の拡散による侵入が抑えられる。従って電子
移動度の高い半導体層を構成することができる。As described above, the superlattice buffer layer (2) is formed by stacking atomic layers of (AlAs) m and (GaAs) n for one cycle or more on the semi-insulating GaAs substrate, and the semiconductor layer ( In the case of epitaxially growing 5), the semiconductor layer (5) is of high quality and high purity, that is, the invasion of Cr impurities from the substrate is suppressed. Therefore, a semiconductor layer having high electron mobility can be formed.
これは(AlAs)m(GaAs)nの超格子バッファ層
(2)によってGaAs基板からのエピタキシャル成長に際
して混入する不純物例えばCrがAlAs層によってゲットリ
ングされることによる。このAlAsのゲッタリングは、第
3図に示すような混晶と超格子のラマン散乱の結果から
示唆される。即ち、AlGaAs3元混晶でも、(AlAs)m(G
aAs)n超格子でもGaAs的LOフォノンとAlAs的LOフォノ
ンの2つのピークがラマン散乱で見えるが、その後者の
前者に対する強度比IAl/IGaは混晶の場合には、存在比
できまっていることがわかる。すなわち同図において△
印と○印とは夫々AlxGa1-xAs混晶と、(AlAs)m(GaA
s)n超格子との、夫々のx/(1−x)(但しxはAlの
分率、(x−1)はGaの分率)を変化させたときのIAl/
IGaを示したものであるが、混晶の場合は、x/(1−
x)の直線に良くのっているに比し超格子にするとこの
比がx/(1−x)よりずっと小さくなっている。一般に
フォノンピーク強度は結晶の質に比例するのでこのこと
は、AlAs層の質が落ち、反面GaAs層の質は向上したこと
を示すものとみられる。つまり、AlAsによるゲッタリン
グがおこっていると思われる。This is because impurities (eg, Cr) mixed during epitaxial growth from the GaAs substrate are get ringed by the AlAs layer by the superlattice buffer layer (2) of (AlAs) m (GaAs) n . This gettering of AlAs is suggested by the results of Raman scattering of mixed crystal and superlattice as shown in FIG. That is, even with an AlGaAs ternary mixed crystal, (AlAs) m (G
Although two peaks of GaAs-like LO phonon and AlAs-like LO phonon can be seen by Raman scattering even in the aAs) n superlattice, the intensity ratio of the latter, I Al / I Ga , to the former is not abundant in the mixed crystal. You can see that That is, in the figure
The mark and the circle mark are the Al x Ga 1-x As mixed crystal and (AlAs) m (GaA
s) I Al / when changing each x / (1-x) (where x is the Al fraction and (x-1) is the Ga fraction) with the n superlattice
I Ga is shown, but in the case of a mixed crystal, x / (1-
This ratio is much smaller than x / (1-x) when it is made into a superlattice, in contrast to the straight line of x). Since the phonon peak intensity is generally proportional to the quality of the crystal, this seems to indicate that the quality of the AlAs layer deteriorates while the quality of the GaAs layer improves. In other words, it seems that gettering by AlAs occurs.
第4図,第5図,第6図及び第7図は夫々(AlAs)m
(GaAs)n超格子構造のm=nとし、夫々n=6,8,12,2
としたときのラマンスペクトルを示し、第8図はAl0.5G
a0.5Asの混晶の同様のラマンスペクトルを示す。また第
9図中曲線(31)及び(32)は夫々(AlAs)m(GaAs)
n超格子構造のm=nとしたときのラマンスペクトルに
おけるAlAs的LOフォノン及びGaAs的LOフォノンの各ピー
ク強度のnの値に対する依存性を示したものであり、同
図中×印及び○印は夫々そのAlAs的フォノン及びGaAs的
フォノンの各nの値を変化させたときの各ピーク強度の
測定値をプロットしたものである。これによれば、AlAs
的LOフォノンのピーク強度は、n=6以上でほぼ一定と
なりまたGaAs的LOフォノンの強度は、nの増加と共に増
大し、m=n=6〜12でAlAs的LOフォノンピーク強度が
GaAs的LOフォノンピーク強度に比し充分小さくなること
が分かる。すなわち、フォノンのピーク強度はLOフォノ
ンの寿命に比例するものであるので、nの増加と共にフ
ォノンの寿命が増加していること、つまりGaAsの純度が
向上していることが分かる。また第10図は同様のn値に
対するLOフォノンピークの半値幅の依存性を示すもの
で、第10図において○印はGaAs的LOフォノンの半値幅、
△印はAlAs的LOフォノンのそれを示す。これによれば両
者共nの増大と共に半値幅が減少しn=6以上でほぼ一
定になることが分かる。即ちフォノンのピークの反値幅
はLOフォノンの寿命の逆数に比例するのでn(=m)が
増大するにつれてLOフォノンのダンピングが小さくなり
エピタキシャル層の結晶性が良くなっていることが分か
る。つまり(AlAs)m(GaAs)n超格子構造では、エピ
タキシャル成長の際に混入する不純物がAlAs層によって
ゲッタリングされ、n=m=6〜12GaAs層及びAlAs層の
純度が向上しており、このような構造がバッファ層とし
て有効であることを示している。4, 5, 6 and 7 are (AlAs) m, respectively.
(GaAs) n superlattice structure m = n, and n = 6,8,12,2, respectively
The Raman spectrum is shown in Fig. 8. Fig. 8 shows Al 0.5 G
A similar Raman spectrum of a mixed crystal of a 0.5 As is shown. Curves (31) and (32) in FIG. 9 are (AlAs) m (GaAs), respectively.
This figure shows the dependence of each peak intensity of AlAs-like LO phonons and GaAs-like LO phonons on the n value in the Raman spectrum of n superlattice structure where m = n. Are plots of the measured values of the respective peak intensities when the respective n values of the AlAs-like phonon and the GaAs-like phonon are changed. According to this, AlAs
The LO intensity of the LO phonon is almost constant when n = 6 or more, and the intensity of the LO phonon of GaAs increases with the increase of n, and the peak intensity of the LO phonon of AlAs is m = n = 6 to 12.
It can be seen that it is sufficiently smaller than the GaAs-like LO phonon peak intensity. That is, since the peak intensity of phonons is proportional to the lifetime of LO phonons, it can be seen that the lifetime of phonons increases as n increases, that is, the purity of GaAs improves. Further, FIG. 10 shows the dependence of the half width of the LO phonon peak on the similar n value. In FIG. 10, the circles indicate the half width of the GaAs LO phonon.
The triangle marks show that of AlAs-like LO phonons. According to this, it can be seen that the half-widths decrease with increasing n and become almost constant when n = 6 or more. That is, since the inverse width of the phonon peak is proportional to the reciprocal of the LO phonon lifetime, it can be seen that the damping of the LO phonons decreases and the crystallinity of the epitaxial layer improves as n (= m) increases. That is, in the (AlAs) m (GaAs) n superlattice structure, impurities mixed during the epitaxial growth are gettered by the AlAs layer, and the n = m = 6 to 12 GaAs layer and the AlAs layer are improved in purity. It is shown that this structure is effective as a buffer layer.
第2図はHEMTに本発明を適用した場合の一例で、この
例ではCrがドープされた半絶縁性のGaAs基板(1)上に
(AlAs)6(GaAs)6の2〜3周期の超格子バッファ層
(2)を形成し、これの上に不純物がドープされない厚
さ2μmのGaAs層より成る第1の半導体層(13)、さら
にこれの上にノーンドープのAlGaAs層より成る第2の半
導体層(14)、さらにこれの上に例えばn型のAl0.3Ga
0.7As層より成る第3の半導体層(15)を形成した。こ
れら層(2),(13)〜(15)は、連続的にMOCVD法或
いはMBE法によって供給する原料ガスを切換ることによ
って一連のエピタキシャル工程で形成できる。そして、
層(15)に対してショットキゲート電極(16)を被着
し、これの両側にソース及びドレインの各電極(17)及
び(18)を夫々オーミックに被着した。この場合、GaAs
の第1の半導体層(13)のAlGaAsの第2の半導体層(1
4)との界面に2次元電子ガスチャンネルが形成される
ものであるが、これら層(13)及び(14)の界面部分は
すぐれた純度及び結晶性を有するので、より高い電子移
動度が得られ、高速性にすぐれたHEMTが構成できる。FIG. 2 shows an example in which the present invention is applied to a HEMT. In this example, a super-insulating (AlAs) 6 (GaAs) 6 having a period of 2 to 3 is formed on a semi-insulating GaAs substrate (1) doped with Cr. A lattice buffer layer (2) is formed on which a first semiconductor layer (13) made of a 2 μm thick GaAs layer which is not doped with impurities, and a second semiconductor made of a non-doped AlGaAs layer thereon. A layer (14), on top of which, for example, n-type Al 0.3 Ga
A third semiconductor layer (15) consisting of a 0.7 As layer was formed. These layers (2), (13) to (15) can be formed by a series of epitaxial processes by continuously switching the source gas supplied by the MOCVD method or the MBE method. And
A Schottky gate electrode (16) was deposited on the layer (15), and source and drain electrodes (17) and (18) were ohmicly deposited on both sides of the Schottky gate electrode (16). In this case, GaAs
The first semiconductor layer (13) of the AlGaAs second semiconductor layer (1
A two-dimensional electron gas channel is formed at the interface with 4), but since the interface portions of these layers (13) and (14) have excellent purity and crystallinity, higher electron mobility can be obtained. Therefore, a HEMT with high speed can be configured.
また本発明は、上述した例に限らず、種々の化合物半
導体装置においてGaAs基板上にその動作層ないしは活性
層をエピタキシャル成長させる場合に基板上にバッファ
層(2)を形成し、これの上に目的とする動作層ないし
は活性層を形成することができる。Further, the present invention is not limited to the above-mentioned examples, and in various compound semiconductor devices, when the operation layer or the active layer is epitaxially grown on the GaAs substrate, the buffer layer (2) is formed on the substrate, and the object is formed thereon. It is possible to form an operating layer or an active layer.
上述したように本発明においては(AlAs)m(GaAs)
nのm=n=6〜12で2〜3周期の超格子構造の極めて
薄いバッファ層(2)を設けるのみで基板(1)側から
のCr等の不純物をゲッタリングする効果を得ることがで
き、これの上に形成するエピタキシャル半導体層の純度
を向上しキャリア移動度の高い高品質の半導体層を形成
できるので、各種化合物半導体装置の動作領域をエピタ
キシャルする場合に用いて特性の向上をはかることがで
きる。As described above, in the present invention, (AlAs) m (GaAs)
very thin buffer layer of n of m = n = 6 to 12 with 2 to 3 periods of the superlattice structure (2) has the advantages of gettering impurities such as Cr from the substrate (1) side only provided Since it is possible to improve the purity of the epitaxial semiconductor layer formed thereon and to form a high-quality semiconductor layer with high carrier mobility, it is possible to improve the characteristics by using it when epitaxially operating regions of various compound semiconductor devices. be able to.
第1図は本発明装置の一例の要部の略線的拡大断面図、
第2図は本発明をHEMTに適用した場合の一例の略線的拡
大断面図、第3図〜第7図は夫々(AlAs)m(GaAs)n
のラマンスペクトル図、第8図はAlGaAs混晶のラマンス
ペクトル図、第9図及び第10図は夫々(AlAs)m(GaA
s)n(m=n)のラマンスペクトルのフォノンピーク
強度及び半値幅のnの値に対する依存性を示す図であ
る。 (1)はGaAs基板、(2)は超格子バッファ層である。FIG. 1 is an enlarged schematic cross-sectional view of a main part of an example of the device of the present invention,
FIG. 2 is a schematic enlarged cross-sectional view of an example in which the present invention is applied to HEMT, and FIGS. 3 to 7 are (AlAs) m (GaAs) n, respectively.
8 Raman spectrum of AlGaAs mixed crystal, and Figures 9 and 10 show (AlAs) m (GaA
s) It is a figure which shows the dependence with respect to the value of n of the phonon peak intensity and half width of the Raman spectrum of n (m = n). (1) is a GaAs substrate, and (2) is a superlattice buffer layer.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/812 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 29/812
Claims (1)
m≦12,6≦n≦12の1周期以上の超格子構造によるバッ
ファ層を介して動作領域となる半導体層をエピタキシャ
ル成長させて成り、GaAs的LOフォノンピークに比し、Al
As的LOフォノンピークの強度が小とされ、GaAs基板から
の不純物がAlAsにゲッタリングされてなることを特徴と
する半導体装置。1. On a GaAs substrate, (AlAs) m (GaAs) n with 6 ≦
It is formed by epitaxially growing a semiconductor layer to be an operating region through a buffer layer having a superlattice structure of m ≦ 12, 6 ≦ n ≦ 12 for one period or more.
A semiconductor device characterized in that the intensity of the As-like LO phonon peak is low and impurities from the GaAs substrate are gettered into AlAs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60191717A JPH0815212B2 (en) | 1985-08-30 | 1985-08-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60191717A JPH0815212B2 (en) | 1985-08-30 | 1985-08-30 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6251266A JPS6251266A (en) | 1987-03-05 |
JPH0815212B2 true JPH0815212B2 (en) | 1996-02-14 |
Family
ID=16279306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60191717A Expired - Lifetime JPH0815212B2 (en) | 1985-08-30 | 1985-08-30 | Semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JPH0815212B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07120792B2 (en) * | 1987-09-04 | 1995-12-20 | 日本電気株式会社 | Semiconductor device |
EP0323249B1 (en) * | 1987-12-29 | 1993-11-03 | Nec Corporation | Semiconductor crystal structure and a process for producing the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5929462A (en) * | 1982-08-10 | 1984-02-16 | Mitsubishi Electric Corp | Hetero-junction element |
JPS61216317A (en) * | 1985-03-20 | 1986-09-26 | Nippon Telegr & Teleph Corp <Ntt> | Method for formation of single crystal gaas layer on single crystal gaas substrate |
-
1985
- 1985-08-30 JP JP60191717A patent/JPH0815212B2/en not_active Expired - Lifetime
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JPS6251266A (en) | 1987-03-05 |
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