JPS6146031A - Semiconductor laminating structure - Google Patents

Semiconductor laminating structure

Info

Publication number
JPS6146031A
JPS6146031A JP59167991A JP16799184A JPS6146031A JP S6146031 A JPS6146031 A JP S6146031A JP 59167991 A JP59167991 A JP 59167991A JP 16799184 A JP16799184 A JP 16799184A JP S6146031 A JPS6146031 A JP S6146031A
Authority
JP
Japan
Prior art keywords
substrate
single crystal
buffer layer
znse
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59167991A
Other languages
Japanese (ja)
Other versions
JP2647824B2 (en
Inventor
Yuji Hishida
有二 菱田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP16799184A priority Critical patent/JP2647824B2/en
Publication of JPS6146031A publication Critical patent/JPS6146031A/en
Application granted granted Critical
Publication of JP2647824B2 publication Critical patent/JP2647824B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02387Group 13/15 materials
    • H01L21/02395Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02463Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/0256Selenides

Abstract

PURPOSE:To enable an electrode to be led out from the reverse surface of a semiconductor substrate even in a device which employs ZnSe single crystal, by laminating ZnSe single crystal on the substrate through a buffer layer, and continuoulsy changing the electron effinity of the buffer layer. CONSTITUTION:ZnSe single crystal 13 is laminated on a semiconductor substrate 11 through a buffer layer 12. The electron affinity of the buffer layer 12 is continuously changed so that the electron affinity of the layer 12 on the side thereof which is closer to the substrate 11 is substantially the same as that of the substrate 11, and the electron affinity of the layer 12 on the side thereof which is closer to the ZnSe single crystal 13 is substantially the same as that of the ZnSe 13. For example, a buffer layer 12 is formed on a substrate 11 made of n type GaAs single crystal, the layer 12 being made of n type Ga1-xAlxAs single crystal in which the Al molar ratio X changes from 0-0.13 toward the surface of the layer 12 from the side thereof which is closer to the substrate 11, and an n type ZnSe single crystal 13 is laminated on the layer 12. Thus, it is possible to reduce the conductor disnotinuity between the substrate 11 and the ZnSe single crystal 13 so that no rectifying porperty is produced.

Description

【発明の詳細な説明】 げ)産業上の利用分野 本発明はZnSe(ジンクセレン)単結晶を含む半導体
積層構造に関する。
DETAILED DESCRIPTION OF THE INVENTION G) Industrial Application Field The present invention relates to a semiconductor laminated structure containing ZnSe (zinc selenium) single crystal.

(ロ)従来技術 ZnSe単結晶は室温2.7eVのバンドギャップを有
するため青色発光材料として有望視されているが、末だ
実用化に到っていない。この原因は第1にはZnSe単
結晶が従来法では高品質なものが得られなかったことに
あり、第2IこはZnSe単結晶は自己補償効果が強く
n型伝導しか示さないためpn接合を形成することがで
きないことにある。
(b) Prior Art ZnSe single crystal has a band gap of 2.7 eV at room temperature and is therefore seen as promising as a blue light emitting material, but it has not yet been put into practical use. The first reason for this is that high-quality ZnSe single crystals cannot be obtained using conventional methods, and the second reason is that ZnSe single crystals have a strong self-compensation effect and only exhibit n-type conduction, so p-n junctions cannot be used. It lies in the inability to form.

上記第1の問題は従来の液相、気相成長方法等とは全(
異なる熱的非平衡状態からの成長であるMBE(分子線
エピタキシャル)成長方法を用いることで解決される。
The first problem mentioned above is that conventional liquid phase and vapor phase growth methods are completely different from each other (
This problem is solved by using the MBE (molecular beam epitaxial) growth method, which is growth from different thermal non-equilibrium states.

その具体的な成長方法は例えば特願昭57−12646
5号に開示されている。
For example, the specific growth method is disclosed in Japanese Patent Application No. 57-12646.
It is disclosed in No. 5.

また第2の問題は接合型をMIS型とすることにより解
決される。
The second problem is solved by using the MIS type as the junction type.

第3図はZnSe単結晶からなるMis型発光発光ダイ
オード式的に示し、(1)は例えばn ljl GλA
s単結晶からなる基板、<27は該基板上1ζMBE成
長方法により積層されたn盟ZnSe単結晶層、(3)
は該単結晶層上に積層された絶縁層、(4)は該絶縁層
上に積層された例えばAut#Jからなる金属層である
FIG. 3 schematically shows a Mis-type light emitting diode made of ZnSe single crystal, and (1) is, for example, n ljl GλA
A substrate made of s single crystal, <27 is an n-ZnSe single crystal layer stacked on the substrate by a 1ζMBE growth method, (3)
(4) is an insulating layer laminated on the single crystal layer, and (4) is a metal layer made of, for example, Aut#J, laminated on the insulating layer.

斯る構成では確かにんflsfi接合部に順方向バイア
スを印加することにより所望の青色発光が得られる。然
るに上記基板(1)は単にZ II S e単結晶との
熱膨張係数及び格子定数等の物理的特性により選択され
たものであり、電子親和力及びバンドギャップ等の電子
的特性は一斉考慮されていない。
In such a configuration, the desired blue light emission can certainly be obtained by applying a forward bias to the flsfi junction. However, the above substrate (1) was selected simply based on its physical properties such as the thermal expansion coefficient and lattice constant relative to the Z II S e single crystal, and the electronic properties such as electron affinity and band gap were not taken into consideration. do not have.

従って、物理的特性・の鑑点のみから選ばれたGaAs
、Ge等の基板とZnSeとの接合部には整流性が発生
し、このため上記基板(1)裏面からの電極取出しが不
可能となりでいた。
Therefore, GaAs was selected only from the viewpoint of physical properties.
Rectifying properties occur at the junction between ZnSe and the substrate made of Ge, etc., making it impossible to take out the electrode from the back surface of the substrate (1).

(/1 発明が解決しようとする問題点本発明は斯る点
に鑑みてなされたもので、ZnSeと略等しい物理的特
性を有する基板上にZnSe単結晶を成長させたものに
おいて、上記整流性を消滅させることが可能な半導体積
層構造を提供せんとするものである。
(/1 Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned problems, and in a product in which a ZnSe single crystal is grown on a substrate having approximately the same physical properties as ZnSe, the above-mentioned rectification property is improved. The purpose of the present invention is to provide a semiconductor stacked structure that can eliminate the

に)問題点を解決するための手段 本発明の上記目的を達成するための特徴点は、半導体基
板、該基板上に積層されたバッファ層、該バッファ層上
に積層されたZnSe単結晶からなり、上記バッファ層
は上記基板側では斯る基板の電子親和力と略同一となり
、上記ZnSe単結晶側では斯るZn5cの電子親和力
と略同一となるように電子親和力が連続的に変化してい
ることにある。
B) Means for Solving the Problems The features of the present invention for achieving the above-mentioned objects include a semiconductor substrate, a buffer layer laminated on the substrate, and a ZnSe single crystal laminated on the buffer layer. , the electron affinity of the buffer layer on the substrate side is approximately the same as that of the substrate, and the electron affinity on the ZnSe single crystal side is continuously changing so that it is approximately the same as the electron affinity of Zn5c. It is in.

匝)作用 このように基板とZnSe単結晶との間にバッファ層を
介装せしめると、n型基板上にn型バ・ソファ層を成長
させることにより基板とZnSe単結晶との伝導帯の不
連続を整流性が生じないように減少でき、またP型基板
上にP型バッファ層を成長させることにより基板とZn
Se単結晶との価電子帯の不連続を整流性が生じないよ
うに減少できる。
匝) Function When a buffer layer is interposed between the substrate and the ZnSe single crystal in this way, the conduction band gap between the substrate and the ZnSe single crystal is changed by growing the n-type buffer layer on the n-type substrate. The continuity can be reduced so that rectification does not occur, and by growing a P-type buffer layer on a P-type substrate, the substrate and Zn
Discontinuity in the valence band with the Se single crystal can be reduced so that rectification does not occur.

ト)実施例 第1図は本発明の一実施例を示し、(1))はn型Ga
kg単結晶からなる基板、(2)は該基板上をこ積層さ
れたバv 7 y層であり、該バッファ層はn型Ga1
−xAj7xAs (ガリウムアルミ砒素)単結晶から
なり、そのAI!モル比Xが基板αυ側より表面に向っ
て0〜0.13まで変化する。
g) Example FIG. 1 shows an example of the present invention, (1)) is an n-type Ga
kg single crystal substrate, (2) is a buffer layer laminated on the substrate, and the buffer layer is an n-type Ga1
-xAj7xAs (Galium Aluminum Arsenide) made of single crystal, its AI! The molar ratio X changes from 0 to 0.13 from the substrate αυ side toward the surface.

斯るバッファ層■は例えば周知のMBE(分子線エピタ
キシャル)成長方法により形成できる。
Such a buffer layer (1) can be formed, for example, by the well-known MBE (molecular beam epitaxial) growth method.

具体的な成長条件は1O−10Torr以下に排気され
た超高真空中において基板圓を600℃、Gaセル温度
を1010℃、Asセル温度830℃に固定すると共に
AI!セル温度を500℃から1)00℃まで10℃/
 m i nの速度で変化させる。
The specific growth conditions were to fix the substrate circle at 600°C, the Ga cell temperature at 1010°C, and the As cell temperature at 830°C in an ultra-high vacuum evacuated to 10-10 Torr or less, and to use AI! Increase cell temperature from 500℃ to 1) 00℃ by 10℃/
change at a speed of min.

(2)は上記バッファ層@上に積層されたn型ZnSe
単結晶であり、該単結晶もMBF−成長方法により形成
でき、その成長条件は基板温度を320℃、Znセル温
度300℃、Seセル温度を420℃とする。
(2) is the n-type ZnSe layered on the buffer layer
It is a single crystal, and the single crystal can also be formed by the MBF-growth method, and the growth conditions are a substrate temperature of 320°C, a Zn cell temperature of 300°C, and a Se cell temperature of 420°C.

第2図は本実施例の半導体積層構造のバンド構造を示し
、図中α引ヨ真空準位、叫は伝導バンド、(161はフ
ェルミレベル、α力は価電子バンドである。
FIG. 2 shows the band structure of the semiconductor laminated structure of this example, in which the α force is the vacuum level, the conduction band (161 is the Fermi level, and the α force is the valence band).

第2図より明らかなように、本実施例の構造では伝導バ
ンドの不連続性は存在しないため、整流性は生じない。
As is clear from FIG. 2, in the structure of this example, there is no discontinuity in the conduction band, so no rectification occurs.

参考までに上記バッファ層α2が存在しないときのバン
ド構造を第4図に示すと、n型Cy a A s単結晶
とn型ZnS e単結晶とのバンドギャップエネルギ差
により界面に伝導バンドの不連続性(18)が生じ整流
性を生じることとなる。
For reference, the band structure when the buffer layer α2 does not exist is shown in FIG. 4. Due to the difference in band gap energy between the n-type Cy a As single crystal and the n-type ZnSe single crystal, there is a conduction band defect at the interface. Continuity (18) occurs and rectification occurs.

尚、本実施例ではバッファ層材料としてGa1−x A
 j’ x A sを用いたが、Ga1−xA1!xs
b(ガリウムニルアルミアンチモン)、Ga1−xAl
!xsbyAS1−γ(ガリウムアルミアンチモン砒素
)等基板及びZn5cと物理的、電子的特性が近似する
材料を用いても良く、また基板材料としてG a A 
sを用いたがこれに換えて少なくとも7.nSeと物理
的特性が近似するGe等用いることも可能である。
In this example, Ga1-x A is used as the buffer layer material.
j' x A s was used, but Ga1-xA1! xs
b (gallium nil aluminum antimony), Ga1-xAl
! Materials having physical and electronic properties similar to those of the substrate and Zn5c, such as xsbyAS1-γ (gallium aluminum antimony arsenide), may also be used, and G a A as the substrate material.
s was used, but instead of this, at least 7. It is also possible to use Ge, etc., which has similar physical properties to nSe.

(ト)効果 本発明の半導体積層構造を用いれば、Zn5 e単結晶
を用いたデバイスにおいても基板裏面より電極を取出す
ことが可能となる。
(g) Effects If the semiconductor stacked structure of the present invention is used, it becomes possible to take out the electrode from the back surface of the substrate even in a device using a Zn5e single crystal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2図及び第
4図はバンド構造を示す模式図、第3図は従来例を示す
断面図である。 αD・・・基板、α2・・・バッファ層、(2)・・・
ZnSe単結晶。
FIG. 1 is a sectional view showing an embodiment of the present invention, FIGS. 2 and 4 are schematic views showing a band structure, and FIG. 3 is a sectional view showing a conventional example. αD...Substrate, α2...Buffer layer, (2)...
ZnSe single crystal.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板、該基板上に積層されたバッファ層、
該バッファ層上に積層されたZnSe単結晶からなり、
上記バッファ層は上記基板側では斯る基板の電子親和力
と略同一となり、上記ZnSe単結晶側では斯るZnS
eの電子親和力と略同一となるように電子親和力が連続
的に変化していることを特徴とする半導体積層構造。
(1) A semiconductor substrate, a buffer layer laminated on the substrate,
Consisting of a ZnSe single crystal layered on the buffer layer,
On the substrate side, the buffer layer has approximately the same electron affinity as the substrate, and on the ZnSe single crystal side, the ZnS
A semiconductor stacked structure characterized in that the electron affinity continuously changes to be approximately the same as the electron affinity of e.
JP16799184A 1984-08-10 1984-08-10 Semiconductor laminated structure Expired - Lifetime JP2647824B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16799184A JP2647824B2 (en) 1984-08-10 1984-08-10 Semiconductor laminated structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16799184A JP2647824B2 (en) 1984-08-10 1984-08-10 Semiconductor laminated structure

Publications (2)

Publication Number Publication Date
JPS6146031A true JPS6146031A (en) 1986-03-06
JP2647824B2 JP2647824B2 (en) 1997-08-27

Family

ID=15859771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16799184A Expired - Lifetime JP2647824B2 (en) 1984-08-10 1984-08-10 Semiconductor laminated structure

Country Status (1)

Country Link
JP (1) JP2647824B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786603A (en) * 1995-09-12 1998-07-28 Kabushiki Kaisha Toshiba Multilayer structured semiconductor devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039076A (en) * 1973-08-08 1975-04-10
JPS5870573A (en) * 1981-10-22 1983-04-27 Nec Corp Compound semiconductor fet
JPS5916393A (en) * 1982-07-19 1984-01-27 Sanyo Electric Co Ltd Blue light emitting element
JPS59211267A (en) * 1983-05-17 1984-11-30 Toshiba Corp Hetero junction bipolar transistor
JPS60160166A (en) * 1984-01-30 1985-08-21 Nec Corp Bypolar transistor with hetero junction collector

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039076A (en) * 1973-08-08 1975-04-10
JPS5870573A (en) * 1981-10-22 1983-04-27 Nec Corp Compound semiconductor fet
JPS5916393A (en) * 1982-07-19 1984-01-27 Sanyo Electric Co Ltd Blue light emitting element
JPS59211267A (en) * 1983-05-17 1984-11-30 Toshiba Corp Hetero junction bipolar transistor
JPS60160166A (en) * 1984-01-30 1985-08-21 Nec Corp Bypolar transistor with hetero junction collector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786603A (en) * 1995-09-12 1998-07-28 Kabushiki Kaisha Toshiba Multilayer structured semiconductor devices

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