JPH03148183A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH03148183A
JPH03148183A JP1286451A JP28645189A JPH03148183A JP H03148183 A JPH03148183 A JP H03148183A JP 1286451 A JP1286451 A JP 1286451A JP 28645189 A JP28645189 A JP 28645189A JP H03148183 A JPH03148183 A JP H03148183A
Authority
JP
Japan
Prior art keywords
semiconductor
thin film
insulating layer
quantum
film insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1286451A
Other languages
Japanese (ja)
Inventor
Akito Hara
明人 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1286451A priority Critical patent/JPH03148183A/en
Publication of JPH03148183A publication Critical patent/JPH03148183A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a quantum level of a carrier by a simple structure by realizing nonlinear conduction characteristic by resonance tunnel effect of quantized two-dimensional carrier which is formed at an interface between two semiconductor substrates and a thin film insulating layer. CONSTITUTION:A triangular potential well is formed at an interface between semiconductor substrates 2, 4 and a thin film insulating layer 6 by an SIS (semiconductor-insulator-semiconductor) structure which means that a thin film insulating layer is held between two semiconductor substrates. Quantum levels of two-dimensional carrier formed in the triangular potential well at the both sides holding the thin film insulating layer 6 between are relatively changed by using that a two-dimensional carrier stored in a triangular potential well is quantized. Nonlinear current-voltage characteristic is realized by making a large resonance tunnel current flow only when either of quantum levels at both sides coincides. Thereby, a quantum level of a carrier can be formed by a simple structure.

Description

【発明の詳細な説明】 [概要] 半導体装置及びその製造方法に係り、特に5IS(半導
体−絶縁体一半導体>m造を有する非線形伝導量子デバ
イス及びその製造方法に関し、極めて簡単な構造でキャ
リアの量子準位が形成されると共に、容易に製造するこ
とができる非線形伝導特性の半導体装置を提供すること
を目的とし、 2つの半導体基板と、前記2つの半導体基板に挟まれた
薄膜絶縁層とを具備し、l1fj記2つの半導体基板と
前記薄膜絶縁層との界面に形成される量子化された2次
元キャリアの共鳴トンネル効果により、非線形伝導特性
を有するように構成する。
[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a nonlinear conduction quantum device having a 5IS (semiconductor-insulator-semiconductor>m structure) and a method for manufacturing the same, in which carriers can be produced with an extremely simple structure. The purpose of the present invention is to provide a semiconductor device in which a quantum level is formed and which has nonlinear conduction characteristics that can be easily manufactured. The device is configured to have nonlinear conduction characteristics due to a resonant tunneling effect of quantized two-dimensional carriers formed at the interface between the two semiconductor substrates and the thin film insulating layer.

[産業上の利用分野] 本発明は半導体装置及びその製造方法に係り、特に5I
S(半導体〜絶縁体−半導体)構造を有する非線形伝導
量子デバイス及びその製造方法に関する。
[Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a 5I
The present invention relates to a nonlinear conduction quantum device having an S (semiconductor-insulator-semiconductor) structure and a method for manufacturing the same.

[従来の技術] 次世代の新機能素子として、電子の波動性を利用した量
子デバイスが重要視されている。そしてこうした量子デ
バイスの電子の波動性を実現するために、従来は、MB
E (分子線エピタキシャル法)やMOCVD <有機
金属気相成長法)を用いて、構成原子及びバンドギャッ
プの異なる薄膜結晶を堆積し、電子の量子準位を形成す
る方法か一般的であった。
[Prior Art] Quantum devices that utilize the wave nature of electrons are gaining importance as next-generation new functional devices. In order to realize the wave nature of electrons in quantum devices, conventionally, MB
A common method was to use E (molecular beam epitaxial method) or MOCVD (metal-organic vapor phase epitaxy) to deposit thin film crystals with different constituent atoms and band gaps to form electron quantum levels.

[発明が解決しようとする課題] しかし、上記従来の量子デバイスを形成するため用いた
MBE’PMOCVD等の技術は、例えば10−” T
orr程度の超高真空を必要としたり、結晶成長の速度
が遅くて効率が悪かったり、或いは有毒なガスを必要と
したりするといった問題を有していた。
[Problems to be Solved by the Invention] However, the techniques such as MBE'PMOCVD used to form the conventional quantum device described above, for example,
This method has problems such as requiring an ultra-high vacuum of about 1000 m or more, slow crystal growth resulting in poor efficiency, and requiring toxic gas.

そこで本発明は、極めて簡単な構造でキャリアの量子準
位が形成されるとj〔に、容易に製造することができる
非線形伝導特性の半導体装置を提供することを目的とす
る。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device with nonlinear conduction characteristics that can be easily manufactured when a carrier quantum level is formed with an extremely simple structure.

[課題を解決するだめの手段] 上記課題は、2つの半導体基板と、前記2つの半導体基
板に挟まれた薄膜絶縁層とを具面し、前記2つの半導体
基板と前記薄膜絶縁層との界面に形成される量子化され
た2次元キャリアの共鳴トンネル効果により、非線形伝
導特性を有することを特徴とする半導体装置によって達
成される。
[Means for solving the problem] The above problem includes two semiconductor substrates and a thin film insulating layer sandwiched between the two semiconductor substrates, and an interface between the two semiconductor substrates and the thin film insulating layer. This is achieved by a semiconductor device characterized by having nonlinear conduction characteristics due to the resonant tunneling effect of quantized two-dimensional carriers formed in the semiconductor device.

また上記課題は、2つの半導体基板上にそれぞれ薄膜絶
縁層を形成する工程と、前記2つの半導体基板上の前記
薄膜絶縁層を互いに貼り合わせて半導体−絶縁体一半導
体構造を形成する工程とを有することを特徴とする半導
体装置の製造方法によって達成される。
The above problem also includes a step of forming thin film insulating layers on two semiconductor substrates, and a step of bonding the thin film insulating layers on the two semiconductor substrates to each other to form a semiconductor-insulator-semiconductor structure. This is achieved by a method of manufacturing a semiconductor device characterized by having the following characteristics.

[作 用] ) すなわち本発明は、2つの半導体基板に薄膜絶縁層が挟
まれているSIS構造により、半導体基板と薄膜絶縁層
との界面に三角ポテンシャル井戸が形成され、更にこの
三角ポテンシャル井戸に蓄積された2次元キャリアが量
子化されることを利用し、薄膜絶縁層を挟む両側の三角
ポテンシャル井戸に形成された2次元キャリアの量子準
位を相対的に変化させ、両側の量子準位のいずれかが一
致する場合にのみ大きな共鳴トンネル電流が流れるよう
にして、非線形の電流−電圧特性を実現する。
[Function]) That is, in the present invention, a triangular potential well is formed at the interface between the semiconductor substrate and the thin film insulating layer by an SIS structure in which a thin film insulating layer is sandwiched between two semiconductor substrates, and a triangular potential well is further formed in this triangular potential well. Utilizing the fact that the accumulated two-dimensional carriers are quantized, the quantum levels of the two-dimensional carriers formed in the triangular potential wells on both sides of the thin film insulating layer are relatively changed, and the quantum levels on both sides are changed. A large resonant tunneling current flows only when either of them matches, thereby realizing nonlinear current-voltage characteristics.

[実線例] 以下、本発明を図示する実線例に基づいて具体的に説明
する。
[Solid line example] Hereinafter, the present invention will be specifically described based on a solid line example.

第1図は本発明の一実施例による非線形伝導量子デバイ
スを示す断面図である。
FIG. 1 is a cross-sectional view showing a nonlinear conduction quantum device according to an embodiment of the present invention.

2つの半導体基板、例えば(11A S基板2,4の間
に、厚さ100〜・200へのInAs酸化膜6が挟ま
れ、SISwJ造を形成している。そしてInAs基板
2,4上面及び底面上には、それぞれ例えばPb(鉛)
からなるオーミック電極8゜10が設けられている。
An InAs oxide film 6 with a thickness of 100 to 200 mm is sandwiched between two semiconductor substrates, for example (11A S substrates 2 and 4), forming a SISwJ structure. On top, for example, Pb (lead)
An ohmic electrode 8°10 consisting of the following is provided.

次に、こうした5ISI造の非線形伝導量子デバイスの
エネルギーバンドを第2図に示す。
Next, FIG. 2 shows the energy band of such a 5ISI nonlinear conduction quantum device.

InAs基板2,4とI n A s酸化WA6との界
面においては、キャリア密度が減少するため、バンドギ
ャップの曲がりが生じる。そしてこの部分に2次元電子
が蓄積される。
At the interface between the InAs substrates 2 and 4 and the InAs oxidized WA 6, carrier density decreases, resulting in band gap bending. Two-dimensional electrons are accumulated in this part.

I nAs基板2.4とI nAs1l化膜6とが接触
している場合、バンドギャップの曲がりが急峻であるた
め、その界面の伝導帯に三角ポテンシャル井戸12.1
4が形成される。そして第2図の縮退電子系のバンド図
に示されるように、この三角ポテンシャル井戸12.1
4に蓄積された2次元電子が量子1ヒされ、それぞれ量
子準位El、E2、・・・が形成される。
When the InAs substrate 2.4 and the InAs1l film 6 are in contact, the bandgap curve is steep, so a triangular potential well 12.1 is formed in the conduction band at the interface.
4 is formed. As shown in the band diagram of the degenerate electron system in Figure 2, this triangular potential well 12.1
The two-dimensional electrons accumulated in the electron beam 4 are subjected to a quantum one, and quantum levels El, E2, . . . are formed, respectively.

次に、第3図を用いて、動作を説明する。Next, the operation will be explained using FIG.

I nAs基板2111!lのオーミック電極8に正の
電圧を、TnAs基板4側のオーミック電vf!10に
負の電圧をそれぞれ印加すると、第3図(a)に示され
るように、InAs酸化膜6を挟む両側の三角ポテンシ
ャル井戸12.14に形成された2次元電子の量子準位
El、E2.・・・は互いにズレを生じて、いずれの量
子準位El、E2.・・・も−致しなくなる。従ってI
nAs基板2,4間には、十分に薄い厚さのI nAs
酸化膜6をl・ンネル効果によって透過するトンネル電
流が流れるのみで、その電流値は小さい。
InAs substrate 2111! A positive voltage is applied to the ohmic electrode 8 of l, and the ohmic voltage vf! of the TnAs substrate 4 side is applied. When a negative voltage is applied to each of 10 and 10, as shown in FIG. .. ... are shifted from each other, and none of the quantum levels El, E2 . ...will no longer be possible. Therefore I
Between the nAs substrates 2 and 4 is a sufficiently thin InAs substrate.
Only a tunnel current that passes through the oxide film 6 due to the l-channel effect flows, and the current value is small.

次いで、I nAs基板2,4上面及び底面上のそれぞ
れのオーミック電[8,10に印加する電圧を増加して
いくと、第3図(b)に示されるように、InAs基板
2側の三角ポテンシャル井戸12に形成された量子準位
E2とInAs基板4測の三角ポテンシャル井戸14に
形成された量子準位E1とが一致するようになる。従っ
て、両準位間において共鳴トンネル効果が生じるため、
大きな共鳴1−ンネル電流がInAs酸化膜6を透過し
てI nAs基板2.4間に流れる。
Next, as the voltage applied to the ohmic voltages [8 and 10 on the top and bottom surfaces of the InAs substrates 2 and 4 is increased, as shown in FIG. 3(b), the triangles on the InAs substrate 2 side are The quantum level E2 formed in the potential well 12 coincides with the quantum level E1 formed in the triangular potential well 14 of the InAs substrate. Therefore, since a resonant tunnel effect occurs between both levels,
A large resonant channel current passes through the InAs oxide film 6 and flows between the InAs substrates 2 and 4.

このようにして得られる電流−電圧特性の測定結果を第
4図に示す。
The measurement results of the current-voltage characteristics obtained in this manner are shown in FIG.

第3図(a)に対応して、I nAs′#化rIA6を
挟む両側の三角ポテンシャル井戸12.14に形成され
た2次元電子の量子準位El、E2.・・・のいずれも
が一致しない場合には、A点に示されるように、電流が
減少している。これに対し、第3図(b)に対応して、
三角ポテンシャル井戸12゜14に形成された量子準位
El、B2.・・・のいずれかが一致している場合には
、B点に示されるように、電流が増加している。こうし
てInAs基板2.4間に流れる電流は、印加電圧に対
して線形ではなく、波打つ形となる。すなわち、非線形
特性を示す。なお、第4図のグラフは、温度4゜2Kに
おいて測定したものである。
Corresponding to FIG. 3(a), two-dimensional electron quantum levels El, E2, . ... do not match, the current is decreasing as shown at point A. On the other hand, corresponding to FIG. 3(b),
Quantum levels El, B2. formed in the triangular potential well 12°14. If any of them match, the current is increasing as shown at point B. In this way, the current flowing between the InAs substrates 2 and 4 is not linear with respect to the applied voltage, but has a wavy shape. That is, it exhibits nonlinear characteristics. The graph in FIG. 4 was measured at a temperature of 4.degree. 2K.

このように本実施例によれば、I nAs基板2゜4間
に厚さ100〜200人のInAs酸化膜6が挟まれて
いる5ISvJ造により、InAs基板2.4とI n
AsAs酸化膜6界面の伝導帯に三角ポテンシャル井戸
12.14が形成され、さらにこの三角ポテンシャル井
戸12.14に蓄積された2次元電子が量子化されて、
それぞれ量子準位E1.E2.・・・が形成される。
As described above, according to this embodiment, the InAs substrate 2.4 and the InAs oxide film 6 having a thickness of 100 to 200 layers are sandwiched between the InAs substrates 2.4 and 2.4 by the 5ISvJ structure.
A triangular potential well 12.14 is formed in the conduction band at the interface of the AsAs oxide film 6, and the two-dimensional electrons accumulated in this triangular potential well 12.14 are quantized,
Quantum level E1. E2. ... is formed.

そしてI nAs基板2,4間に所定の電圧を印加する
ことにより、In、As酸化膜6を挟む両側の三角ポテ
ンシャル井戸12.14に形成された2次元電子の量子
準位E1.E2.・・・を相対的に変化させ、両側の量
子準位El、E2.・・・のいずれもが一致しない場合
には小さなトンネル電流が流れ、量子準位E1.E2.
・・・のいずれかが一致する場合には大きな共I′!+
’、 l、ンネル電流が流れる非線形の@流−電圧特性
を実現することができる。
By applying a predetermined voltage between the InAs substrates 2 and 4, the two-dimensional electron quantum level E1. E2. . . , the quantum levels El, E2 . ... do not match, a small tunnel current flows and the quantum level E1. E2.
. . . if any of them match, there is a large co-I'! +
', l, it is possible to realize a nonlinear current-voltage characteristic where the channel current flows.

次に、第5図を用いて、第1図の非線形伝導量子デバイ
スの製造方法を説明する。
Next, a method for manufacturing the nonlinear conduction quantum device shown in FIG. 1 will be explained using FIG. 5.

ウェーハ状の2つのInAs基板2,4をそれぞれ酸化
雰囲気中で熱処理して、I nAs基板2゜11両面上
に、それぞれ厚さ50〜100人のInAsnAs酸化
膜6aを形成する(第5図(a)参照)。
Two wafer-shaped InAs substrates 2 and 4 are heat-treated in an oxidizing atmosphere to form InAsnAs oxide films 6a each having a thickness of 50 to 100 layers on both sides of the InAs substrates 2 and 11 (see FIG. 5). a)).

次いで、InAs基板2,4上のInAS酸化膜6a、
6bを接着させて熱処理を行ない、InAs基板2,4
を貼り合わせる。このとき、InAs基板2,4に挟ま
れたIIIAS酸化膜6a。
Next, the InAS oxide film 6a on the InAs substrates 2 and 4,
6b is bonded and heat treated to form InAs substrates 2 and 4.
Paste together. At this time, the IIIAS oxide film 6a is sandwiched between the InAs substrates 2 and 4.

6bは、厚さ100〜200人のInAs酸化膜6とな
る。こうしてSIS構造が形成される(第5図(b)参
照)。
6b is an InAs oxide film 6 having a thickness of 100 to 200 μm. In this way, the SIS structure is formed (see FIG. 5(b)).

次いで、InAsnAs酸化膜6て貼り合わされたIn
As基板2.4両外測のI nAs酸化膜6a、6bを
除去する。そして露出したI nAs基板2,4上面及
び底面上にそれぞれpbを蒸着した後、熱処理を施して
合金化し、オーミック電&8,10を形成する(第5図
(c)参照)。
Next, the InAsnAs oxide film 6 is bonded to the
The InAs oxide films 6a and 6b on both sides of the As substrate 2.4 are removed. After evaporating PB on the exposed top and bottom surfaces of the InAs substrates 2 and 4, heat treatment is performed to form an alloy to form ohmic conductors 8 and 10 (see FIG. 5(c)).

こうして非線形の電流−電圧特性を有する非線形伝導量
子デバイスを作製する。
In this way, a nonlinear conduction quantum device having nonlinear current-voltage characteristics is fabricated.

このように本実施例による製造方法によれば、超高真空
を必要としたり、結晶成長の効率が悪かったり、或いは
有毒なガスを必要としたりするMBE’?MOCVD等
の技術を用いることなく、いわゆるウェーハ貼り合わせ
技術を用いて、極めて容易に非線形伝導量子デバイスを
作製することができる。
As described above, according to the manufacturing method of this embodiment, MBE'? A nonlinear conduction quantum device can be manufactured extremely easily using a so-called wafer bonding technique without using a technique such as MOCVD.

0 なお、上記実施例において、InAs基板24上に形成
するオーミック電i8.ioとしてPbを用いているが
、代わりにNb(ニオブ)を用いてもよい。
0 In the above embodiment, the ohmic electrode i8.0 formed on the InAs substrate 24. Although Pb is used as io, Nb (niobium) may be used instead.

また、上記実施例においては、半導体基板としてInA
s基板を用いることにより、InAs酸化膜との界面に
量子化された2次元電子を形成し、この2次元電子の共
鳴トンネル効果を利用して非線形伝導特性を実現してい
るが、半導体基板を他の半導体材料に変えることにより
、2次元正孔の共鳴トンネル効果を利用した非線形伝導
特性を実現することもできる。
Further, in the above embodiment, InA is used as the semiconductor substrate.
By using an s-substrate, quantized two-dimensional electrons are formed at the interface with the InAs oxide film, and the resonant tunneling effect of these two-dimensional electrons is used to achieve nonlinear conduction characteristics. By changing to another semiconductor material, it is also possible to realize nonlinear conduction characteristics using the two-dimensional hole resonance tunneling effect.

[発明の効果] 以上のように本発明によれば、2つの半導体基板に薄膜
絶縁層が挟まれているSIS椙造により、2つの半導体
基板と薄膜絶縁層との界面に形成される三角ボデンシャ
ル井戸に蓄積され、量子化された2次元キャリアの共鳴
1−ンネル効果を利用して非線形の電流−電圧特性を実
現することができる。
[Effects of the Invention] As described above, according to the present invention, by using the SIS structure in which a thin film insulating layer is sandwiched between two semiconductor substrates, a triangular bodential is formed at the interface between the two semiconductor substrates and the thin film insulating layer. Nonlinear current-voltage characteristics can be realized by utilizing the resonant one-channel effect of quantized two-dimensional carriers accumulated in the well.

また本発明によれば、このような非線形伝導特性を有す
る半導体装置を、薄膜絶縁層が形成された2つの半導体
基板の貼り合わせ技術により、極めて容易に作製するこ
とができる。
Further, according to the present invention, a semiconductor device having such nonlinear conduction characteristics can be manufactured extremely easily by a technique of bonding two semiconductor substrates on which thin film insulating layers are formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による非線形伝導量子デバイ
スを示す断面図、 第2図は第1図の非線形伝導量子デバイスのエネルギー
バンド図、 第3図は第1図の非線形伝導量子デバイスの動作を説明
するためのエネルギーバンド図、第4図は第1図の非線
形伝導量子デバイスの特性を示すグラフ、 第5図は第1図の非線形伝導量子デバイスの製造方法を
示す工程図である。 図において、 2.4・・・・・・InAs基板、 6.6a、6b−−−・・−1n、As酸化膜、8.1
0・・・・・・オーミック電極、12.14・・・・・
・三角ポテンシャル井戸。
FIG. 1 is a cross-sectional view showing a nonlinear conduction quantum device according to an embodiment of the present invention, FIG. 2 is an energy band diagram of the nonlinear conduction quantum device of FIG. 1, and FIG. 3 is a cross-sectional view of the nonlinear conduction quantum device of FIG. FIG. 4 is an energy band diagram for explaining the operation, FIG. 4 is a graph showing the characteristics of the nonlinear conduction quantum device shown in FIG. 1, and FIG. 5 is a process chart showing a method for manufacturing the nonlinear conduction quantum device shown in FIG. 1. In the figure, 2.4...InAs substrate, 6.6a, 6b---...-1n, As oxide film, 8.1
0...Ohmic electrode, 12.14...
・Triangular potential well.

Claims (1)

【特許請求の範囲】 1、2つの半導体基板と、 前記2つの半導体基板に挟まれた薄膜絶縁層とを具備し
、 前記2つの半導体基板と前記薄膜絶縁層との界面に形成
される量子化された2次元キャリアの共鳴トンネル効果
により、非線形伝導特性を有することを特徴とする半導
体装置。 2、2つの半導体基板上にそれぞれ薄膜絶縁層を形成す
る工程と、 前記2つの半導体基板上の前記薄膜絶縁層を互いに貼り
合わせて半導体−絶縁体−半導体構造を形成する工程と を有することを特徴とする半導体装置の製造方法。
[Claims] 1. Comprising two semiconductor substrates and a thin film insulating layer sandwiched between the two semiconductor substrates, quantization formed at an interface between the two semiconductor substrates and the thin film insulating layer. A semiconductor device characterized by having nonlinear conduction characteristics due to the resonance tunneling effect of two-dimensional carriers. 2. Forming a thin film insulating layer on each of the two semiconductor substrates; and bonding the thin film insulating layers on the two semiconductor substrates to each other to form a semiconductor-insulator-semiconductor structure. A method for manufacturing a featured semiconductor device.
JP1286451A 1989-11-02 1989-11-02 Semiconductor device and its manufacture Pending JPH03148183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1286451A JPH03148183A (en) 1989-11-02 1989-11-02 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1286451A JPH03148183A (en) 1989-11-02 1989-11-02 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH03148183A true JPH03148183A (en) 1991-06-24

Family

ID=17704558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1286451A Pending JPH03148183A (en) 1989-11-02 1989-11-02 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH03148183A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0744777A1 (en) * 1995-05-25 1996-11-27 Matsushita Electric Industrial Co., Ltd. Nonlinear element and bistable memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0744777A1 (en) * 1995-05-25 1996-11-27 Matsushita Electric Industrial Co., Ltd. Nonlinear element and bistable memory device
US5665978A (en) * 1995-05-25 1997-09-09 Matsushita Electric Industrial Co., Ltd. Nonlinear element and bistable memory device

Similar Documents

Publication Publication Date Title
JP2542448B2 (en) Field effect transistor and method of manufacturing the same
US9640391B2 (en) Direct and pre-patterned synthesis of two-dimensional heterostructures
JPS6271271A (en) Electrode structure of silicon carbide semiconductor
JP3930561B2 (en) Ohmic contact and method for manufacturing a semiconductor device comprising such an ohmic contact
EP1807913A1 (en) Semiconductor device with tunable energy band gap
JP3547234B2 (en) Hall element and its manufacturing method
JPS6354777A (en) Resonance tunnel device
JPH03148183A (en) Semiconductor device and its manufacture
US4543442A (en) GaAs Schottky barrier photo-responsive device and method of fabrication
KR100738584B1 (en) Zinc oxide-based multilayer structural body and its producing method
JPS63160273A (en) High-speed semiconductor device
JPH0575101A (en) Semiconductor device having schottky barrier
JPS60258971A (en) Semiconductor device and manufacture thereof
JP3501019B2 (en) Cold cathode electron source
CN108878423B (en) Semiconductor and two-dimensional material combined power device and preparation method thereof
JP2666841B2 (en) Manufacturing method of avalanche type semiconductor light receiving element
JPS605572A (en) Manufacture of high speed semiconductor device
JPH1168087A (en) Resonance tunnel transistor and manufacture thereof
JPH03214774A (en) Semiconductor device
JP2993654B2 (en) Electrode structure
JPS62216370A (en) Semiconductor device
JPH02244673A (en) Electronic element using organic semiconductor and manufacture thereof
JP2676075B2 (en) Semiconductor layer formation method
JPH0256970A (en) Thin-film transistor and manufacture thereof
JPH0346271A (en) Mis type field effect transistor