JPH0346271A - Mis type field effect transistor - Google Patents
Mis type field effect transistorInfo
- Publication number
- JPH0346271A JPH0346271A JP18057789A JP18057789A JPH0346271A JP H0346271 A JPH0346271 A JP H0346271A JP 18057789 A JP18057789 A JP 18057789A JP 18057789 A JP18057789 A JP 18057789A JP H0346271 A JPH0346271 A JP H0346271A
- Authority
- JP
- Japan
- Prior art keywords
- zns
- insulating film
- znse
- gate insulating
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 8
- 239000010408 film Substances 0.000 claims abstract description 60
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 22
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 4
- 238000010030 laminating Methods 0.000 claims abstract 2
- 229910007709 ZnTe Inorganic materials 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- RVIXKDRPFPUUOO-UHFFFAOYSA-N dimethylselenide Chemical compound C[Se]C RVIXKDRPFPUUOO-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- -1 2...Si o Substances 0.000 description 1
- RWSOTUBLDIXVET-UHFFFAOYSA-N Dihydrogen sulfide Chemical compound S RWSOTUBLDIXVET-UHFFFAOYSA-N 0.000 description 1
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- AXAZMDOAUQTMOW-UHFFFAOYSA-N dimethylzinc Chemical compound C[Zn]C AXAZMDOAUQTMOW-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000037 hydrogen sulfide Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229960001730 nitrous oxide Drugs 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、Ｇ ａ Ａ ｓ基板を用いた金属／絶縁物／
半導体形電界効果トランジスタ（以下ＭＩＳＦＥＴと称
す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides metal/insulator/
The present invention relates to a semiconductor field effect transistor (hereinafter referred to as MISFET).
（従来の技術）
近年、Ｇ ａ Ａ ｓは、Ｓｉに比べ電子移動度が大き
く、超高速論理素子材料として注目されている。(Prior Art) In recent years, GaAs has higher electron mobility than Si and has attracted attention as a material for ultrahigh-speed logic elements.
現在、ＧａＡｓを用いた論理素子は、Ｇ ａ Ａ ｓ
Ｍ ＥＳＦＥＴが主流であるが、ＭＥＳＦＥＴに比べて
、消費電力が小さく、高集積化が可能なＧａＡｓＭＩＳ
ＦＥＴの実用化が強く期待されている。Currently, logic elements using GaAs are
Although MESFETs are the mainstream, GaAsMISs have lower power consumption and can be highly integrated than MESFETs.
There are strong expectations for the practical application of FETs.
一般に、Ｓｉ基板の表面に、絶縁膜を形成する方法は、
熱酸化により良質のＳｉＯ□膜を形成する。Generally, the method of forming an insulating film on the surface of a Si substrate is as follows:
A high quality SiO□ film is formed by thermal oxidation.
しかしながら、ＧａＡｓ基板の場合は、Ａｓは蒸気圧が
高く熱脱離を起こすために、良質の熱酸化膜を得ること
は不可能であった。従って、Ｇ ａ Ａ ｓ基板上に化
学的気相成長法（以下ＣＶＤと称す）や、スパッタ法等
により、低温で絶縁膜を形成していた。However, in the case of a GaAs substrate, it has been impossible to obtain a high-quality thermal oxide film because As has a high vapor pressure and causes thermal desorption. Therefore, an insulating film has been formed on a GaAs substrate at a low temperature by chemical vapor deposition (hereinafter referred to as CVD), sputtering, or the like.
従来のＭＩＳＦＥＴについて、第４図（ａ）および（ｂ
）により説明する。Regarding the conventional MISFET, Fig. 4(a) and (b)
).
第４図（ａ）における第１の従来例のＭＩＳＦＥＴは、
半絶縁性Ｇ ａ Ａ ｓ基板１の表面に、化学的気相成
長によるＳｉｏ、膜２のゲート絶縁膜を介して形成した
ゲート電極３を挟んで、不純物イオンが注入されたｎ０
拡散領域４上にソース・ドレイン電極５が形成されたも
のである。The first conventional MISFET in FIG. 4(a) is as follows:
Impurity ions are implanted onto the surface of a semi-insulating GaAs substrate 1 with a gate electrode 3 formed via a gate insulating film of SIO film 2 by chemical vapor deposition.
Source/drain electrodes 5 are formed on the diffusion region 4.
第４図（ｂ）における第２の従来例のＭＩＳＦＥＴが、
上記の第１の従来例と異なる点は、半絶縁性ＧａＡｓ基
板１の表面に、エピタキシャル成長によるＺ ｎ Ｓ
ｚ Ｓ ６ｌ−ｒ（０，０３＜ ｘ ＜０．０５）膜６
を介してゲート電極３が形成されている点で、その他は
変わりがない。The second conventional MISFET in FIG. 4(b) is
The difference from the above-mentioned first conventional example is that ZnS is grown epitaxially on the surface of the semi-insulating GaAs substrate 1.
z S 6l-r (0,03<x<0.05) membrane 6
There is no other difference except that the gate electrode 3 is formed through the gate electrode 3.
なお、第１の従来例では、５ｉｎ２膜２の替りに、Ｓｉ
、Ｎ４膜を、又第２の従来例ではＺｎ５ｚＳｅ１４膜６
の替りにＧａｙＡＱｌ−ｘＡ８（０＜ Ｘ ＜ １ ）
膜をそれぞれ形成した例もある。In addition, in the first conventional example, instead of the 5in2 film 2, Si
, N4 film, and in the second conventional example, Zn5zSe14 film 6
GayAQl-xA8 (0<X<1) instead of
There are also examples in which separate films were formed.
（発明が解決しようとする問題点）
しかしながら、第１の従来例では、Ｇ ａ Ａ ｓ基板
１とＳｉｎ、膜２又はＳｉ、Ｎ４膜の界面には、多量の
未結合が存在し、界面準位を形成していることが知られ
ている。このため、ＧａＡｓ基板１に対しＳｉｏ２膜２
の比抵抗が大きいため、ＧａＡｓ基板１とＳｉｎ、膜２
の間の界面準位密度が、１Ｘ１０”ａｎ−”ｅＶ−１程
度と大きくなり、ＦＥＴとして実用化するのは難しいと
いう問題があった。(Problems to be Solved by the Invention) However, in the first conventional example, there are a large amount of unbonded bonds at the interface between the GaAs substrate 1 and the Sin, film 2 or Si, N4 film, and the interface quasi It is known that they form a position. For this reason, the Sio2 film 2 is
Since the resistivity of GaAs substrate 1 and the film 2 are large,
There was a problem in that the interface state density between the two was as large as about 1×10"an-"eV-1, making it difficult to put it into practical use as an FET.
また、第２の従来例では、Ｚｎ５ｚＳｅ１−ｘ膜６は。Furthermore, in the second conventional example, the Zn5zSe1-x film 6 is as follows.
ＧａＡｓ基板１に格子整合し、且つ、禁制帯幅が、Ｇａ
Ａｓより大きく、さらに、上記のＳｉｏ、膜２に比べて
界面準位密度が小さく、且つ、比抵抗も小さいが、伝導
帯のバンド不連続量が。It is lattice matched to the GaAs substrate 1 and has a forbidden band width.
It is larger than As, and has a lower interface state density and resistivity than the above-mentioned Sio film 2, but the amount of band discontinuity in the conduction band.
ｚｎ Ｓ ａ 、０３ Ｓ ｅｏ 、７ ／ Ｑ６Ａｇ
で０．０２ｅＶ、Ｇ ａ Ａ Ｑ Ａ ｓ／ＧａＡｓで
０．１７ｅＶと小さく、界面にキャリアを有効に閉じ込
めることが難しいという問題があった。zn S a , 03 S eo , 7 / Q6Ag
It is as small as 0.02 eV for GaA Q A s/GaAs and 0.17 eV for GaA Q A s/GaAs, which poses a problem that it is difficult to effectively confine carriers at the interface.
本発明は上記の問題を解決するもので、ＧａＡｓ基板を
用いた高性能のＭＩＳＦＥＴを提供するものである。The present invention solves the above problems and provides a high-performance MISFET using a GaAs substrate.
（ｍ１題を解決するための手段）
上記の課題を解決するため、本発明はＧａＡｓ基板上に
、異なる２種類以上の■−■族化合物半導体からなる超
格子を堆積し、ゲート絶縁膜とするものである。(Means for Solving Problem m1) In order to solve the above problems, the present invention deposits a superlattice made of two or more different types of ■-■ group compound semiconductors on a GaAs substrate, and uses it as a gate insulating film. It is something.
また、Ｇ ａ Ａ ｓ基板とＳｉｎ、膜又はＳｉ、Ｎｌ
膜等の絶縁膜との間に異なる２種類以上のＩＩ −ＶＩ
族化合物半導体からなる超格子を挿入するものである。In addition, GaAs substrate and Sin, film or Si, Nl
Two or more different types of II-VI between insulating films such as films
This method involves inserting a superlattice made of group compound semiconductors.
（作 用）
Ｇ ａ Ａ ｓ基板上に、例えば、ＺｎＳｅ、ＺｎＳ薄
膜を交互に積層したＺｎＳｅ／ＺｎＳ歪超格子でゲート
絶縁膜を形成すると、ＧａＡｓ、ＺｎＳｅおよびＺｎＳ
結晶は、それぞれ格子定数が異なるが、ゲート絶縁膜を
形成する各層厚は極めて薄いため、格子が歪み、格子不
整合による転位が発生せず、ＧａＡｓ／絶縁膜界面の未
結合手が極めて少なくなる。(Function) When a gate insulating film is formed on a GaAs substrate using, for example, a ZnSe/ZnS strained superlattice in which ZnSe and ZnS thin films are alternately laminated, GaAs, ZnSe and ZnS
Each crystal has a different lattice constant, but since the thickness of each layer forming the gate insulating film is extremely thin, lattice distortion and dislocation due to lattice mismatch do not occur, and dangling bonds at the GaAs/insulating film interface are extremely reduced. .
従って、Ｓｉｎ、膜、又は５１３Ｎ４膜に比べて、界面
準位密度の著しく小さな絶縁膜の形成が可能となる。Therefore, it is possible to form an insulating film with a significantly lower density of interface states than a Sin film or a 513N4 film.
第３図（ａ）および（ｂ）は、Ｇ ａ Ａ ｓ基板上に
ＺｎＳｅ／ＺｎＳ歪超格子およびＧ ａ Ａ ｓ基板に
格子整合したＺｎＳ、、、、Ｓｓ、、、、をそれぞれ形
成した時のエネルギーバンド図である。ＺｎＳｅ／Ｚｎ
Ｓ歪超格子を絶縁膜として用いた場合、ＺｎＳＳｅ膜を
用いた場合に比べ、ＧａＡｓ／絶縁膜界面での伝導帯の
エネルギー不連続量が約０．１５ｅＶ大きい、歪超格子
は、ＧａＡｓ界面に蓄積された電子にとって大きな障壁
となり、ゲート電極への漏れ電流を著しく軽減する。な
お、Ｚｎ５ａ／ＺｎＳ歪超格子で説明したが、ＺｎＴｅ
／ＺｎＳ、Ｚｎ５Ｓｓ／ＺｎＳ、ＺｎＴｅＳ／ＺｎＳ、
ＺｎＳｅＴｅ／ＺｎＳを用いても、同様の効果が得られ
る。Figures 3(a) and (b) show the results when a ZnSe/ZnS strained superlattice is formed on a GaAs substrate and ZnS, . . . , Ss, . FIG. ZnSe/Zn
When an S strained superlattice is used as an insulating film, the amount of energy discontinuity in the conduction band at the GaAs/insulating film interface is approximately 0.15 eV larger than when a ZnSSe film is used. It acts as a large barrier to the accumulated electrons and significantly reduces leakage current to the gate electrode. Although the explanation was given using Zn5a/ZnS strained superlattice, ZnTe
/ZnS, Zn5Ss/ZnS, ZnTeS/ZnS,
Similar effects can be obtained by using ZnSeTe/ZnS.
Ｇ ａ Ａ ｓ基板とＳｉｏ、膜あるいはＳｉ、Ｎ、膜
等のゲート絶縁膜との界面に、例えば、ＺｎＳｅとＺｎ
Ｓからなる歪超格子を挿入すると、界面に歪エネルギー
が貯えられ、転位の発生を抑制し、界面の未結合手の数
を軽減することができる。これより、従来のＳｉｎ、膜
又はＳｉ、Ｎ４膜単層のＭＩＳＦＥＴに比べて相互コン
ダクタンス等の特性が向上する。For example, ZnSe and Zn are added at the interface between the GaAs substrate and the gate insulating film such as Sio, film or Si, N, film.
When a strained superlattice made of S is inserted, strain energy is stored at the interface, suppressing the generation of dislocations, and reducing the number of dangling bonds at the interface. As a result, characteristics such as mutual conductance are improved compared to conventional single-layer MISFETs of Sin, film, or Si, N4 film.
なお、ＺｎＳｅ／ＺｎＳ歪超格子の替わりにＺｎＴｅ／
ＺｎＳ、ＺｎＳＳｅ／ＺｎＳ 、ＺｎＴｅＳ／ＺｎＳ。In addition, instead of ZnSe/ZnS strained superlattice, ZnTe/
ZnS, ZnSSe/ZnS, ZnTeS/ZnS.
ＺｎＳｅＴｅ／ＺｎＳを用いても、同様の効果が得られ
る。Similar effects can be obtained by using ZnSeTe/ZnS.
（実施例）
本発明の実施例２例について、第１図および第２図によ
り説明する。(Example) Two examples of the present invention will be described with reference to FIGS. 1 and 2.
第１図は、ＺｎＳｅ／ＺｎＳ歪超格子７をゲート絶縁膜
として用いた第１の実施例の要部拡大断面図である。な
お、第４図に示した従来例と同じ構成部には、同一符号
を付して説明を進める。FIG. 1 is an enlarged sectional view of a main part of a first embodiment in which a ZnSe/ZnS strained superlattice 7 is used as a gate insulating film. Note that the same components as in the conventional example shown in FIG. 4 are given the same reference numerals and the explanation will be continued.
Ｓｉイオン注入を用いてソース・ドレイン領域となるｎ
０拡散領域４を形成した半絶縁性Ｇ ａ Ａ ｓ基板上
の上に、有機金属気相成長法により。n to become source/drain regions using Si ion implantation.
0 diffusion region 4 was formed on a semi-insulating GaAs substrate by metal organic vapor phase epitaxy.
ＺｎＳｅ／ＺｎＳ歪超格子７を堆積した。原料ガスには
、ジメチル亜鉛、ジメチルセレン、硫化水素を用い、成
長温度を５５０℃とした。A ZnSe/ZnS strained superlattice 7 was deposited. Dimethylzinc, dimethylselenium, and hydrogen sulfide were used as raw material gases, and the growth temperature was set at 550°C.
歪超格子７は、膜厚５０ＡのＺｎＳｅ７ａと、膜厚５０
入のＺｎＳ ７ｂをそれぞれ１０層交互に積層して全面
に形成した後、反応性イオンエツチング法によりゲート
電極３の部分以外の歪超格子７を除去した。The strained superlattice 7 is made of ZnSe7a with a film thickness of 50A and a film with a film thickness of 50A.
After ten layers of ZnS 7b were alternately stacked on the entire surface, the strained superlattice 7 except for the gate electrode 3 was removed by reactive ion etching.
ソース・ドレイン電極５はＡ ｕ ／ Ｑ ６を真空蒸
着した後、４００℃１分間の熱処理を施しオーム性電極
とし、ゲート電極３は、Ａｕの真空蒸着により形成した
。The source/drain electrodes 5 were formed by vacuum evaporating Au/Q 6 and then subjected to heat treatment at 400° C. for 1 minute to form ohmic electrodes, and the gate electrode 3 was formed by vacuum evaporating Au.
このようにして得られたＧａＡｓＭ Ｉ Ｓ Ｆ Ｅ
Ｔのゲート長は１μｍ、ゲート幅は１０μｍである。試
作品について、ドレイン電流−ドレイン電圧特性を測定
した結果、室温で相互コンダクタンス５００＋ｓ Ｓｉ
請を得た。GaAsM I S F E thus obtained
The gate length of T is 1 μm and the gate width is 10 μm. As a result of measuring the drain current-drain voltage characteristics of the prototype, it was found that the transconductance was 500+s Si at room temperature.
I got the request.
また、キャリア密度２ Ｘ １０” （！ｍ−”を半絶
縁性ＧａＡｓ基板上に、同様の手法でＺｎＳｅ／ＺｎＳ
歪超格子を堆積し、Ａｕ電極を蒸着してＭＩＳダイオー
ドを試作し、その容量−電圧特性から求めた界面準位密
度の最小値は、Ｉ ＸＩＯｌｌａｍ−”ｅＶ−１であっ
た。In addition, ZnSe/ZnS was deposited using the same method on a semi-insulating GaAs substrate with a carrier density of 2 × 10” (!m-”).
A MIS diode was prototyped by depositing a strained superlattice and evaporating an Au electrode, and the minimum value of the interface state density determined from its capacitance-voltage characteristics was IXIOllam-''eV-1.
本実施例のように、ＺｎＳｅ／ＺｎＳ歪超格子７をゲー
ト絶縁膜に用いると、良好な界面特性が得られ、ＭＩＳ
ＦＥＴの特性が向上する。When the ZnSe/ZnS strained superlattice 7 is used as the gate insulating film as in this example, good interface characteristics can be obtained and MIS
The characteristics of FET are improved.
また、ゲート電極３への漏れ電流密度は、５ｖ印加時に
、１ ｐ Ａ ／ ｄ以下で、従って、ＺｎＳｅ／Ｚｎ
Ｓ歪超格子７の比抵抗がｒｏ１！Ω・０以上となりＺｎ
ＳＳｅ膜やＡ Ｑ Ｇ ａ Ａ ｓ膜に比べ、絶縁性に
優れている。Furthermore, the leakage current density to the gate electrode 3 is less than 1 pA/d when 5V is applied, and therefore, the ZnSe/Zn
The specific resistance of the S strain superlattice 7 is ro1! Ω・0 or more and Zn
It has superior insulation properties compared to SSe films and AQGaAs films.
なお、ＺｎＳｅ／ＺｎＳ歪超格子７の替わりにＺｎＴａ
／ＺｎＳ、ＺｎＳＳｅ／ＺｎＳ、ＺｎＴａ５／ＺｎＳ、
ＺｎＳｅＴｅ／ＺｎＳ歪超格子を用いた場合も同様の結
果が得られた。Note that ZnTa instead of the ZnSe/ZnS strained superlattice 7
/ZnS, ZnSSe/ZnS, ZnTa5/ZnS,
Similar results were obtained using a ZnSeTe/ZnS strained superlattice.
第２図は、ＧａＡｓ基板ｌとＳｊ、０２膜２との間にＺ
ｎＳｅ／ＺｎＳ歪超格子７を挿入した第２の実施例の要
部拡大断面図である。FIG. 2 shows a Z
FIG. 7 is an enlarged sectional view of a main part of a second embodiment in which an nSe/ZnS strained superlattice 7 is inserted.
第２の実施例が、第１図に示した第１の実施例と異なる
点は、歪超格子７が、５０人のＺｎＳｅと５０入のＺｎ
Ｓをそれぞれ２層交互に積層して形成した点と、続いて
原料ガスとしてモノシランおよび酸化二窒素を用いたプ
ラズマＣＶＤにより８００λのＳｉｎ、膜２を堆積した
点である。その点は変わらないので、同じ構成部には同
一符号を付して、その説明を省略する。The second embodiment is different from the first embodiment shown in FIG.
Two layers of S were formed by alternately stacking each layer, and then a film 2 of 800λ of Sin was deposited by plasma CVD using monosilane and dinitrogen oxide as raw material gases. Since this point remains the same, the same components are given the same reference numerals and their explanations will be omitted.
試作したＧａＡｓＭ Ｉ Ｓ Ｆ Ｅ Ｔは、ゲート長
がｌμＬゲート幅がｌＯμ冒で、ドレイン電流−ドレイ
ン電圧特性を測定した結果、室温で相互コンダクタンス
５００ｍ Ｓ ／ ｍを得た。また、ゲート電極への漏
れ電流密度を測定した結果、ｌｎＡ／ａＪ以下であった
。The prototype GaAs MISFET had a gate length of 1 μL and a gate width of 10 μL, and as a result of measuring the drain current-drain voltage characteristics, a mutual conductance of 500 mS/m was obtained at room temperature. Further, as a result of measuring the leakage current density to the gate electrode, it was less than lnA/aJ.
本実施例のように、ＧａＡｓ基板１とＳｉｏ、膜２の間
に、ＺｎＳｅ／ＺｎＳ歪超格子７を挿入することによっ
て、ＭＩＳＦＥＴの特性が大幅に向上した。By inserting the ZnSe/ZnS strained superlattice 7 between the GaAs substrate 1 and the Sio film 2 as in this example, the characteristics of the MISFET were significantly improved.
なお、ＺｎＳｅ／ＺｎＳ歪超格子７の替わりにＺｎＴｅ
／ＺｎＳ、Ｚｎ５Ｓｓ／ＺｎＳ、ＺｎＴｅＳ／ＺｎＳ、
ＺｎＳｅＴｅ／ＺｎＳを用いても同様の結果が得られた
。Note that ZnTe is used instead of the ZnSe/ZnS strained superlattice 7.
/ZnS, Zn5Ss/ZnS, ZnTeS/ZnS,
Similar results were obtained using ZnSeTe/ZnS.
（発明の効果）
以上説明したように、本発明によれば、室温で相互フン
ダクタンスが５００＋ａ Ｓ ／ ｒｍ程度の高性能な
ＧａＡｓＭＩＳＦＥＴトランジスタが得られる。(Effects of the Invention) As described above, according to the present invention, a high-performance GaAs MISFET transistor having a mutual fundance of about 500+a S/rm at room temperature can be obtained.
第１図は本発明によるＺｎＳｅ／ＺｎＳ歪超格子をゲー
ト絶縁膜としたＧａＡｓＭ Ｉ Ｓ Ｆ Ｅ Ｔの要部
拡大断面図、第２図は本発明による、界面にＺｎＳｅ／
ＺｎＳ歪超格子を挿入したＧａＡｓＭＩＳＦＥＴの要部
拡大断面図、第３図（ａ）および（ｂ）はそれぞれＺｎ
Ｓｅ／ＺｎＳ歪超格子／ＧａＡｓおよびＺ ｎ Ｓ １
） 、 ６３ Ｓ ６６ 、 ｇ ７ ／ Ｇ ａ Ａ
Ｓのエネルギーバンド図、第４図（ａ）および（ｂ）
はそれぞれＳｉｎ、膜およびＺｎＳＳｅ膜をゲート絶縁
膜に用いた従来のＧ ａ Ａ ５Ｍｌ５ＦＥＴの要部拡
大断面図である。
工・・・半絶縁性Ｇ ａ Ａ ｓ基板、 ２・・・Ｓｉ
ｏ、膜、３・・・ゲート電極、 ４・・・ｎ°拡散領域
。
５・・・ソース・ドレイン電極、 ６・・・ＺｎＳ。
Ｓ ｅｌ−ｘ膜、 ７＝−ＺｎＳｅ／ＺｎＳ歪超格子
、７ａ−−−ＺｎＳｅ、 ７ｂ−ＺｎＳ。FIG. 1 is an enlarged cross-sectional view of the main part of a GaAsMISFET using a ZnSe/ZnS strained superlattice as a gate insulating film according to the present invention, and FIG.
Figures 3(a) and 3(b) are enlarged cross-sectional views of the main parts of a GaAs MISFET with a ZnS strained superlattice inserted, respectively.
Se/ZnS strained superlattice/GaAs and Z n S 1
), 63 S 66, g 7 / G a A
Energy band diagram of S, Figure 4 (a) and (b)
These are enlarged cross-sectional views of essential parts of a conventional GaA 5Ml5FET using a Sin film, a ZnSSe film, and a ZnSSe film as the gate insulating film, respectively. Engineering...Semi-insulating GaAs substrate, 2...Si
o, film, 3... gate electrode, 4... n° diffusion region. 5... Source/drain electrode, 6... ZnS. Sel-x film, 7=-ZnSe/ZnS strained superlattice, 7a---ZnSe, 7b-ZnS.
Claims (4)
電極を形成したＭＩＳ形電界効果トランジスタにおいて
、上記のゲート絶縁膜が２種類以上の異種II−VI族化合
物半導体薄膜を交互に積層して形成されたことを特徴と
するＭＩＳ形電界効果トランジスタ。(1) In a MIS field effect transistor in which a gate electrode is formed on a GaAs substrate via a gate insulating film, the gate insulating film is formed by alternately laminating two or more different types of II-VI compound semiconductor thin films. An MIS type field effect transistor characterized by being formed.
Ｓ、ＺｎＴｅ／ＺｎＳ、ＺｎＳＳｅ／ＺｎＳ、ＺｎＴｅ
Ｓ／ＺｎＳ、ＺｎＳｅＴｅ／ＺｎＳであることを特徴と
する請求項（１）記載のＭＩＳ形電界効果トランジスタ
。(2) The above II-VI group compound semiconductor is ZnSe/Zn
S, ZnTe/ZnS, ZnSSe/ZnS, ZnTe
The MIS type field effect transistor according to claim 1, characterized in that it is S/ZnS or ZnSeTe/ZnS.
種類以上の異種II−VI族化合物半導体膜を交互に積層し
て挿入したことを特徴とするＭＩＳ形電界効果トランジ
スタ。(3) Between the GaAs substrate and the Si-based gate insulating film,
A MIS type field effect transistor characterized in that more than one type of different type II-VI group compound semiconductor films are alternately stacked and inserted.
Ｓ、ＺｎＴｅ／ＺｎＳ、ＺｎＳＳｅ／ＺｎＳ、ＺｎＴｅ
Ｓ／ＺｎＳ、ＺｎＳｅＴｅ／ＺｎＳであることを特徴と
する請求項（３）記載のＭＩＳ形電界効果トランジスタ
。(4) The above II-VI group compound semiconductor is ZnSe/Zn
S, ZnTe/ZnS, ZnSSe/ZnS, ZnTe
The MIS type field effect transistor according to claim 3, characterized in that it is S/ZnS or ZnSeTe/ZnS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18057789A JPH0346271A (en) | 1989-07-14 | 1989-07-14 | Mis type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18057789A JPH0346271A (en) | 1989-07-14 | 1989-07-14 | Mis type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0346271A true JPH0346271A (en) | 1991-02-27 |
Family
ID=16085704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18057789A Pending JPH0346271A (en) | 1989-07-14 | 1989-07-14 | Mis type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0346271A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009045233A (en) * | 2007-08-20 | 2009-03-05 | Physical Air Corporation Co Ltd | Training method and apparatus |
| US20180006131A1 (en) * | 2016-06-30 | 2018-01-04 | International Business Machines Corporation | Lattice matched and strain compensated single-crystal compound for gate dielectric |
-
1989
- 1989-07-14 JP JP18057789A patent/JPH0346271A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009045233A (en) * | 2007-08-20 | 2009-03-05 | Physical Air Corporation Co Ltd | Training method and apparatus |
| US20180006131A1 (en) * | 2016-06-30 | 2018-01-04 | International Business Machines Corporation | Lattice matched and strain compensated single-crystal compound for gate dielectric |
| US9876090B1 (en) * | 2016-06-30 | 2018-01-23 | International Business Machines Corporation | Lattice matched and strain compensated single-crystal compound for gate dielectric |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2542448B2 (en) | Field effect transistor and method of manufacturing the same | |
| JP3364119B2 (en) | Hydrogen-terminated diamond MISFET and method for manufacturing the same | |
| JPH0766971B2 (en) | Silicon carbide semiconductor device | |
| JPH04312982A (en) | Semiconductor polycrystalline diamond electronic device and manufacture thereof | |
| JP2000223697A (en) | Heterojunction field effect transistor | |
| US7187045B2 (en) | Junction field effect metal oxide compound semiconductor integrated transistor devices | |
| JP3308755B2 (en) | Method for manufacturing hydrogen-terminated diamond semiconductor device with element isolation | |
| JPS62271475A (en) | Semiconductor device | |
| CN107359127B (en) | Fe-doped spin field effect transistor of sapphire substrate and manufacturing method thereof | |
| JPH0346271A (en) | Mis type field effect transistor | |
| CN109904227B (en) | Diamond-based field effect transistor with low-work-function conductive grid and preparation method thereof | |
| US20120018704A1 (en) | Uniaxial tensile strain in semiconductor devices | |
| JPH0719888B2 (en) | Field effect transistor and method of manufacturing the same | |
| CN107527949B (en) | Heterojunction spin field effect transistor based on Cr-doped 4H-SiC substrate and preparation method thereof | |
| CN107425059B (en) | Cr-doped heterojunction spin field effect transistor and preparation method thereof | |
| JPH01119065A (en) | Iii-v compound semiconductor field-effect transistor | |
| JPS6292327A (en) | Semiconductor device and manufacture thereof | |
| CN112103190B (en) | Structure of semiconductor device and preparation method thereof | |
| US20240079477A1 (en) | Vertical gallium oxide transistor and preparation method thereof | |
| CN107359122B (en) | Preparation method of Mn-doped heterojunction spin field effect transistor | |
| JPS59165460A (en) | Semiconductor device and manufacture thereof | |
| JPH02196436A (en) | Semiconductor device | |
| JP2633009B2 (en) | Compound semiconductor field effect transistor and method of manufacturing the same | |
| Liu et al. | Diamond Metal-Oxide-Semiconductor Field-Effect Transistors on a Large-Area Wafer | |
| JPS63161625A (en) | Manufacture of field-effect transistor |