JPS61276377A - Field-effect-type compound semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the difference between threshold voltages at room temperature and a low temperature, by providing a GaAs/n-AlGaAs hetero-junction in which the n-AlxGa1-xAs layer serving as a carrier supply layer has a specified molar ratio of Al. CONSTITUTION:A GaAs substrate 1 is provided thereon with an undoped GaAs layer 2, an undoped Al0.2Ga0.8As layer 3, an n-type Al0.2Ga0.8As layer 4, an undoped GaAs layer 5, an n-type Al0.2Ga0.8As layer 6 and an n-type GaAs layer 7 in that order. Source and drain electrodes 8 and 9 are formed on the surface of this substrate to be contacted with the layer 5. Subsequentially, the layer 7 located between the electrodes 8 and 9 is partially removed and a gate electrode 10 is formed in said removed part. According to such construction, hetero- junctions are formed between the layers 6 and 5 and between the layers 5 and 4, respectively. When the layer 5 is sufficiently thin, the two-dimentional electron gas produced by the layer 6 and 4 practically acts as a single channel, and thereby the sheet carrier density can be prevented from being decreased. Accordingly, the difference between threshold voltages at room temperature and a low temperature can be decreased.

Description

Detailed Description of the Invention [Summary] In a GaAs/n-AJGaAs heterojunction FET, the molar ratio of n-AllGaAs serving as a carrier supply layer is set to 0.1 or more and 0.22 or less, and a double heterojunction is formed in the channel portion. By using this structure, fluctuations in threshold voltage between room temperature and low temperature can be made small, and a decrease in sheet carrier concentration can be prevented.

[Industrial application field]

The present invention relates to a field effect semiconductor device using a heterojunction in a channel, and particularly to a device structure that can suppress threshold fluctuations at room temperature and low temperature.

[Conventional technology]

Conventionally, in a field-effect semiconductor device (FIT) using a heterojunction as a channel part, a high-mobility two-dimensional structure that occurs at the interface on the undoped GaAs layer side of the heterojunction between an undoped GaAs layer and an n-AlGaAs layer is used as the normal channel. It uses electronic gas to achieve high-speed operation.

FIG. 5 shows a cross section of the element. Semi-insulating GaA
On the s-substrate 51, a buffer layer of GaAa 52 r 2
An AND single layer on which a dimensional electron gas (2DEG) layer 57 is formed is epitaxially formed, and a source and drain electrode 59 and a gate electrode ω are provided.

In normal cases, the molar ratio of Aj in n-AjGmAs 54 is almost always X=0.3. This is because the sheet carrier concentration n can be increased by making the band discontinuity in the heterojunction as large as possible.
/Aj: 0.3 was selected because the molar ratio X of Aj was attempted to be increased within a range that allowed the mismatch of the GaAs lattice.

FIG. 4 shows an energy band diagram of a conventional GaAs layer n-AJGaAa heterostructure, and when x: 0.3, mismatch in the lattice of the GaAs layer n-AjGaAs hardly becomes a problem. but,! >0.
When the temperature reaches 3 K, interface states are generated as indicated by E in FIG. 4, and the device characteristics deteriorate.

[Problem that the invention seeks to solve]

As mentioned above, the conventional element with x=0.3 is capable of sufficiently high-speed operation, but n-Al6. HG a
6, yA s has a deep impurity level called a DX center, so in devices fabricated using it,
There is a problem in that the threshold voltage vth at room temperature and vth at low temperature (77K) are significantly different. For example, 3
00 K "t' f) Vth = -0,8V is 7
7, the voltage Vth changes to -0.3V.

On the other hand, n-Ajz Gal-1 with X≦0.22
It is known that in devices using Aa, fluctuations in %vth between room temperature and low temperature can be made sufficiently small. However, as shown in the table, this structure has the disadvantage that the sheet carrier concentration n in the channel decreases and the FET ratio deteriorates.

[Means for solving problems]

The present invention provides an FET using a GaAs/n-AJGaAs heterojunction for the channel, in which the n
-hlxGa, -xAs molar ratio X of Al is 0.1≦x
≦0.22, and the channel portion has a double heterostructure.

[Effect]

Taking the example of FIG. 1 and explaining it, undoped GaA
n-Al64 caOJ As on the upper and lower sides of the s layer 5
Layers 6 and 4 are provided, and a heterojunction is formed between each glabella, resulting in a so-called double heterostructure.

Besides, upper and lower n-A764 Ga@4AI layers 6
．． 4 each function as an electron supply layer, and when the undoped GaAs layer 5 is sufficiently thin, the two-dimensional electron gas generated from the two electron supply layers does not form two channels, but effectively becomes one channel.
The n of the channel is approximately twice that of the single heterostructure.

On the other hand, as shown in Figure 3, which shows the relationship between the AJ molar ratio of AjGaAs and the ionization energy of the dopant, x = 0.2
If it is less than 2, the ionization energy is sufficiently small that no deep level is formed.

From the above, according to the present invention, Aj of the electron supply layer
Molar ratio of Al in X Ga 1-X As xt-0,22
By doing the following, the ionization energy can be made sufficiently small, and fluctuations in Vth can be prevented even at low temperatures.

On the other hand, as the molar ratio X of AAI becomes smaller, the GaAs layer n
-AJf.

As the discontinuity of the energy band of Gal-1AsI becomes smaller, the sheet carrier concentration in the channel n,
The disadvantage of a decrease in n can be improved by using a tuple heterostructure, and a high-speed semiconductor device with stable characteristics at low temperatures and a large n that can flow a large current can be obtained. It will be done.

Note that in the present invention, as described above, undoped GaAs
It is desirable to make the thickness of the 5th layer sufficiently thin so that the two-dimensional electron gas generated from the two electron supply layers forms one channel, and the film thickness of about %100A is the most desirable.
A film thickness in the range of X to 200X is practically applicable. 60X
When a very thin undoped GaAs layer is used, carriers flowing through the layer are scattered by Alx Ga 1- z@AI above and below, and their mobility decreases.

Put it away. On the other hand, if an undoped GaAs layer of 200.times.

〔Example〕

FIG. 1 shows a cross section of an element according to an embodiment of the present invention, and FIG. 2 shows its energy band diagram.

As shown in FIG. 1, the following layers are formed on a semi-insulating GaAs+ substrate 1 by epitaxial growth.

Film thickness Carrier concentration 2: Undoped GaAs 1000 A3:
Undoped Ajl, lGm6. @As 200 or 4:
n-AJ64Ga0. gAIB 200X
1.9X10"am-"5: Undoped GaAs
1GOA6: n-A noro 4Ga@4Al
250~400A 1-9X10"am-"?
: n-GaAs 700X
1.9X10"am-" where 7 is ohmic
This is a layer for making good contact.

Next, source and drain electrodes 8 and 9 (AuGe/
Au, etc.) is formed by a lift-off method or the like, and brought into contact with the undoped GaAs layer 5 in which a two-dimensional atomic gas is formed by an alloy method in which heating or the like is applied.

Next, the n-GaAs between the source and gate electrodes 8 and 9 is
The layer 7 is partially etched away, and a gate electrode 1G (Aj, etc.) made of a Schmittki junction metal is formed in that part.

When the undoped GaAs channel layer of 5 is 100X, the A thickness of the two electron supply layers is 1 Gmg4 As.
It has been found that the two-dimensional electron gas generated from 4 + 6 does not act as two channels, but effectively acts as one channel, and this state is shown in the energy band diagram of FIG.

60n-Aj64 Gmg, @As is the upper electron supply layer and also forms a Schottky barrier with the gate metal (A).
th can be determined. For example, at about 250X it is in enhancement mode and at 400X it is in depression mode.

According to this embodiment, for example, the threshold value (Vth) is 2 at 300.
> In the case of E-o, svo, the variation in Vth can be reduced to about -0.7V at a low temperature of 77 compared to the conventional method, and the sheet carrier concentration n can also be approximately doubled by double heterojunction. can.

〔Effect of the invention〕

As is clear from the above, according to the present invention, contrary to the development trend of conventional HEMTs, the channel carrier sheet concentration n, as well as the threshold voltage when cooled to a low temperature (Vt
Focusing on prevention of fluctuations in h), the molar ratio of Aj in the carrier supply layer is made small, so that changes in -Vth can be made small, and on the other hand, it is possible to prevent a decrease in n8 of the channel.

In addition, the present invention makes it possible to provide a stable, high-speed, and high-performance semiconductor device.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the main part of the embodiment of the present invention, Fig. 2 is an energy band diagram of the embodiment, Fig. 3 is a diagram showing the relationship between the X value and ionization energy, and Fig. 4 is a diagram of the conventional example. It is an energy band diagram. Fuku S1zbai L rice example town + i1m pickles too. 1...GaA@Substrate 2...Undoped GaAs 3...Undoped AJ(1,gGa6.@As4"
"n-Aj1)4G&.4AII5...Undoped GaAs6H=n-Aj(14Ga(1,8As7...
n-GaAs 8.9...Source, drain electrode 10...Gate electrode Patent application/Otsuya Fujitsu Limited Representative Patent Attorney Hisashi Tamamushi (1 person) Cross-sectional view of essential parts of an embodiment of the present invention Fig. 1 Energy band diagram of the embodiment of n-AIo2Ga6sAs Fig. 2

Claims (1)

[Claims] On the substrate, n-type Al_xGa_1_-_xAs (0.1
≦x≦0.22), a GaAs layer as a channel layer, and an n-type Al_yGa_1_-_y
Each semiconductor layer of the second carrier supply layer made of As (0.1≦y≦0.22) is formed to be crystallographically compatible, and a pair of electrodes are connected to the GaAs layer of the channel layer; A field effect compound semiconductor device comprising: a gate electrode disposed on the second carrier supply layer side between the pair of electrodes.