JPS61276367A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high withstanding bi-polar IC which has a reduced hFE and can prevent VCE(sat) from increasing, by forming an N epitaxial layer with an SiCl4 source on a P-type Si substrate having an N layer and a P layer buried, by burying a P layer, and by overlapping an N epitaxial layer with a small specific resistance thereon with an SiH4 source. CONSTITUTION:On a P<-> Si substrate 1, an N<+> layer 2 is buried by diffusing As, then a P layer 3 is buried by diffusing BCl3 and an N<-> epitaxial layer 4 is overlapped with a reducing reaction of SiCl4 at about 1,170 deg.C. By diffusing BCl3 from the surface, a P layer 5 is buried over the layer 3, and by thermal decomposition of SiH4 at about 1,050 deg.C, an N<-> epitaxial layer 6b is overlapped, with self-addition of B being less than the layer 4. In this way, an inverted layer or a high resistance layer can be prevented from occurring at the interface between the epitaxial layers, and if the layer is increased in concentration, the self-addition can be perfectly eliminated. Accordingly, if an NPN transistor is made, with a P layer 10 being formed, which separates the epitaxial layers 4, 6b, an extremely high diffusion yield can be realized without reducing the hFE and increasing the VCE(sat).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a high voltage bipolar integrated circuit having at least a two-layer epitaxial layer structure.

[Conventional technology]

Conventionally, in bipolar integrated circuits (hereinafter referred to as ICs), the following measures have been taken to achieve high breakdown voltage of vertical transistors, such as NPN transistors, in which a base diffusion layer and an emitter diffusion layer are sequentially formed in an epitaxial layer. is applied.

(1) The depth of the diffusion layer (below c, referred to as xj) is increased.

(2) Increase the epitaxial layer resistivity (hereinafter referred to as 5epi).

(3) Epitaxial layer thickness (hereinafter referred to as tepi)
thicken.

Regarding (1), for example, the depth xj of the pace diffusion layer is increased to alleviate electric field concentration on the surface or side surface due to the curvature of the pace diffusion layer, thereby improving the withstand voltage. Regarding (2), the spread of the depletion layer extending from the pace-collector junction toward the epitaxial layer is increased, thereby relaxing electric field concentration on the surface, side surfaces, or bottom portion, and improving breakdown voltage. (3) Regarding 1, the depletion layer extending from the pace-collector junction to the epitaxial layer side collides with the high-concentration layer, for example, the high-concentration buried layer, and prevents the breakdown voltage from decreasing due to leak-through.
This improves the withstand voltage.

As described above, in the vertical transistor, the pace-collector breakdown voltage (hereinafter referred to as BVCBO) and the emitter-collector breakdown voltage (hereinafter referred to as VBczn) can be improved. However, in high voltage ICs with BVcΣD'': about 200cm, a two-layer epitaxial structure as shown in Figure 3 is used.
'It shows the impurity concentration profile in the cross-sectional view. That is, after providing a P-type substrate 11, a CP-type second buried layer 3 and an N-type first buried layer 2, and providing an N-type first epitaxial layer 4, a Pfi third
After providing the buried layer 5 and providing the N-type second epitaxial layer 6a, a P-type isolation region 10 is provided and a large number of island regions t-&1 are provided.
．． The second epitaxial layer 4, 6a is provided with a P type base region 8. An N-type emitter region 9a and an N-type collector contact region 9b'f were sequentially formed to obtain a high breakdown voltage transistor.

In general, high voltage transistors with a two-layer epitaxial structure have the following characteristics: (1) Heat treatment time for insulation separation can be shortened.

(II) Due to (1), the increase in the size of multiple elements is relatively small.

[Phase] Coexistence with low voltage devices (e.g. ijMO8 transistor, I''L, etc.) is possible.

and so on.

[Problem that the invention seeks to solve]

However, BVcmn? For a high voltage IC of about 2QOV, the specific resistance of the bitaxial layer may be about 30Ω, and in order to achieve a high specific resistance, it is easy to do it by auto-doping boron from the P-layer buried layer during epitaxial layer growth. The phenomenon of reversal to P-type has recently occurred. In general, in high-voltage ICs, the epitaxial layer becomes thicker, so an 8iC1a source with a high growth rate is used, but growth using an 8iCj4 source requires a high growth temperature of around 1170°C. To be done and to be done,
Autodoping is encouraged. When this phenomenon occurs particularly in the boundary region between the first epitaxial layer and the second epitaxial layer, the current amplification factor (hereinafter referred to as %bvz) of the NPN transistor decreases, and the collector saturation voltage (hereinafter referred to as ■CΣcsai) decreases. ) caused a rise in

Furthermore, even if the P-type inversion layer does not reach the boundary region between the first epitaxial layer and the second epitaxial layer, the boundary region is further N''''
``'' type high resistance layer, similarly caused deterioration of device characteristics. FIG. 5 shows the impurity concentration boulograph of the t#3 diagram A-A' cross-sectional view when an F- type inversion layer or an N-1 type high resistivity layer is formed. The present invention aims to solve such problems. In a pie-hole high voltage IC having at least two epitaxial layers, an inversion layer or an inversion layer is provided in the boundary region between one epitaxial layer and the other epitaxial layer. It prevents the occurrence of a high resistance layer, reduces hyz, and reduces Vcz(sa
An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents an increase in t).

[Means for solving problems]
1. A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a first buried layer R- and a second buried layer of one conductivity type from the surface of a semiconductor substrate of one conductivity type. Thereafter, a step of forming a first epitaxial layer of another conductivity type, and then a step of forming at least the -conductivity type II on the surface of the first epitaxial layer. Step of forming the third buried layer of the mold, and then applying another conductive layer @2 of the mold.
In the method of manufacturing a semiconductor device including the step of forming a two-layer epitaxial layer, the first epitaxial layer is made of 8icla.
The second epitaxial layer is formed using a SiH4 source. At this time, the specific resistance of the second epitaxial layer is preferably formed to be smaller than the specific resistance of the first epitaxial layer.

〔Example〕

The present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(C) are structural sectional views showing one embodiment of the present invention. First, as shown in FIG. 1(a), an N-type first buried layer 2 is formed from the surface of a P-type substrate 1 by, for example, diffusion of SB or As, and then an insulation isolation layer is formed by diffusion of, for example, BCl3. A P-type second buried layer 3 is formed, and a sepic layer is formed on the substrate 1 including the apprentice 1 and the second buried layers 2 and 3.
m25~35Ωan, tepi=20-25μm N
--type first epitaxial layer 4 is grown. At this time, the first epitaxial layer 4 is grown by a reduction reaction of 8iC14 at about 1170°C.

Next, as shown in FIG. 4(b), a buried layer 5 of P-type holes 3 for insulation isolation is formed by diffusion of BCIm on the surface of the first epitaxial layer 4, and then a second buried layer 3 is formed. 1st including
N-type second epitaxial layer 6 on epitaxial layer 4
grow b. This second epitaxial layer 6b has 10
K grown by thermal decomposition of 8iH4 at about 50℃
Therefore, autodoping of boron is reduced compared to 8iC1a grown at high temperature. For this reason, the first epitaxial layer 4
It is grown to tepi=zo~25 μm with the same specific resistance as . Thereafter, the first and second epitaxial layers 4.6b are separated into island regions by diffusion forming the P-type isolation region 10, and the P-type base region 8.6b is separated into island regions. N-type emitter region 9a
, a transistor is obtained by forming the Nu collector contact region 9b. Figures 2(a), (b), and (C) show other embodiments of the present invention, in which the process of Figure 2(a) is performed. After forming the first epitaxial layer 4 and forming the P-type cavity 3 buried layer 5 in the process shown in FIG. ~
l Otim second epitaxial layer 6a is grown.

At this time, the second epitaxial layer #6a is made thick enough to cover the P-type cavity 3 buried layer 5. Next, as shown in FIG. 2(C), N of
− type third epitaxial layer 7 tepi=10~15μ
m grow. After that, P type isolation region 10. P-type pace area8. A transistor as shown in FIG. 1C is formed by forming an NM emitter region 9a and an N type collector contact region 9b. At this time, since the second epitaxial layer 6a has a high concentration, autodoping is more completely prevented, and since a transistor is formed in the third epitaxial layer 7, the characteristics of the transistor do not change.

〔Effect of the invention〕

As explained above, according to the present invention, the second epitaxial layer is grown by thermal decomposition of 8iH4, so the growth temperature is 1050°C, which is lower than that of 8iC1a, so the boron in the third buried layer is grown automatically. Since the doping is reduced, it is possible to prevent the formation of an inversion layer or a high resistance layer in the boundary region between the first epitaxial layer and the second epitaxial layer. Furthermore, by increasing the concentration of the second epitaxial layer, this autodoping can be more completely prevented.

Therefore, the decrease in IIFK of NPN) transistor, VCI
An extremely high diffusion yield can be achieved without causing an increase in (sat).

It should be noted that the present invention is not limited to the above-mentioned embodiments, and even if the polarity is changed, similar practical effects can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are structural sectional views showing the manufacturing process for explaining one embodiment of the present invention, and FIGS. 2(a) to (C)
3 is a structural cross-sectional view showing the manufacturing process for explaining another embodiment of the present invention, FIG. 3 is a structural cross-sectional view of a conventional NPN) transistor having a two-layer epitaxial layer structure, and FIG. The impurity concentration profile of the A-A' cross section, Figure 5 is the A-A' cross section of Figure 3 when an inversion layer or an expanded resistivity layer is formed in the boundary region between the first epitaxial layer and the second epitaxial island. This is the impurity frequency profile. 1... P type substrate, 2... N type first buried layer, 3... P type second buried layer, 4...
N-type first epitaxial layer, 5...P-type third buried layer, 6a, 6b...N! Second epitaxial layer, 7...N-type third epitaxial layer, 8.
...P type base region, 9a ... Nu emitter region, 9b ... N type collector contact region, 10 ... P presentation isolation region, P ... ...P
− type inversion layer, q...N=fi high resistivity layer. Agent Patent Attorney Susumu Uchihara to Pa. 2! N+ type prison l embedded view (e) No. zYgJ Iwa 3 Zujo 4 ℃

Claims (3)

[Claims] (1) forming a first buried layer of another conductivity type and a second buried layer of one conductivity type from the surface of a semiconductor substrate of one conductivity type;
Thereafter, a step of forming a first epitaxial layer of the other conductivity type, and a step of forming a third epitaxial layer of the one conductivity type in a portion corresponding to the second buried layer from the surface of the first epitaxial layer.
forming a buried layer; thereafter, vapor-growing the second epitaxial layer of the other conductivity type by thermal decomposition; and adding the third buried layer to the upper epitaxial layer including the second epitaxial layer. 1. A method for manufacturing a semiconductor device, comprising the steps of performing insulation isolation diffusion to reach the insulation isolation diffusion, and forming a semiconductor element in the upper epitaxial layer surrounded by the insulation isolation diffusion. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the resistivity of the second epitaxial layer is smaller than the resistivity of the first epitaxial layer. (3) Claim (1) characterized in that the third epitaxial layer of one conductivity type is formed on the second epitaxial layer to form the upper epitaxial layer.
The method for manufacturing a semiconductor device according to item (2) or item (2).