JPS5892264A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS5892264A JPS5892264A JP56191138A JP19113881A JPS5892264A JP S5892264 A JPS5892264 A JP S5892264A JP 56191138 A JP56191138 A JP 56191138A JP 19113881 A JP19113881 A JP 19113881A JP S5892264 A JPS5892264 A JP S5892264A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- active base
- collector
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- OQCFWECOQNPQCG-UHFFFAOYSA-N 1,3,4,8-tetrahydropyrimido[4,5-c]oxazin-7-one Chemical compound C1CONC2=C1C=NC(=O)N2 OQCFWECOQNPQCG-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 この発明は半導体集積回路装置に関するものである。[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.
半導体集積回路装置を構成するＰＮＰ ）ランジスタの
１つとして、従来からエピタキシャルベースＰＮＰ ト
ランジスタがあシ、これを第１図に示しである。この第
１図において、（１）はＰ型半導体基板、（２）はこの
基板（１）の主面上に成長させたＮＳ！！エピタキシャ
ル層、（３）は同層（２）上にＰ型不純物を選択拡散し
て形成したＰＮＰ ）ランジスタのコレクタ領域、（４
）はこれらの上に同様に成長されたＮ型エピタキシャル
層、（５）は同層（４）上にＰ型不純物を選択拡散して
形成したコレクタ引出し拡散層、（６１は同様にＰ型不
純物を選択拡散して形成したエミッタ領域、（７）は同
様にＮ型不純物を選択拡散して形成した同層（４）とし
てのベース領域（４′）のコンタクト拡散層である。そ
してこの従来のエピタキシャルベースＰＮＰ ）ランジ
スタの高周波特性−寸なわちｆＴ： Ｉｇ特性を第２図
に１またその不純物濃度プロファイルを第３図にそれぞ
れ表わしている。An epitaxial base PNP transistor has conventionally been used as one of the PNP transistors constituting a semiconductor integrated circuit device, and this is shown in FIG. In FIG. 1, (1) is a P-type semiconductor substrate, and (2) is NS! grown on the main surface of this substrate (1). ! Epitaxial layer (3) is a PNP formed by selectively diffusing P-type impurities on the same layer (2). Collector region of transistor (4)
) is an N-type epitaxial layer grown similarly on these layers, (5) is a collector extraction diffusion layer formed by selectively diffusing P-type impurities on the same layer (4), and (61 is a P-type impurity similarly grown). (7) is a contact diffusion layer of the base region (4') as the same layer (4), which is also formed by selectively diffusing N-type impurities. The high frequency characteristics of the epitaxial base PNP (PNP) transistor, namely fT: Ig characteristics, are shown in FIG. 2, and its impurity concentration profile is shown in FIG. 3, respectively.
こ＼でこのような従来のエピタキシャルベースＰＮＰ
）ランジスタにおいては、ベース領域がエピタキシャル
層によシ形成されているために、エミッタ領域からベー
ス領域に注入される少数キャリヤは加速電界を受けず、
従って拡散ベースＰＮＰトランジスタに比較してｆＴ：
Ｉｇ特性が劣るという欠点があった。これは次式によ
り知られる。すなわち、
一１１Ｔｉｗ ｒｓ 十ｒ６ （ｃｅ’＋ Ｃｃ）ひで
、τｙｓ／ｒｌ少数キャリヤのベース走行時間、ｒｃは
エミッタ抵抗、Ｃｅはエミッタ遷移容量、Ｃｃはコレク
タ遷移容量であり、エピタキシャルＰＮＰ ）ランジス
タは、通常、均一ベーストランジスタであるために、拡
散勾配に起因する加速電界を受けず、拡散ベーストラン
ジスタに比較してＴＢが大となり、ｆ’ｒが小となるの
である。Conventional epitaxial base PNP like this
) In a transistor, since the base region is formed by an epitaxial layer, minority carriers injected from the emitter region into the base region are not subjected to an accelerating electric field.
Therefore fT compared to a diffused-based PNP transistor:
It had the disadvantage of poor Ig characteristics. This is known from the following equation. That is, 111 Tiw rs 0 r6 (ce' + Cc), τys/rl Minority carrier base transit time, rc is the emitter resistance, Ce is the emitter transition capacitance, Cc is the collector transition capacitance, and the epitaxial PNP transistor is: Normally, since it is a uniform base transistor, it is not subjected to an accelerating electric field caused by a diffusion gradient, and thus TB becomes larger and f'r becomes smaller compared to a diffused base transistor.
この発明は従来のこのような欠点に鑑み、前記Ｐ重拡散
層からなるコレクタ領域ＫＮ型不純物を選択拡散して能
動ベース領域を形成させると共Ｋ。In view of the above-mentioned drawbacks of the prior art, the present invention includes forming an active base region by selectively diffusing KN-type impurities in the collector region consisting of the P heavy diffusion layer.
Ｐ重拡散層からなるエミッタ領域をこのエピタキシャル
層内にある能動ベース領域に達するように形成させて、
能動ベース領域によシ加速電界を構成させることによシ
高周波特性を改善し得るようにしたものである。An emitter region consisting of a P-heavy diffusion layer is formed in this epitaxial layer to reach an active base region,
By forming an accelerating electric field in the active base region, high frequency characteristics can be improved.
以下、この発明方法の一実施例につき、第４図ないし第
６図を参照して詳細に説明する。Hereinafter, one embodiment of the method of this invention will be described in detail with reference to FIGS. 4 to 6.
第４図においてこの実施例方法では、前記Ｐ重拡散層に
よるコレクタ領域（３）を形成したのち、Ｎ型不純物を
選択拡散して能動ベース領域（８）を形成させ、ついで
これらの上にＮ型エピタキシャル層（４）を成長させ、
その後Ｐ型不純物の選択拡散により、前記コレクタ領域
（３１に達するコレクタ引出し拡散層（５１と共に、能
動ベース領域（８）に達するエミッタ領域（９）を形成
させ、かつさらにＮ型不純物の選択拡散によるベースコ
ンタクト拡散層（７）を形成させるのである。In FIG. 4, in this embodiment method, after the collector region (3) is formed by the P heavy diffusion layer, an N-type impurity is selectively diffused to form an active base region (8), and then an N-type impurity is formed on the collector region (3). growing a type epitaxial layer (4);
Thereafter, by selective diffusion of P-type impurities, an emitter region (9) reaching the active base region (8) is formed together with the collector region (31), and an emitter region (9) reaching the active base region (8) is further formed by selective diffusion of N-type impurities. A base contact diffusion layer (7) is formed.
第５図はこの★流側方法によって得られるエピタキシャ
ルベースＰＮＰ ）ランジスタの不純物濃度プロファイ
ルを示しており、この第５図から明らかなように、新た
に形成された能動ベース領域（８）は、エミッタ領域か
ら注入される少数キャリヤが加速電界を受けるような濃
度勾配を有し、第６図に示すｆＴ： ＩＫ特性、すなわ
ち高周波特性について、前記第２図との比較から明らか
なように充分に優れたものが得られることになる。Fig. 5 shows the impurity concentration profile of the epitaxial base PNP transistor obtained by this ★stream side method, and as is clear from Fig. 5, the newly formed active base region (8) It has a concentration gradient such that the minority carriers injected from the region are subjected to an accelerating electric field, and the fT:IK characteristics shown in FIG. 6, that is, the high frequency characteristics, are sufficiently excellent as is clear from the comparison with FIG. You will get what you want.
以上詳述したようにこの発明方法によれば、半導体集積
回路装置に対し、個別半導体素子としての拡散ベースＰ
ＮＰ ）ランジスタと同様な高周波特性をもつエピタキ
シャルベースＰＮＰ ）ランジスタを形成でき、併せて
ＰＮＰ、ＮＰＮ）ランジスタのいわゆる相補型トランジ
スタの集積回路装置内への実現をより一層容易に可能と
するなどの特長を有するものである。As described in detail above, according to the method of the present invention, a diffusion base P as an individual semiconductor element can be used for a semiconductor integrated circuit device.
Features include being able to form epitaxial-based PNP) transistors with high frequency characteristics similar to those of NP) transistors, and making it easier to implement so-called complementary transistors of PNP and NPN) transistors in integrated circuit devices. It has the following.
第１図は従来例方法により半導体集積回路装置内に形成
されるＰＮＰ ）ランジスタを示す断面図、第２図およ
び第３図は同上トランジスタのｆＴ：工Ｅ′特性および
不純物濃度分布をそれぞれに示す説明図であり、また第
４図はこの発明の一実施例方法により半導体集積回路装
置内に形成されるＰＮＰトランジスタを示す断面図、第
５図および第６図は同上トランジスタの不純物濃度分布
およびｆＴ：ＩＥ％性をそれぞれに示す説明図である。
（１）・拳・・Ｐ型半導体基板、（２）・・嗜・Ｎｌｉ
エピタキシャル層、（３）・・−・Ｐ型コレクタ領域、
（４）・・・−Ｎｆｉエピタキシャル層、（５１・・・
・Ｐ型コレクタ引出し拡散層、（７）・−・・Ｎ型ベー
スコンタクト拡散層、（８）・・・・Ｎ型能動ベース領
域、（９）−＠・・Ｐ型エミッタ領域。
代理人 葛 野 信 −（外１名）
第４図
第２図Fig. 1 is a cross-sectional view showing a PNP transistor formed in a semiconductor integrated circuit device by a conventional method, and Figs. 2 and 3 show fT:E' characteristics and impurity concentration distribution of the same transistor, respectively. FIG. 4 is a sectional view showing a PNP transistor formed in a semiconductor integrated circuit device by a method according to an embodiment of the present invention, and FIGS. 5 and 6 show impurity concentration distribution and fT of the same transistor. : It is an explanatory diagram showing IE% characteristics. (1)・Fist・P-type semiconductor substrate, (2)・Ku・Nli
epitaxial layer, (3)...P-type collector region,
(4)...-Nfi epitaxial layer, (51...
・P-type collector extraction diffusion layer, (7)...N-type base contact diffusion layer, (8)...N-type active base region, (9)-@...P-type emitter region. Agent Shin Kuzuno - (1 other person) Figure 4 Figure 2
Claims (1)
層を成長する工程と、この第１のＮ型エピタキシャル層
上にＰ型不純物を選択的に拡散してコレクタ領域を形成
する工程と、このコレクタ領域にＮ型不純物を選択的に
拡散して能動ベース領域を形成する工程と、これらの上
に第２のＮ型エピタキシャル層を成長する工程と、この
第２のＮ型エピタキシャル層表面から、前記コレクタ領
域および能動ベース領域にそれぞれ達するようＫＰ型不
純物を選択的に拡散してコレクタ引出し拡散領域および
エミッタ領域を形成する工程と、さらＫこの第２のＮ型
エピタキシャル層表面からＮ型不純物を選択的に拡散し
てベースコンタクト拡散層を形成する工程とを含んでＰ
ＮＰ ）ランジスタを構成することを特徴とする半導体
集積回路装置の製造方法。A step of growing a first N-type epitaxial layer on the main surface of a P-type semiconductor substrate, and a step of selectively diffusing P-type impurities onto this first N-type epitaxial layer to form a collector region. a step of selectively diffusing N-type impurities into this collector region to form an active base region; a step of growing a second N-type epitaxial layer thereon; and a step of growing a second N-type epitaxial layer on the active base region. selectively diffusing KP-type impurities from the surface to reach the collector region and active base region, respectively, to form a collector lead-out diffusion region and an emitter region; selectively diffusing type impurities to form a base contact diffusion layer.
NP) A method for manufacturing a semiconductor integrated circuit device comprising a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56191138A JPS5892264A (en) | 1981-11-27 | 1981-11-27 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56191138A JPS5892264A (en) | 1981-11-27 | 1981-11-27 | Manufacture of semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5892264A true JPS5892264A (en) | 1983-06-01 |
| JPH0138378B2 JPH0138378B2 (en) | 1989-08-14 |
Family
ID=16269513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56191138A Granted JPS5892264A (en) | 1981-11-27 | 1981-11-27 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5892264A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267931A (en) * | 1989-12-14 | 1993-10-15 | Communications Satellite Corp (Comsat) | Micro strip antenna for cross polarization double band |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104076A (en) * | 1976-02-27 | 1977-09-01 | Sony Corp | Semiconductor unit |
| JPS53134374A (en) * | 1977-04-28 | 1978-11-22 | Sony Corp | Semiconductor device |
-
1981
- 1981-11-27 JP JP56191138A patent/JPS5892264A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104076A (en) * | 1976-02-27 | 1977-09-01 | Sony Corp | Semiconductor unit |
| JPS53134374A (en) * | 1977-04-28 | 1978-11-22 | Sony Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267931A (en) * | 1989-12-14 | 1993-10-15 | Communications Satellite Corp (Comsat) | Micro strip antenna for cross polarization double band |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0138378B2 (en) | 1989-08-14 |
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