JPS59184523A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS59184523A
JPS59184523A JP5952683A JP5952683A JPS59184523A JP S59184523 A JPS59184523 A JP S59184523A JP 5952683 A JP5952683 A JP 5952683A JP 5952683 A JP5952683 A JP 5952683A JP S59184523 A JPS59184523 A JP S59184523A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
nitride film
integrated circuit
regions
electrode contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5952683A
Other languages
Japanese (ja)
Other versions
JPH0257703B2 (en
Inventor
Tadashi Kishi
正 岸
Kenji Kanezaki
金崎　賢治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP5952683A priority Critical patent/JPS59184523A/en
Publication of JPS59184523A publication Critical patent/JPS59184523A/en
Publication of JPH0257703B2 publication Critical patent/JPH0257703B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To restrain the reaction of an Al wiring with an Si substrate as well as to enable simple manufacture of semiconductor integrated circuit of high quality having high hfe by forming an Si-rich nitride film in the electrode contact part and forming an electrode wiring after removing and nitride film. CONSTITUTION:A silicon nitride film 9 including more Si than N (Si-rich) is formed on oxide films 8 and electrode contact parts 41, 61 and 71. At this time, Si regions 10 including a small quantity of N are formed in the regions being in contact with the electrode contact parts of a collector 4, a base 6 and an emitter 7 respectively. Subsequently, the nitride film 9 on the Si regions 10 is removed. Subsequently, electrode wiring regions 11, for example, of Al are formed to be completed on the electrode contact parts 41, 61 and 71 where the nitride film 9 was already removed. As the Si regions 10 including a small quantity of N functions so as to restrain the reaction of Al with Si, the semiconductor integrated circuit of high quality having high hfe can be fabricated by a simple processes.

Description

【発明の詳細な説明】 本発明は、半導体集積回路の製造方法に関するものであ
る。更に詳しくは、本発明は高品質の半導体集積回路を
簡単な製造工程で製造できる製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit. More specifically, the present invention relates to a manufacturing method capable of manufacturing high quality semiconductor integrated circuits through simple manufacturing steps.

従来、半導体集積回路は配線領域上にリンガラスを形成
している。リンガラスは、ゲッタリング作用がある上に
、比較的厚い膜を形成出来るといった効果があるが、保
護膜としては十分でない。Conventionally, in semiconductor integrated circuits, a phosphor glass is formed on a wiring area. Phosphorous glass has a gettering effect and is effective in forming a relatively thick film, but is not sufficient as a protective film.

また、一部では配線領域上、あるいは下にテラ化膜を保
護膜として形成し、高品質の半導体集積回路を製造する
ようにしだものもある。この場合、テラ化膜と、Ｓ１領
域の界面が不安定である為に、テラ化膜を直接Ｓｉ上に
形成しないで、両者間に８１０２を介してテラ化膜を形
成するようにしている。In some cases, a TERA film is formed as a protective film on or below the wiring area to manufacture high-quality semiconductor integrated circuits. In this case, since the interface between the TELLA film and the S1 region is unstable, the TELLA film is not formed directly on Si, but is formed via 8102 between them.

従って、テラ化膜は、単に保護膜あるいは８１基板の歪
応力の解消の役割を果たすのみで、それ以上の効果、例
えばＡ１配線やＳｉ層におけるＳｌの反応を防止する等
の効果を期待することはできなかった。Therefore, the TERRA film only serves as a protective film or to relieve the strain stress of the 81 substrate, and it is not expected that it will have more effects, such as preventing the reaction of Sl in the A1 wiring and the Si layer. I couldn't.

ＡＩ配線やＳｉ層におけるＳｌの反応を防止する為には
、両者の間に、例えばショットキーＴＴＬの場合におけ
るＴｉ−Ｗ層や、ＭＯ３メモリーの場合におけるＳｉ層
のようた何んらかの層を形成する必要がある。In order to prevent the reaction of Sl in the AI wiring and Si layer, some kind of layer should be placed between them, such as a Ti-W layer in the case of Schottky TTL or a Si layer in the case of MO3 memory. need to be formed.

ここにおいて、本発明は、例えばＡＩの配線と８１基板
の反応を抑制するとともに、高いｈｆｅを持った高品質
の半導体集積回路を簡単に製造することのできる製造方
法を提供しようとするものである。Here, the present invention aims to provide a manufacturing method that can suppress the reaction between, for example, an AI wiring and an 81 substrate, and can easily manufacture a high quality semiconductor integrated circuit with a high hfe. .

本発明に係る方法は、電極コンタクト部分に８１リツチ
なテラ化膜を形成し、このテラ化膜を除去した後に電極
配線を形成するようにした点に特徴がある。The method according to the present invention is characterized in that an 81-rich terra film is formed on the electrode contact portion, and the electrode wiring is formed after this terra film is removed.

第１図〜第４図は本発明に係る方法の主要部分の手順を
説明するだめの構成断面図で、ここではバイポーラＩＣ
のｎｐｎトランジスタを例にとって示しである。1 to 4 are cross-sectional views of the structure of a bipolar IC for explaining the steps of the main parts of the method according to the present invention.
The following is an example of an npn transistor.

第１図において、１はＰ型半導体基体、２は訂型埋込領
域、５はｎ型エピタキシャル層、４はｎ＋型コレクタ領
域、５はＰ型絶縁分離領域、６はＰ型ベース領域、７は
ｎ型エミッタ領域、８は酸化膜である。ｎ型エピタキシ
ャル層５は、Ｐ型絶縁分離領域５で分離され、はじめに
、このｎ型エピタキシャル層３に、コレクタ低抵抗領域
４、ベース領域６及びエミッタ領域７を形成する。その
後、酸化膜８を形成し、これを選択的に除去して、コレ
クタ領域４、ベース領域６及びエミッタ領域７上にそれ
ぞれ電極コンタクト部４１．６１及び７１を形成する。In FIG. 1, 1 is a P-type semiconductor substrate, 2 is a reshaped buried region, 5 is an n-type epitaxial layer, 4 is an n+-type collector region, 5 is a P-type isolation region, 6 is a P-type base region, and 7 is an n-type emitter region, and 8 is an oxide film. The n-type epitaxial layer 5 is separated by a P-type isolation region 5, and first, a collector low resistance region 4, a base region 6, and an emitter region 7 are formed in this n-type epitaxial layer 3. Thereafter, an oxide film 8 is formed and selectively removed to form electrode contact portions 41.61 and 71 on the collector region 4, base region 6, and emitter region 7, respectively.

続いて、第２図に示すように、Ｓｉの含有量がＮよシ多
い（これをＳｉリッチという）シリコンチッ化膜９を、
各酸化膜８上及び各電極コンタクト部４１．６１．７１
上に形成する。この時、コレクタ４゜ベース６、エミッ
タ７の各電極コンタクト部に接する各領域には、Ｎを微
量含んだＳ１領域１０がそれぞれ形成される。Next, as shown in FIG. 2, a silicon nitride film 9 containing more Si than N (referred to as Si-rich) was formed.
On each oxide film 8 and each electrode contact part 41.61.71
Form on top. At this time, an S1 region 10 containing a small amount of N is formed in each region in contact with each electrode contact portion of the collector 4°, base 6, and emitter 7.

続いて、第３図に示すように、Ｓ１領域１０上のチッ化
膜５を、ホトレジスト技術を利用して選択的に除去する
。Subsequently, as shown in FIG. 3, the nitride film 5 on the S1 region 10 is selectively removed using photoresist technology.

続いて、第４図に示すように、例えばＡＩの電極配線領
域１１を、チッ化膜９を除去した電極コンタクト部４１
．６１．７１部分に形成して完成させる。Subsequently, as shown in FIG. 4, for example, the electrode wiring region 11 of AI is formed into an electrode contact portion 41 with the nitride film 9 removed.
．． 61. Complete by forming the 71 part.

このようにして製造される半導体集積回路は、Ｎを微量
含んだＳ１領域１０がＡ１とＳｌの反応を抑制する作用
をなすもので、本発明によれば、高品質で、かつり、ｅ
が高いの半導体集積回路を簡単な工程で製作することが
できる。In the semiconductor integrated circuit manufactured in this manner, the S1 region 10 containing a small amount of N acts to suppress the reaction between A1 and Sl, and according to the present invention, the semiconductor integrated circuit is of high quality and has e.g.
High-performance semiconductor integrated circuits can be manufactured using simple processes.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第４図は本発明に係る方法の手順を説明するた
めの詞明図である。 １・・・Ｐ型半導体基体、４１．６１．７１・・・電極
コンタ（５ノ クト部分、８・・・酸化膜、９・・・５ＩＩＪツチなチ
ッ化膜、１１・・・電極配線領域。 （４） 応　／　４ β 第　２１４1 to 4 are illustrations for explaining the procedure of the method according to the present invention. 1...P-type semiconductor substrate, 41.61.71...electrode contour (5 node part, 8...oxide film, 9...5IIJ-like nitride film, 11...electrode wiring area). (4) Response / 4 β No. 214

Claims (1)

【特許請求の範囲】[Claims] （１）　　電極配線領域を形成する工程を含んだ半導体
集積回路の製造方法であって、 電極コンタクト部分にはじめＳｔリッチなテラ化膜を形
成し、その後このテラ化膜を除去し、当該電極コンタク
ト部分に電極配線領域を形成するようにしたことを特徴
とする半導体集積回路の製造方法。(1) A method for manufacturing a semiconductor integrated circuit including a step of forming an electrode wiring region, the method comprising: first forming a St-rich TELLA film on an electrode contact portion; then removing this TELLA film; 1. A method of manufacturing a semiconductor integrated circuit, characterized in that an electrode wiring region is formed in a portion.
JP5952683A 1983-04-05 1983-04-05 Manufacture of semiconductor integrated circuit Granted JPS59184523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5952683A JPS59184523A (en) 1983-04-05 1983-04-05 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5952683A JPS59184523A (en) 1983-04-05 1983-04-05 Manufacture of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS59184523A true JPS59184523A (en) 1984-10-19
JPH0257703B2 JPH0257703B2 (en) 1990-12-05

Family

ID=13115801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5952683A Granted JPS59184523A (en) 1983-04-05 1983-04-05 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS59184523A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009018193A (en) * 2008-10-03 2009-01-29 Twinbird Corp Brush apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0416004U (en) * 1990-05-31 1992-02-10

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53115173A (en) * 1977-03-18 1978-10-07 Hitachi Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53115173A (en) * 1977-03-18 1978-10-07 Hitachi Ltd Production of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009018193A (en) * 2008-10-03 2009-01-29 Twinbird Corp Brush apparatus

Also Published As

Publication number Publication date
JPH0257703B2 (en) 1990-12-05

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