JPH0851222A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device, where breakdown strength of a well and an element isolating area is improved and the breakdown strength is improved as a whole, and its manufacturing method. CONSTITUTION:This is a semiconductor device, where an epitaxial growth layer of different conductivity type from that of a semiconductor substrate 1 is made on the surface of that semiconductor substrate 1 and a semiconductor element is made in a well 2 being made separately by the element isolating region 8 provided in the epitaxial growth layer, and in this device a ring-shaped region 9 of the same conductivity as the well 2 is provided electrically independent of the well 2, around the well and besides within the element isolating region 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of elements such as ICs and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device in which the breakdown voltage between the well in which each element is formed and the element isolation region is improved, and the breakdown voltage is improved as a whole, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, various measures for improving the breakdown voltage of a pn junction have been taken in individual semiconductors such as power transistors. For example, p in the base region and collector region of the transistor
In the n-junction, the pn junction at the curved portion or the semiconductor layer surface is particularly weak against breakdown voltage, and the depletion layer is expanded by reducing the impurity concentration in the collector region, or the base region is formed adjacent to the base region on the semiconductor layer surface. A field limiting ring (FLR) of the same conductivity type and electrically independent of the base region is provided, and the end of the depletion layer on the semiconductor layer surface is connected to the depletion layer formed by the field limiting ring. The withstand voltage is improved by moving away from it.

On the other hand, in the case of ICs as well, with the integration and integration of high breakdown voltage elements (high breakdown voltage transistors), the conventional 35 to 35
A high breakdown voltage of 50 V to 200 V or higher has been required. In a normal IC, as shown in FIG. 3, one element portion is shown in a partial cross-sectional perspective view, an epitaxial growth layer provided on a semiconductor substrate 1 is separated by an element isolation region (isolation) 8 to form a well 2 in the well 2. Then, each semiconductor element such as a transistor is formed in each well 2.
The well 2 is formed, for example, as follows.

First, an n-type impurity such as arsenic for forming the buried layer 6 is formed on the surface of the semiconductor substrate 1 made of, for example, p-type silicon by coating diffusion or ion implantation for forming the buried layer 6. Then, p-type impurities such as boron are introduced to form the lower layer portion 8a of the element isolation region 8 on both sides thereof, and an n-type semiconductor layer is epitaxially grown.

After the epitaxial growth layer is formed, a p-type impurity such as boron is introduced into the surface of the formation portion of the element isolation region 8 by coating diffusion or ion implantation, and a heat treatment is performed to diffuse the p-type impurity. Lower part 8 of the element isolation region diffused to the lower layer and diffused upward
The element isolation region 8 is formed by joining with a. as a result,
An n-type well 2 having a buried layer 6 at the bottom surrounded by a p-type region is formed, and, for example, a p-type base region 3 and an n-type emitter region 4 are formed in the well 2. Thus, a transistor having the well 2 as the collector region is independently formed. Since the element isolation region 8 is formed mainly by impurity diffusion from the surface of the semiconductor layer,
A curved portion A is formed at the lower end of the well 2. Reference numeral 5 is an n ⁺ -type high-concentration impurity region for obtaining ohmic contact with the collector electrode, and 7 is an n-type well 2 and semiconductor substrate 1.
And the expansion of the depletion layer of the pn junction with the p-type region of the element isolation region 8, which is usually about 10 to 20 μm. In addition, the buried layer 6 and the lower layer portion 8a of the element isolation region may not be formed.

[0006]

The withstand voltage of each element in the IC can be improved to some extent by the same measures as those of the individual semiconductor device described above, but in the case of the IC, even if the withstand voltage of the element is improved. It does not necessarily improve the breakdown voltage of the IC. That is, the well 2 is not limited to the pn junction with the base region 3 but also the semiconductor substrate 1 and the element isolation region 8
A pn junction is also formed between the
As shown in FIG. 3, a curvature portion A is formed at the lower end portion of the well 2, and breakdown of breakdown voltage is most likely to occur at this portion,
There is a problem that the breakdown voltage of a semiconductor device such as an IC cannot be improved.

It is an object of the present invention to solve the above problems and to provide a semiconductor device having an improved withstand voltage between the well and the element isolation region, and an improved withstand voltage as a whole, and a manufacturing method thereof.

[0008]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device in which an epitaxial growth layer having a conductivity type different from that of the semiconductor substrate is formed on a surface of a semiconductor substrate, and semiconductor elements are formed in wells formed by element isolation regions provided in the epitaxial growth layer. Therefore, a ring-shaped region having the same conductivity type as the well and electrically independent of the well is provided around the well and in the element isolation region.

It is preferable that two or more ring-shaped regions are provided because the breakdown voltage can be further improved.

According to the method of manufacturing a semiconductor device of the present invention, (a) an epitaxial growth layer having a conductivity type different from that of the semiconductor substrate is formed on the surface of the semiconductor substrate, and (b) a well forming place around the epitaxial growth layer is formed. Impurity regions of the same conductivity type as the semiconductor substrate to serve as element isolation regions are provided at least twice so as to reach the surface of the semiconductor substrate, and (c) at least the semiconductor device is formed in the well region. A ring-shaped region of the same conductivity type as the well sandwiched by double impurity regions is formed in the element isolation region electrically independent of the well.

[0011]

According to the present invention, since a ring-shaped region having the same conductivity type as the well and electrically independent from the well is formed around the well in the element isolation region, the region between the well and the element isolation region is formed. The depletion layer formed in the pn junction is formed by connecting with the depletion layer formed by the ring-shaped region. Therefore, the depletion layer at the edge portion of the well expands, the radius of curvature of the depletion layer increases, electric field concentration is less likely to occur at the edge curvature portion, and the breakdown voltage improves.

As a result, the breakdown voltage of the entire junction between the well and the element isolation region is improved, and the breakdown voltage of the entire semiconductor device is also improved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device of the present invention and a manufacturing method thereof will be described with reference to the drawings. 1 is a partial cross-sectional perspective view of an embodiment of the semiconductor device of the present invention, and FIG. 2 is a diagram showing the manufacturing process thereof.

In FIG. 1, 1 to 8 show the same parts as in FIG. 3, and 9 is a ring-shaped region of the same conductivity type as the well 2 and provided in the element isolation region 8 so as to surround the well 2.

The present invention is characterized in that a ring-shaped region 9 having the same conductivity type as the well 2 and electrically independent of the well 2 is provided in the element isolation region 8 around the well 2. The ring-shaped region 9 has a distance a from the end of the well 2.
Is about 5 to 30 μm, and its width b is about 5 to 20 μm. Since there is this ring-shaped region 9, the well 2
The depletion layer 7 of the pn junction between the n-type region and the p-type region of the semiconductor substrate 1 and the element isolation region 8 is connected to the depletion layer 7 formed by the ring-shaped region 9 as shown in FIG. Extend to the surface of the semiconductor layer. That is, although the ring-shaped region 9 is electrically independent of the well 2, it has the same conductivity type as the well 2, an internal potential is generated, and the depletion layer 7 is formed at the junction with the element isolation region 8. Therefore, the depletion layer 7 is connected to the depletion layer formed by the ring-shaped region 9 and extends to the surface side of the semiconductor layer. As a result, the depletion layer 7 is not formed along the curvature portion A at the bottom edge of the well 2 and becomes far away, and the depletion layer at the curvature portion A at the edge with the weakest withstand voltage expands and becomes far away. It becomes gentle and the pressure resistance is improved. On the other hand, the depletion layer 7 is formed around the ring-shaped region 9 and near the edge portion B of the ring-shaped region 9 and the surface portion C of the semiconductor layer, but the ring-shaped region 9 is electrically isolated from the well 2. Since the well 2 and the depletion layer 7 are separated from each other by a + b, the breakdown between the well 2 and the element isolation region is unlikely to occur. Further, it is preferable that the corner portion D of the ring-shaped region is rounded with a large curvature, but the corner portion D does not pose any problem.

In order to further improve the breakdown voltage,
By providing second and third ring-shaped regions on the outer periphery of the ring-shaped region 9 at similar intervals of a and b, the well 2
And the depletion layer 7 can be separated from each other, and an IC having a higher breakdown voltage can be obtained.

Next, a method of manufacturing the semiconductor device of the present invention will be described with reference to FIG.

First, n ⁺ shown in FIG. 1 is formed on the semiconductor substrate 1 shown in FIG. 2A, which is made of p-type silicon having an impurity concentration of about 2 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³ , for example. In order to form the buried layer 6 having a shape, for example, impurities such as arsenic are introduced by ion implantation, coating diffusion or the like to form the lower layer portion 6a of the buried layer (see FIG. 2B). Next, as shown in FIG. 2C, impurities such as boron are introduced in order to form the lower layer portions 8a and 8b of the element isolation region on the outer periphery of the lower layer portion 6a of the buried layer. At this time, since the ring-shaped region 9 is formed in the element isolation region 8, the structure shown in FIG.
As shown in (c), the lower layer portion 8a of the element isolation region,
8b is provided in a double ring shape.

Next, as shown in FIG. 2D, the impurity concentration is, for example, 1.5 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm 3.
A semiconductor crystal layer doped with an n-type impurity is epitaxially grown so as to have a thickness of about ³ to form an epitaxial growth layer 2a.

Next, lower layers 8a and 8b of the element isolation region are formed.
The p-type impurities 8c and 8d such as boron are introduced into the surface of the epitaxial growth layer 2a corresponding to 1 by ion implantation, coating diffusion, etc. (see FIG. 2 (e)). Then, by performing a heat treatment at 1000 to 1300 ° C. for about 5 to 15 hours, impurities 8c and 8d on the surface of the epitaxial growth layer 2a diffuse into the lower layers 8a and 8b as shown in FIG. 2 (f). The well 2 surrounded by the p-type semiconductor substrate 1 and the element isolation region 8 is formed, and the ring-shaped region 9 is formed in the element isolation region 8.

A transistor or the like can be formed in the well 2 by providing the base region 3 and the emitter region 4 shown in FIG. 1 by a known manufacturing method.

When the ring-shaped regions 9 are provided in double or triple layers, the element isolation regions may be formed in triple layers or triple layers, which can be easily formed in the same manner without increasing the number of steps.
Furthermore, although the n-type well is formed in the p-type semiconductor substrate in the above description, the n-type and p-type wells may be reversed.

[0023]

According to the semiconductor device of the present invention, since the ring-shaped region having the same conductivity type as that of the well is formed so as to surround the well in the element isolation region, the depletion layer is separated from the edge portion of the well. Firewood formed apart. As a result, concentration of an electric field at the edge of the well is eliminated, breakdown is less likely to occur, and a semiconductor device such as an IC having a higher breakdown voltage than that of the element can be obtained.

Further, according to the manufacturing method of the present invention, the diffusion region of the element isolation region is doubled or tripled when the element isolation region is formed.
The ring-shaped region can be easily formed without increasing the number of steps, and the breakdown voltage of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional perspective view showing an embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device in FIG.

FIG. 3 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

 1 semiconductor substrate 2 well 8 element isolation region 9 ring-shaped region

Claims (3)

[Claims] 1. An epitaxial growth layer having a conductivity type different from that of the semiconductor substrate is formed on a surface of the semiconductor substrate,
A semiconductor device in which a semiconductor element is formed in a well formed by being isolated by an element isolation region provided in the epitaxial growth layer, the semiconductor device having the same conductivity as the well in the periphery of the well and in the element isolation region. A semiconductor device in which a ring-shaped region is provided in a mold so as to be electrically independent of the well. 2. The semiconductor device according to claim 1, wherein two or more ring-shaped regions are provided. 3. (a) An epitaxial growth layer having a conductivity type different from that of the semiconductor substrate is formed on the surface of the semiconductor substrate, and (b) an element isolation region is formed around a well forming place of the epitaxial growth layer. Impurity regions of the same conductivity type as the semiconductor substrate are provided at least twice so as to reach the surface of the semiconductor substrate, and (c) a semiconductor element is formed in the well region so as to be sandwiched by the at least double impurity regions. A method of manufacturing a semiconductor device, characterized in that a ring-shaped region having the same conductivity type as that of the well is formed in the element isolation region electrically independently of the well.