JPS61269330A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61269330A JPS61269330A JP11167085A JP11167085A JPS61269330A JP S61269330 A JPS61269330 A JP S61269330A JP 11167085 A JP11167085 A JP 11167085A JP 11167085 A JP11167085 A JP 11167085A JP S61269330 A JPS61269330 A JP S61269330A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- silicon
- film
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、酸化膜分離法を用いる半導体集積回路の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit using an oxide film separation method.
従来の技術
半導体集積回路においては、近年高周波化、高密度化、
低消費電力化をはかるために、酸化膜分離法と呼ばれる
素子間分離技術が多く使用されている。第2図はこれに
よって形成された素子の断面図である。この構造はP形
単結晶シリコン基板(1)に、その逆導電形のN形埋込
層(2)を形成し、さらにこの上からN形又はP形シリ
コン層(3)をエピタキシャル成長させ、このシリコン
層(3)において前記N形埋込層(2)の上部に位置す
る部分を除く周辺部分を所定の深さまで等方的に食刻し
た後、N形埋込層(2)に隣接する分離領域(基板(1
)−シリコン層(3)の周辺との間)にチャンネルが形
成されるのを防ぐためにイオン注入法でP形不純物層(
4)を形成し、先の食刻した部分の残存シリコン層を酸
化膜(5)に変換して、埋込層(2)上のシリコン層(
3)による島領域を形成するものである。Conventional technology Semiconductor integrated circuits have recently seen higher frequencies, higher densities,
In order to reduce power consumption, an element isolation technique called an oxide film isolation method is often used. FIG. 2 is a sectional view of an element formed thereby. This structure consists of forming an N-type buried layer (2) of the opposite conductivity type on a P-type single crystal silicon substrate (1), and then epitaxially growing an N-type or P-type silicon layer (3) on top of this. After isotropically etching the peripheral portion of the silicon layer (3), excluding the portion located above the N-type buried layer (2), to a predetermined depth, a portion adjacent to the N-type buried layer (2) is etched. Separation area (substrate (1)
) and the periphery of the silicon layer (3)), a P-type impurity layer (
4), converting the remaining silicon layer in the previously etched portion into an oxide film (5), and forming the silicon layer (5) on the buried layer (2).
3) forms an island region.
発明が解決しようとする問題点
しかし、この様な従来の製造方法では、P形不純物層(
4)のイオン注入の際、オフアングル注入によりN形シ
リコン層(3)の側面にもP形不純物が入ることを防止
するため、N形シリコン層(3)の側面をオフアングル
による入り込み分dだけエツチングしておかねばならず
、これが高密度化において大きな支障となっていた。Problems to be Solved by the Invention However, in such conventional manufacturing methods, the P-type impurity layer (
During the ion implantation in step 4), in order to prevent P-type impurities from entering the side surfaces of the N-type silicon layer (3) due to off-angle implantation, the side surfaces of the N-type silicon layer (3) are implanted by the off-angle implantation amount d. This was a major hindrance in increasing the density.
本発明は、この様な埋め込み層上のN形シリコン層の側
面にチャンネルストッパー用のP形不純物が入ることな
く、パターン通シの素子を得ることを目的とするもので
ある。The object of the present invention is to obtain a pattern-through element without introducing P-type impurities for a channel stopper into the side surfaces of the N-type silicon layer on such a buried layer.
問題点を解決するための手段
上記の問題点を解決するため、本発明の半導体集積回路
の製造方法は、P形又はN形からなる一導電形のシリコ
ン基板に逆導電形の埋め込み層を形成する工程と、前記
埋め込み層を含むシリコン基板上に前記一導電形あるい
は逆導電形のシリコン層をエピタキシャル成長させる工
程と、前記埋め込み層の上に位置する部分の前記シリコ
ン層を残し、その周辺のシリコン層を所定の深さまで異
方的に食刻する工程と、前記埋め込み層の上に位置する
部分及びその周辺食刻部からなる前記シリコン層の全面
に薄膜を形成する工程と、イオン注入法により埋め込み
層上のシリコン層以外のシリコン層にのみ一導電形の不
純物を形成する工程と、前記薄膜を除去する工程と、前
記シリコン層の部分を酸化物層に変換する工程とを含む
ものである。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor integrated circuit of the present invention includes forming a buried layer of the opposite conductivity type on a silicon substrate of one conductivity type consisting of P type or N type. a step of epitaxially growing the silicon layer of one conductivity type or the opposite conductivity type on the silicon substrate including the buried layer, leaving a portion of the silicon layer located on the buried layer and growing the silicon around it; a step of etching the layer anisotropically to a predetermined depth; a step of forming a thin film on the entire surface of the silicon layer consisting of a portion located on the buried layer and the etched portion around it; and a step of forming a thin film by ion implantation. This method includes the steps of forming an impurity of one conductivity type only in a silicon layer other than the silicon layer on the buried layer, removing the thin film, and converting a portion of the silicon layer into an oxide layer.
作用
この製造方法によれば、異方性エッチで寸法通シにエッ
チし、全面を酸化シリコン層等の薄膜でおおってからチ
ャンネルストッパー用の不純物を蒸着するため、寸法精
度が良く、かつ不純物が混入しない高密度、高信頼性の
素子が形成される。Function: According to this manufacturing method, the entire surface is etched with anisotropic etching, the entire surface is covered with a thin film such as a silicon oxide layer, and then the impurity for the channel stopper is vapor deposited, resulting in good dimensional accuracy and no impurities. A high-density, highly reliable device free from contamination is formed.
実施例
本発明の半導体集積回路の製造方法の一実施例を第1図
a ”−’ cの工程順断面図を参照して説明する。Embodiment An embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to step-by-step cross-sectional views of FIGS.
まず、第1図aのように、P形単結晶シリコン基板(1
)の上に厚さが0.5〜2μmの酸化シリコン膜(図示
せず)を形成し、これをマスクとしてアンチモン(sb
)、あるいは砒素(As)をスピンオン法やイオン注入
法により選択的にドープしてN形埋め込み層(イ)を形
成する。First, as shown in Figure 1a, a P-type single crystal silicon substrate (1
), a silicon oxide film (not shown) with a thickness of 0.5 to 2 μm is formed, and using this as a mask, antimony (sb
) or selectively doped with arsenic (As) by spin-on method or ion implantation method to form an N-type buried layer (a).
次いで、酸化シリコン膜全てを除去し、引き続いて埋め
込み層(2)の表面、及びシリコン基板(1〕の表面全
体に比抵抗が0.5〜2.0ΩαのP形あるいはN形シ
リコン層(3)を0.5〜2.0μmの厚さにエピタキ
シャル成長させ、こののちシリコン層(3)の表面全域
に厚さが100〜500人の酸化シリコン膜(6)と厚
さが500〜1500人の窒化シリコン膜(7)を順次
形成した後、これらの膜を選択的にエツチングしてN形
埋込層(2)上にのみ酸化シリコン膜(6)と窒化シリ
コン膜(7)を残す。次に、第1図すのように、ドライ
エッチ等で露出したシリコン層(3)の部分を、その厚
みが半分程度になるまで異方性エツチングする。そして
、CVD法等によシ、酸化シリコン膜あるいは窒化シリ
コン膜の薄膜(8)を厚さ1000〜5000人全面に
蒸着し、そノ後チャンネルストッパー用のポロンの)を
N形埋め込み層(2)に隣接する分離領域下にのみイオ
ン注入してP形不純物層(4)を形成し、その後酸化シ
リコン膜等の薄膜(8)を全面除去する。Next, the entire silicon oxide film is removed, and then a P-type or N-type silicon layer (3 ) is epitaxially grown to a thickness of 0.5 to 2.0 μm, and then a silicon oxide film (6) with a thickness of 100 to 500 μm and a silicon oxide film (6) with a thickness of 500 to 1500 μm are formed over the entire surface of the silicon layer (3). After sequentially forming silicon nitride films (7), these films are selectively etched to leave the silicon oxide film (6) and silicon nitride film (7) only on the N-type buried layer (2). Next, as shown in Figure 1, the silicon layer (3) exposed by dry etching is anisotropically etched until its thickness is reduced to about half.Then, by CVD or the like, silicon oxide is etched. A thin film (8) of silicon nitride film or silicon nitride film is deposited to a thickness of 1000 to 5000 nm over the entire surface, and then a channel stopper (of poron) is ion-implanted only under the isolation region adjacent to the N-type buried layer (2). A P-type impurity layer (4) is then formed, and then the thin film (8) such as a silicon oxide film is completely removed.
こののち、第1図Cのように、高圧酸化炉等で酸化処理
する、この処理で窒化シリコン膜(7)により覆われて
いないシリコン層(3)の部分が選択的に酸化されて分
離酸化膜(5)となシ、同分離酸化膜(5)で囲まれた
シリコン層(3)による島領域が形成される。そして、
この島領域は、半導体集積回路の要素素子を形成する部
分となる。After this, as shown in FIG. In addition to the film (5), an island region is formed by the silicon layer (3) surrounded by the isolation oxide film (5). and,
This island region becomes a portion forming elemental elements of a semiconductor integrated circuit.
以上説明した本発明の半導体集積回路の製造方法では不
純物が入り込むことなくエピタキシャル層をパターン通
りに分離できる。In the method for manufacturing a semiconductor integrated circuit of the present invention described above, the epitaxial layer can be separated according to a pattern without introducing impurities.
発明の効果
本発明の半導体集積回路の製造方法によれば、エツチン
グをパターン通りに行なっても、エピタキシャル層の側
面に不純物が入らないため、高密度、高信頼性の素子を
形成することができる。Effects of the Invention According to the method of manufacturing a semiconductor integrated circuit of the present invention, even if etching is performed according to a pattern, impurities do not enter the side surfaces of the epitaxial layer, so a high-density, highly reliable device can be formed. .
第1図a、b、cは本発明の一実施例の工程順断面図、
第2図は従来の製造方法で形成された分離酸化膜による
島領域部の断面図である。
(1)・・・・・・・・・・・・・・・・・・・・・・
・・・・・P形単結晶シリコン基板(2)・・・・・・
・・・・・・・・・・・・・・・・・・・・・N形埋込
層(3)・・・・・・・・・・・・・・・・・・・・−
・・・・・N形又はP形シリコン層(4)・・・・・・
・・・・・・・・・・・・・・・・・・・・・P形不純
物層(5)・・・・・・・・・・・・・・・・・・・・
・・・・・・・分離酸化膜(6)・・・・・・・・・・
・・・・・・・・・・・・・・・・・酸化シリコン膜(
7)・・・・・・・・・・・・・・・・・・・・・・・
・・・・窒化シリコン膜(8)・・・・・・・・・・・
・・・・・・・・・・・・・・・・酸化シリコン又は窒
化シリコン膜Figures 1a, b, and c are cross-sectional views of an embodiment of the present invention in the order of steps;
FIG. 2 is a cross-sectional view of an island region formed by an isolation oxide film formed by a conventional manufacturing method. (1)・・・・・・・・・・・・・・・・・・・・・
...P-type single crystal silicon substrate (2) ...
・・・・・・・・・・・・・・・・・・N-type buried layer (3)・・・・・・・・・・・・・・・・・・-
...N-type or P-type silicon layer (4)...
・・・・・・・・・・・・・・・・・・P-type impurity layer (5)・・・・・・・・・・・・・・・・・・・・・
......Isolation oxide film (6)...
・・・・・・・・・・・・・・・・・・ Silicon oxide film (
7)・・・・・・・・・・・・・・・・・・・・・
...Silicon nitride film (8)...
・・・・・・・・・・・・・・・ Silicon oxide or silicon nitride film
Claims (1)
形の埋め込み層を形成する工程と、前記埋め込み層の表
面を含むシリコン基板上に前記一導電形あるいは逆導電
形のシリコン層をエピタキシャル成長させる工程と、前
記埋め込み層の上に位置する部分の前記シリコン層を残
し、その周辺の同シリコン層を所定の深さまで異方的に
食刻する工程と、前記埋め込み層の上に位置する部分及
びその周辺食刻部からなる前記シリコン層の全面に酸化
又は窒化膜等の薄膜を形成する工程と、前記埋込層上の
シリコン層以外のシリコン層にのみ一導電形の不純物を
イオン注入により形成する工程と、前記薄膜を除去する
工程と、前記シリコン層の前記埋め込み層上の部分を島
領域で残し、他の部分を酸化物層に変換する工程とを含
むことを特徴とする半導体装置の製造方法。A step of forming a buried layer of an opposite conductivity type on a silicon substrate of one conductivity type consisting of P type or N type, and epitaxial growth of the silicon layer of one conductivity type or opposite conductivity type on the silicon substrate including the surface of the buried layer. a step of leaving a portion of the silicon layer located above the buried layer and anisotropically etching the silicon layer around it to a predetermined depth; and a step of etching the silicon layer around the silicon layer anisotropically to a predetermined depth; and a step of forming a thin film such as an oxide or nitride film on the entire surface of the silicon layer consisting of the etched portions thereof, and implanting impurities of one conductivity type only into the silicon layer other than the silicon layer on the buried layer by ion implantation. a step of forming the thin film; a step of removing the thin film; and a step of leaving a portion of the silicon layer on the buried layer as an island region and converting the other portion into an oxide layer. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11167085A JPS61269330A (en) | 1985-05-23 | 1985-05-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11167085A JPS61269330A (en) | 1985-05-23 | 1985-05-23 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61269330A true JPS61269330A (en) | 1986-11-28 |
Family
ID=14567201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11167085A Pending JPS61269330A (en) | 1985-05-23 | 1985-05-23 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61269330A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998055485A1 (en) * | 1997-06-04 | 1998-12-10 | Otsuka Kagaku Kabushiki Kaisha | Process for producing 3-alkenylcephem compounds |
-
1985
- 1985-05-23 JP JP11167085A patent/JPS61269330A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998055485A1 (en) * | 1997-06-04 | 1998-12-10 | Otsuka Kagaku Kabushiki Kaisha | Process for producing 3-alkenylcephem compounds |
US6417351B1 (en) | 1997-06-04 | 2002-07-09 | Otsuka Kagaku Kabushiki Kaisha | Process for producing 3-alkenylcephem compounds |
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