JPS6125251Y2 - - Google Patents
Info
- Publication number
- JPS6125251Y2 JPS6125251Y2 JP17985479U JP17985479U JPS6125251Y2 JP S6125251 Y2 JPS6125251 Y2 JP S6125251Y2 JP 17985479 U JP17985479 U JP 17985479U JP 17985479 U JP17985479 U JP 17985479U JP S6125251 Y2 JPS6125251 Y2 JP S6125251Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- ceramic
- flat plate
- present
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 10
- 238000005452 bending Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Connecting Device With Holders (AREA)
Description
【考案の詳細な説明】
本考案は通信機器および電子機器装置等に使用
するセラミツクIC（集積回路）パツケージの絶
縁カバーに関する。[Detailed Description of the Invention] The present invention relates to an insulating cover for a ceramic IC (integrated circuit) package used in communication equipment, electronic equipment, etc.
従来、第１図に示すように、基板４上に搭載さ
れたセラミツクICパツケージ７の表面を隣接基
板４′のリード線（図示していない）との絶縁
は、絶縁シート１を基板４および４′間に挿入す
ることにより行なわれている。このような従来構
造では、絶縁シート１により空気の流通が妨げら
れ、周囲の温度が上昇してシステムが誤動作した
り、基板実装部品の寿命が低下するという欠点が
ある。この結果、基板の実装間隔を大きくした
り、冷却フアンの性能を上げる必要が生じてい
る。 Conventionally, as shown in FIG. 1, the surface of a ceramic IC package 7 mounted on a substrate 4 is insulated from the lead wires (not shown) of an adjacent substrate 4' by using an insulating sheet 1 between the substrates 4 and 4. This is done by inserting it between '. Such a conventional structure has the disadvantage that the insulating sheet 1 obstructs air circulation, which increases the ambient temperature, causing system malfunctions and shortening the lifespan of board-mounted components. As a result, it has become necessary to increase the mounting distance between the boards and to improve the performance of the cooling fan.
本考案の目的は上述の欠点を除去したセラミツ
クICパツケージ用絶縁カバーを提供することに
ある。 The object of the present invention is to provide an insulating cover for a ceramic IC package that eliminates the above-mentioned drawbacks.
本考案の絶縁カバーは、ICを搭載し複数のピ
ンを有するセラミツクICパツケージの上面を被
覆するための透明性および絶縁性を有する平板部
と前記セラミツクICパツケージの両側面部と嵌
合するように前記平板部の両端を折り曲げ成形し
た曲げ部とから構成されている。 The insulating cover of the present invention has a transparent and insulating flat plate part for covering the top surface of a ceramic IC package having a plurality of pins on which an IC is mounted, and a flat plate part having transparency and insulating properties for covering the top surface of a ceramic IC package having a plurality of pins. It consists of a bent part formed by bending both ends of a flat plate part.
次に本考案について図面を参照して詳細に説明
する。 Next, the present invention will be explained in detail with reference to the drawings.
第２図は本考案の一実施例を示す斜視図であ
る。本実施例は、ICを搭載し複数のピンを有す
るセラミツクICパツケージの上面を被覆するた
めの透明性および絶縁性を有する平板部２と前記
セラミツクICパツケージの両側面部と嵌合する
ように前記平板部の両端を折り曲げ成形した曲げ
部３とから構成されている。 FIG. 2 is a perspective view showing an embodiment of the present invention. In this embodiment, a flat plate part 2 having transparency and insulation for covering the upper surface of a ceramic IC package having a plurality of pins on which an IC is mounted, and a flat plate part 2 which is fitted with both side surfaces of the ceramic IC package. It consists of a bent part 3 formed by bending both ends of the part.
第３図は本考案の絶縁カバー１０を取付けた
ICパツケージ７をソケツト６を介して基板４に
実装した状態を示す図である。参照数字９はIC
パツケージ７のピンである。 Figure 3 shows the insulation cover 10 of the present invention installed.
4 is a diagram showing a state in which an IC package 7 is mounted on a substrate 4 via a socket 6. FIG. Reference number 9 is IC
This is the pin of package 7.
第４図は本考案の絶縁カバー１０が取付けられ
たICパツケージ７を基板４にソケツト６を介し
て実装し、この基板４をフレーム５に取付けられ
たガイド８に挿入した状態を示す図である。 FIG. 4 is a diagram showing a state in which the IC package 7 to which the insulating cover 10 of the present invention is attached is mounted on the board 4 via the socket 6, and the board 4 is inserted into the guide 8 attached to the frame 5. .
このように、ICパツケージ単位の絶縁カバー
が設けられているため、基板実装部品に温度によ
る影響を与えない。また、絶縁カバー１０の取付
けは、曲げ部３をICパツケージ７の側面部に嵌
合させるだけで簡単に行なえるため絶縁の低コス
ト化が達成できる。 In this way, since an insulating cover is provided for each IC package, temperature does not affect the board-mounted components. Further, since the insulation cover 10 can be easily attached by simply fitting the bent portion 3 to the side surface of the IC package 7, the cost of insulation can be reduced.
以上、本考案には、セラミツクICパツケージ
の表面と隣接パツケージ基板のリード線との絶縁
維持が容易に行なえるという効果がある。 As described above, the present invention has the effect of easily maintaining insulation between the surface of the ceramic IC package and the lead wires of the adjacent package substrate.
第１図は従来例を示す図、第２図は本考案の一
実施例を示す図ならびに第３図および第４図は本
考案の絶縁カバーが取付けられたICパツケージ
を基板に実装した例を示す図である。
図において、１……絶縁シート、２……平板
部、３……曲げ部、４，４′……基板、５……フ
レーム、６……ソケツト、７……ICパツケー
ジ、８……ガイド、９……ピン、１０……絶縁カ
バー。
Fig. 1 shows a conventional example, Fig. 2 shows an embodiment of the present invention, and Figs. 3 and 4 show an example in which an IC package to which an insulating cover of the present invention is attached is mounted on a board. FIG. In the figure, 1... Insulating sheet, 2... Flat plate part, 3... Bent part, 4, 4'... Board, 5... Frame, 6... Socket, 7... IC package, 8... Guide, 9...Pin, 10...Insulation cover.
Claims (1)
面部に複数のピンを持ち対向する第３および第４
の側面部にピンを持たないセラミツクICパツケ
ージの上面を被覆するための透明性および絶縁性
を有する平板部と、前記セラミツクICパツケー
ジの前記第３および第４の側面部と嵌合するよう
に前記平板部の両端を折り曲げ成形した曲げ部と
から構成されたことを特徴とするセラミツクIC
パツケージ用絶縁カバー。 A third and a fourth side surface having an integrated circuit mounted thereon and having a plurality of pins on the first and second side surfaces facing each other and facing each other.
a transparent and insulating flat plate part for covering the upper surface of a ceramic IC package having no pins on the side surface thereof; A ceramic IC characterized by comprising a bent portion formed by bending both ends of a flat plate portion.
Insulating cover for package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17985479U JPS6125251Y2 (en) | 1979-12-25 | 1979-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17985479U JPS6125251Y2 (en) | 1979-12-25 | 1979-12-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5696636U JPS5696636U (en) | 1981-07-31 |
| JPS6125251Y2 true JPS6125251Y2 (en) | 1986-07-29 |
Family
ID=29690315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17985479U Expired JPS6125251Y2 (en) | 1979-12-25 | 1979-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6125251Y2 (en) |
-
1979
- 1979-12-25 JP JP17985479U patent/JPS6125251Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5696636U (en) | 1981-07-31 |
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