JPS61230379A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide large mutual conductance, and to enable ultraspeed operation by controlling two-element electrons formed on the interface between a first semiconductor layer and a second semiconductor layer by holes injected onto the interface between the second semiconductor and a third semiconductor from a fourth semiconductor layer. CONSTITUTION:A high-purity GaAs layer 2 in 1mum thickness is grown on a semi-insulating GaAs substrate 1, and a high-purity AlAs layer 8 in 20Angstrom thickness, an N-Al0.4Ga0.6As layer 9 containing an Si impurity of 1X10<18>cm<-3> and having 300Angstrom thickness and a P<+>-Al0.4Ga0.6As layer 10 containing a Be impurity of 3X10<19>cm<-3> and having 100Angstrom thickness are grown. Al is evaporated and patterned to form a gate electrode 5, unnecessary P<+>-Al0.4Ga0.6As is removed while the gate electrode 5 is used as a mask, and a source 6 and a drain electrode 7 consisting of AuGe/Au are evaporated and alloyed, thus completing a transistor. Accordingly, a semiconductor device, the degree of integration thereof is easily improved and the whole system thereof can be operated at superspeed, is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having high mutual conductance and capable of high-speed operation.

(Prior art and its problems) As an active semiconductor device that can be expected to operate at high speed, FF1T (Field
'Effect Tran*or) (For example, Japan Journal of Applied Physics (Jpn, J, Appl, Phys,
19 (1980) L255)). This is due to the hetero-interface of semiconductors with different electron affinities (e.g. A7xGa, -
xAs/GaAs), only the semiconductor with low electron affinity is doped with impurities, two-dimensional electrons are generated on the semiconductor side with high electron affinity, and the feature is that the high mobility of these two-dimensional electrons is utilized. However, from the point of view of the operating mechanism, the FBT is a type of MISFET (Metal
Insulator Sem1conductor P
Since it can be regarded as a Si MOSFET (Me
tal Oxide SemiconductorFB
T ) has similar advantages and disadvantages.

MIS-type FETs have a shorter process time than bipolar transistors, and a planar structure is easier to produce, making it easier to achieve higher integration. On the other hand, since the mutual conductance, which indicates the load driving ability of a device, decreases as the element size becomes smaller, it is not easy to increase the speed of high integration of bipolar transistors with high load driving ability.

FIG. 3 is a schematic cross-sectional view of a conventional FET using two-dimensional electrons. In FIG. 3, 1 is a semi-insulating semiconductor substrate, 2 is a first semiconductor layer with as few impurities as possible, and 3 is an n
An electron supply layer made of a semiconductor containing type impurities and having a lower electron affinity than the first semiconductor layer 2; 4 is the first semiconductor layer 2;
a two-dimensional electron gas formed at the interface between and the electron supply layer 3;
5 is a gate electrode that forms a Schottky junction with the electron supply layer 3; 6 is a source electrode that is alloyed with the electron supply layer 3 and is in electrical contact with the two-dimensional electron gas 4; and 7 is a drain electrode similar to 6. .

FIG. 4 is a diagram showing the band structure under the gate electrode of the FET shown in FIG. 3. In FIG. 4, parts with the same numbers as those in the third chestnut diagram have the same functions.

EC is the conduction band gap, E( is the Fermi level, and Ev is the edge of the filled band.

Next, we will introduce the conventional PET using two-dimensional electrons shown in Figure 3.
The operation will be explained. Here, in the FIT, the first semiconductor layer 2 is made of GaAs, and the electron supply layer 3 is made of n-type 11640m
6. It is assumed that the source is made of As, and that the source is on the order of zero, and a positive voltage is applied to the drain.

When the gate voltage (Vo) is Ov, n AlI3-3
Assuming that 0a6yAs is completely empty and has the band structure shown in Figure 4, AJ (1,3G
n − at the a6,7As/GaAs interface (GaAs side)
AJ6.3Ga6. A two-dimensional electron gas induced by the ionized donors in As is formed, and a drain current flows between the source and drain through the two-dimensional electron gas. Here, as the gate voltage increases in a negative direction, the two-dimensional electron gas under the gate decreases and the drain current decreases, and conversely, as the gate voltage increases in a positive direction, the two-dimensional electron gas under the gate decreases. The gas increases and the drain current increases.

The drain current is n-AJ63 depending on the gate voltage.
It is controlled through the capacitance of Ga(1?As).Therefore, the transconductance (,9m=change in drain current with respect to change in gate voltage) is Mo5p
It is written in the same way as In the area S = A, it becomes.

Here, 2 is the gate width, L is the gate length, and μ. is the two-dimensional electron mobility, C, is n AJ6.3 Ga6.1As
capacitance per unit area, VD is the drain voltage. In order to increase gm, it is necessary to increase zjμn)c and tvD and decrease LL, but μ. is almost constant, and considering integration, both Z and L become small and VD cannot be made large, so it is required to make itself large. C.

Increasing is n AJ6,3 Ga6.7 A
This corresponds to reducing the thickness of s, but this thickness cannot be made extremely thin for the following reason. n AJ
In order to make 6.5Ga6.7As thinner, n A
l. , 3 It is necessary to increase the impurity concentration of Gal1.7As in inverse proportion to the square of the thickness. This increase in impurity concentration lowers the gate breakdown voltage and increases gate leakage current, making it impossible for the transistor to operate normally.

In the case of this system, the limit is considered to be n = 5 x 10''cvt-'' and a thickness of about 200X, and the maximum value of mutual conductance is expected to be about 1000 m8 per unit n at a gate length of 1 μm or less. Since it is considered that a mutual conductance of several thousand m8 or more is required for an ultra-high-speed operating device, a value of this order is insufficient.

As mentioned above, conventional FIT using two-dimensional electrons
However, it is difficult to increase the field mutual conductance due to the same operating mechanism as MO8FB'l', and the performance is insufficient as an ultra-high-speed operating device.

(Objective of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device which has a very large mutual conductor/s and is capable of ultra-high speed operation, similar to a bipolar transistor.

(Structure of the Invention) According to the present invention, a first semiconductor layer with an extremely low impurity concentration;
a second semiconductor layer provided on the first semiconductor layer and having a smaller electron affinity than the first semiconductor layer; and a second semiconductor layer provided on the second semiconductor layer and having a smaller electron affinity than the first semiconductor layer. and a third semiconductor layer containing an n-type impurity and having a smaller sum of electron affinity and forbidden band width than the second semiconductor layer;
a fourth semiconductor layer provided on a part of the semiconductor layer and containing a high concentration of n-type impurities; and a gate provided on the fourth semiconductor layer and forming an ohmic junction with the fourth semiconductor layer. A semiconductor device is obtained that includes an electrode and a pair of electrodes that sandwich the gate electrode and form electrical contact with carriers present at the interface between a first semiconductor layer and a second semiconductor layer. .

(Principle of the Invention) The operating principle of the FET of the present invention is that two-dimensional electrons formed at the interface between the first semiconductor layer and the second semiconductor layer are transferred from the fourth semiconductor layer to the second semiconductor layer and the third semiconductor layer. It is controlled by holes injected into the interface with the semiconductor. The injected holes move toward the source electrode while inducing two-dimensional electrons one after another at the interface between the first semiconductor and the second semiconductor layer. The induced two-dimensional electrons are drawn into the drain at high speed by the drain electric field and become a drain current. Since the amount of injected holes increases exponentially with an increase in gate voltage, the drain current also increases exponentially.

Therefore, high transconductance is easily achieved by the FIT of the present invention.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention.

In Figure 1, the same numbers as in Figure 3.4 are numbered 3ν.
It is equivalent to Figure 4 and performs the same function.

8 is a second semiconductor layer having a smaller electron affinity than the first semiconductor layer 2; 9 is a second semiconductor layer having a smaller IT electron affinity than the first semiconductor layer 2 and a smaller sum of electron affinity and forbidden band width than the second semiconductor layer 8; A third semiconductor layer 10 containing n-type impurities is a fourth semiconductor layer containing n-type impurities at a high concentration.

Here, the E level of the second semiconductor layer 8 may be higher or lower than the Ev level of the first semiconductor layer 2. Also the second
Although the semiconductor layer 8 may contain an n-type impurity, it is better not to contain it in order to suppress gate leakage current.

Furthermore, the thickness of the second semiconductor layer 8 is preferably thinner, but holes are prevented from being completely lost due to the tunnel effect from the third semiconductor layer 9 to the first semiconductor layer 2. thickness is required. This thickness varies depending on the amount of EvO difference between the second semiconductor layer 8 and the third semiconductor layer 9, but is generally several ^.
~ several tens of C) is sufficient. The material of the fourth semiconductor layer 10 may be any material as long as it can inject holes into the third semiconductor layer 9, but from the viewpoint of increasing the injection efficiency, It is desirable to use the same material as the semiconductor layer 9 or a material with a larger sum of electron affinity and forbidden band width than the third semiconductor layer 9. As an example of realizing the structure of the present invention, the first semiconductor layer 2 is of high purity. QaAs1 The second semiconductor layer 8 has a thickness of about 20X, and the third semiconductor layer 9 has a thickness of about 5ooX, and the n-type impurity concentration is IXI.
Q"c+a-' n k16.B Ga6,1
Aa) The fourth semiconductor layer is P" Ga o with a thickness of about 100X and an n-type impurity concentration of I x 10"cm-' or more.
, s Ga6. There is one consisting of y As.

Hereinafter, the operation of this embodiment will be explained in detail using the above-mentioned materials for each semiconductor layer and with reference to FIG. 2, which is a diagram of the band structure.

FIG. 2 is a diagram showing the band structure under the gate electrode of the FET shown in FIG. 1. In FIG. 2, the same numbers as in FIG. 1+3#4 are equivalent to those in FIG. 1s3y4 and perform the same functions.

This band diagram represents a thermal equilibrium state, and shows a state in which a two-dimensional electron gas 4 is formed (dipleg mode) to facilitate understanding of the band structure. In an F'ET for ultra-high-speed operation, it is preferable to use a state (enhancement mode) in which no two-dimensional electron gas 4 is formed in a thermal equilibrium state.

When a positive voltage is applied to the gate electrode, 1)+AI0.3Ga
Q, 7 As layer 10 and n Alo, 3 Gao, y
The junction of the As layer 9 becomes forward biased. At this time, n
Since the A164 Ga6.7As layer 9 is almost completely depleted, the n A16.5Ga6 due to forward bias
．． From y ks layer 9, +-Aj6.3 Ga6. yA
The injection of electrons into the m-layer 10 is almost negligible. on the other hand,
p ” A164 Ga6.y As layer 1o to n
A164 Ga6. The injection of holes into the yAs layer 9 is significant. The injected holes are n A164 Ga64
n −A/6.3 Ga6,7 As via As layer 9
The holes reach the interface between the layer 9 and the A IAs layer 8, but because there is a barrier to holes there, they accumulate at this interface. Most of the accumulated holes are absorbed by the electric field between the source and gate. , 30a6. y It passes through the As layer 9 and moves to the source electrode side. In addition, a part of the electrons thermally crosses the AlA3 barrier or passes through the tunnel effect and enters the GaAs layer, and either moves to the source electrode or disappears by recombination with electrons. n
-A16,30a(1,y When holes accumulate at the As/AjAS interface, AJAs/G
Two-dimensional electrons are induced at the aAs interface. Since the induced two-dimensional electrons have high mobility, they instantly flow toward the drain side due to the electric field between the source and drain, and as a result, two-dimensional electrons are induced again by holes. Therefore, the holes injected from the p''-A1640a6.7 As layer 10 pass through a large number of 2 holes before being absorbed into the source electrode.
In order to induce dimensional electrons, the ratio (current amplification factor β) between the drain current and the gate current (mainly hole current) becomes extremely large. Also, +-Aj6.1 Gag,
y As layer 10 to n klo, B Ga6. yA
Since the number of holes injected into the s-layer 9 increases exponentially with the forward bias voltage (corresponding to the gate voltage), the mutual conductance also increases exponentially with an increase in gate voltage and becomes very large. Become.

As described above, the transistor according to the present invention is structurally similar to a conventional two-dimensional electron gas FIT, but its operating characteristics are similar to a bipolar transistor, and it has the advantages of high integration that conventional FETs have. It combines a suitable structure and the high transconductance of bipolar transistors.

To fabricate the transistor according to this example, first, MBE (Molecular Beam) was used as a crystal growth method.
Epitaxy), semi-insulating GaAs substrate 1
A high-purity GaAs layer 2 with a thickness of 1 μm is grown on top, followed by a high-purity AJAs layer 8 with a thickness of 20X, and a layer of I with a thickness of 300X.
n-A with 8i impurity of X 10” tlm-’
4,4Ga6.6As layer 9, thickness 100X, 3 × l
9 +) dlo containing Be impurity of Q"crn-"
, 4 Ga 6.6 As layer 10 was grown. Next A
I is vapor-deposited and patterned to form the gate electrode 5 and unnecessary p is used.
"AI6.4 GaO96S was removed using this as a mask, and AuGe/Au source and drain electrodes were deposited and alloyed to complete the transistor. As a result, the gate length was 0.5 μm between the gate and the source, and・In the case where the distance between drains is 0.5 μm, Ii
m = 5000m87wm (per 1m gate width), β
=200 characteristics were obtained.

In the above embodiments of the present invention, GaAs is used as the semiconductor material.
/AlGaAs is shown, but it is clear that other semiconductor materials (e.g. InGaAs/InP/InAJAs) may also be used.

The second to fourth semiconductor layers of the present invention do not need to have uniform composition or uniform doping. A short-period superlattice may be used, and the composition and doping may be varied in the thickness direction.

The short-period superlattice has the advantage that all the first to fourth semiconductor layers can be realized using two materials. Changes in composition are important in terms of protecting the surface layer (e.g. changing the third semiconductor layer to n
A16. @ Gradually changing from Ga6.7As to n GaAa). Changes in doping are important for increasing hole injection efficiency (low impurity concentration in the upper part of the third semiconductor layer). Further, the source and drain electrodes may be formed not only on the third semiconductor layer, but also on a portion where this layer is excavated, leaving the fourth semiconductor layer on.

(Effects of the Invention) As described above in detail, according to the present invention, a semiconductor device can be obtained that can be easily integrated during daytime operation and the entire system can be operated at ultra high speed, so the effects are great.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an embodiment of the present invention, FIG. 2 is a band structure diagram under the gate electrode of FIG. 1, FIG. 3 is a cross-sectional view of a conventional two-dimensional electron gas PET, and FIG. 4 is a diagram of a band structure under the gate electrode of FIG. 3. FIG. 1... Substrate 2... First semiconductor layer 3...
・Electron supply layer 4... Two-dimensional electron gas 5... Gate electrode 6... Source electrode 7... Drain electrode
8... Second semiconductor layer 9... Third semiconductor layer lO.
...Fourth semiconductor layer Figure 1 Figure 7

Claims (1)

[Claims] a first semiconductor layer with an extremely low impurity concentration; a second semiconductor layer provided on the first semiconductor layer and having a smaller electron affinity than the first semiconductor layer; and a second semiconductor layer provided on the second semiconductor layer. a third semiconductor layer containing an n-type impurity and having a smaller electron affinity than the first semiconductor layer and a sum of electron affinity and bandgap smaller than the second semiconductor layer; a fourth semiconductor layer provided in a portion thereof and containing a high concentration of P-type impurities; a gate electrode provided on the fourth semiconductor layer and forming an ohmic contact with the fourth semiconductor layer; A semiconductor device comprising: a carrier that is present at an interface between a first semiconductor layer and a second semiconductor layer, sandwiching an electrode; and a pair of electrodes that form an electrical contact.