JP2701568B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor (FET) using a quantum wire as a channel,
In particular, the present invention relates to an epitaxial layer structure capable of improving its performance.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional quantum wire FET. 4A is a device structural view, FIG. 4B is a device cross-sectional view on a plane (X1-X2-X3-X4) including the gate electrode 9, and FIG. 4C is a plane on the same plane. FIG. 4 is a sectional view of an inner superlattice layer 54. Such quantum wire FETs have been manufactured by Tsubaki et al.
nics Lett. ), Vol. 24, No. 20, 126
7, p. 1988. This FET includes a semi-insulating (SI) GaAs substrate 1, a non-doped GaAs layer 52 constituting a buffer layer, an in-plane superlattice layer 54, and an n-type AlGaAs layer 56 serving as an electron supply layer.

Here, as the GaAs substrate 1, [1-1]
Using a (001) GaAs substrate inclined by 1 ° in the [0] direction and using a metal organic chemical vapor deposition (MOCVD) method, a non-doped GaAs rod 54A and a non-doped AlAs rod 54B are alternately formed. A lattice layer 54 has been fabricated. On the electron supply layer 56, n
A cap layer 7 of type GaAs is formed, and a source electrode 8S and a drain electrode 8D are formed on the cap layer 7 by vapor deposition to make ohmic contact with the 2DEG channel layer. A gate electrode 9 is formed in a recess formed by removing the cap layer 7.

[0004]

FIG. 6 shows a potential profile in the direction from the substrate to the gate electrode of the conventional quantum wire FET shown in FIG. FIG. 6 (A),
(C) is on the line including the AlAs rod 54B (FIG. 5 (B)
Are the potential profiles at the time of low electron density and at the time of high electron density in Y1-Y2). FIGS. 5B and 5D show potential profiles at the time of low electron density and at the time of high electron density, respectively, on a line including the GaAs rod 54A (Z1-Z2 in FIG. 5B). At a drawing, E _C is the bottom, E _F of the conduction band is the Fermi level, n represents the electron density distribution. Under the condition of high electron density, as shown in FIGS. 6C and 6D, the electrons approach the vicinity of the hetero interface, so that the electrons are confined in the in-plane superlattice layer, and the one-dimensional electrons are contained in the GaAs rod 54A. Gas is formed. On the other hand, under the condition of low electron density, FIG.
As shown in (B), the confinement is reduced, and the electrons travel in the buffer layer 52.
Behaves as a dimensional gas.

As described above, the conventional quantum wire FET
Shows a good electron transport characteristic with a one-dimensional carrier at a high current, but shows a characteristic similar to a conventional two-dimensional electron gas FET (2DEGFET) at a low current. In general, when an FET is used as a high-frequency low-noise element, a high transfer conductance (g _m ) at a low current is indispensable. There was a problem that was not reflected.

The present invention provides an epitaxial layer structure that can maintain a one-dimensional confinement of carriers even at a low current and exhibit good electron transport characteristics by changing the epitaxial layer structure of a quantum wire. is there.

[0007]

According to the present invention, there is provided a field effect transistor comprising: an electron supply layer formed of a first semiconductor material doped with an n-type impurity on a semiconductor substrate; and an electron supply layer having an electron affinity higher than that of the first semiconductor material. An in-plane superlattice layer in which rods made of a large second semiconductor material and rods made of a third semiconductor material having an electron affinity smaller than that of the second semiconductor material are alternately arranged; A channel layer is sequentially stacked, and electrons travel in the longitudinal direction of the rod made of the second semiconductor material.

Further, in the above-described field effect transistor, an n-type impurity is doped on a side of the non-dove channel layer opposite to the in-plane superlattice layer, and the fifth semiconductor material has a smaller electron affinity than the fourth semiconductor material. An electron supply layer made of a semiconductor material is formed.

[0009]

In the conventional quantum wire FET, electrons leak into the buffer layer under the condition that the electron density is low, and the one-dimensional confinement cannot be maintained. In the present invention, an inverted 2DE GFET structure in which a non-doped channel layer is formed on an electron supply layer is used as a basic structure, and an in-plane superlattice layer is provided at an interface between the electron supply layer and the channel layer. With such a structure, as the electron density decreases, the center of gravity of the electron distribution approaches the electron supply layer, so that the electrons are confined in the in-plane superlattice layer and a one-dimensional electron gas is formed in the GaAs rod. In other words, the one-dimensional confinement becomes particularly strong at a low current, and good noise characteristics are exhibited with the improvement of the electron transport characteristics. On the other hand, under the condition of high electron density, many electrons are released from the in-plane superlattice layer and distributed two-dimensionally in the non-doped channel layer because the electron distribution moves to the gate side. Therefore, by applying an appropriate negative voltage to the gate, one-dimensional confinement of electrons is realized only under the gate, and in other parasitic regions, the electron acts as a two-dimensional gas in the upper non-doped channel layer. The increase in the parasitic resistance due to the thinning of the channel is also suppressed.

In addition, such a structure has a double hetero 2DEGF in which a channel layer is sandwiched between two electron supply layers.
It is also possible to apply to ET. In this case, an in-plane superlattice layer may be provided at the interface between the channel layer and the electron supply layer on the substrate side.

[0011]

FIG. 1 shows an element structure diagram of an FET according to a first embodiment of the present invention. FIG. 1A is a device structural view, FIG. 1B is a device cross-sectional view on a plane (X1-X2-X3-X4) including a gate electrode, and FIG. 1C is a view on the same plane. It is sectional drawing of an in-plane super lattice layer. On a semi-insulating GaAs substrate 1, a non-doped GaAs buffer layer 2, a non-doped Al
GaAs layer 3, n-type AlGaAs electron supply layer 4, in-plane superlattice layer 5 forming a first channel, undoped GaAs
A second channel layer made of s6 and an n-GaAs cap layer 7 are formed.

FIG. 2 shows a potential profile of the FET shown in FIG. 1 in the direction from the substrate to the gate electrode. FIGS. 2A and 2C show potential profiles at the time of low electron density and at the time of high electron density, respectively, on a line including the AlAs rod 5B (Y1-Y2 in FIG. 1B). FIGS. 7B and 7D show potential profiles at a low electron density and a high electron density, respectively, on a line including the GaAs rod 5A (Z1-Z2 in FIG. 1B).

Under the condition of high electron density, FIG.
As shown in (D), since the electrons approach the gate electrode side, the electrons are distributed toward the second channel layer 6, and a two-dimensional electron gas is formed. On the other hand, under the condition of low electron density, FIG.
As shown in (A) and (B), since the center of gravity of the electron distribution moves to the substrate side, the electrons are confined in the in-plane superlattice layer 5 and a one-dimensional electron gas is formed in the GaAs rod 5A. Thus, in the first embodiment according to the present invention, by applying an appropriate negative voltage to the gate, the electrons undergo one-dimensional confinement only under the gate, and behave as a two-dimensional electron gas in places where the electron density is high. . Therefore, while achieving high mobility and high drift speed associated with the one-dimensional confinement under the gate, 2
Since it behaves as a dimensional gas, an increase in parasitic resistance can be avoided.

Such an element is manufactured as follows. (001) GaAs inclined by 1 ° in the [1-10] direction
For example, a non-doped GaAs buffer layer 2 having a thickness of 1 μm and a non-doped A
The l _0.3 Ga _0.7 As layer 3 is sequentially grown to 500 Å (hereinafter referred to as A), and the n-type AlGaAs electron supply layer 4 (doping concentration 3 × 10 ¹⁸ / cm ³ ) is grown to 200 A. Here, since a substrate inclined by 1 ° is used, a step of 162 A period occurs on the crystal plane. By alternately growing AlAs and GaAs along this step, the in-plane superlattice layer (GaAs) ^0.75 (A
(As) ^0.25 5 is formed by 50A. Subsequently, the non-doped GaAs channel layer 6 is 200 A, and the n-type GaAs cap layer (doping concentration 5 × 10 ¹⁸ / cm ³ ) 7 is 5 A.
Grow sequentially to 00A.

After the source electrode 8S and the drain electrode 8D are formed on the n-type GaAs cap layer 7 by vapor deposition, ohmic contact is made by alloying. Here, a source electrode and a drain electrode are arranged on both ends of a semiconductor rod forming an in-plane superlattice. Further, a gate electrode 9 is formed in a recess formed by removing the n-type GaAs layer 7 by etching. Thus, the FET of FIG. 1 is completed.

FIG. 3 shows an element structure of an FET according to a second embodiment of the present invention. FIG. 1A is an element structure diagram, and FIG. 1B is an element cross-sectional view along a plane (X1-X2-X3-X4) including a gate electrode. Non-doped GaAs buffer layer 32, non-doped AlGaAs on semi-insulating GaAs substrate 1.
s layer 33, n-type AlGaAs electron supply layer 34, in-plane superlattice layer 35 forming a first channel, undoped GaAs
A second channel layer made of s36, an n-type AlGaAs electron supply layer 34 ', and an n-GaAs cap layer 7 are formed.

FIG. 4 shows a potential profile of the FET shown in FIG. 3 in the direction from the substrate to the gate electrode. FIGS. 4A and 4C show potential profiles at the time of low electron density and at the time of high electron density, respectively, on a line (Y1-Y2 in FIG. 3) including the AlAs rod 35B.
FIGS. 7B and 7D show potential profiles at the time of low electron density and at the time of high electron density, respectively, on a line (Z1-Z2 in FIG. 3) including the GaAs rod 35A. Under the condition of high electron density, as shown in FIGS.
Since the electrons approach the gate electrode side, the electrons are distributed toward the second channel layer 36, and a two-dimensional electron gas is formed. On the other hand, under the condition of low electron density, as shown in FIGS. 4A and 4B, since the center of gravity of the electron distribution moves to the substrate side, the electrons are confined in the in-plane superlattice 35 and the GaAs rod 35
A one-dimensional electron gas is formed in A. As described above, in the second embodiment according to the present invention, the same principle as that of the first embodiment is used to realize a high mobility and a high drift speed associated with the one-dimensional confinement under the gate, while maintaining the other parasitics. Since the region behaves as a two-dimensional gas, an increase in parasitic resistance can be avoided.

Such an element is manufactured as follows. (001) GaAs inclined by 1 ° in the [1-10] direction
The non-doped GaAs buffer layer 32 is 1 μm thick, the non-doped Al _0.3 Ga _0.7 As layer 33 is 500 A, and the n-type AlGa
As electron supply layer (doping concentration 3 × 10 ¹⁸ / cm ³ )
34 grows sequentially to 200A. Here, since a substrate inclined by 1 ° is used, a step of 162 A period occurs on the crystal plane. According to this step, AlAs
And GaAs are alternately grown to form an in-plane superlattice layer (GaAs) _0.75 (AlAs) _0.25 35 by 50A. Subsequently, the second channel layer 36 made of non-doped GaAs is formed at 150 A, and the n-type AlGaAs electron supply layer (doping concentration 3 × 10 ¹⁸ / cm ³ ) is formed at 250 A.
A, n-type GaAs cap layer (doping concentration 5 × 10
¹⁸ / cm ³ ) 7 is sequentially grown at 500A. n-type GaAs
After the source electrode 8S and the drain electrode 8D are formed on the s cap layer 7 by vapor deposition, an alloy process is performed.
Make ohmic contact. Here, a source electrode and a drain electrode are arranged on both ends of a semiconductor rod forming an in-plane superlattice. Further, a gate electrode 9 is formed in a recess formed by removing the n-type GaAs layer 7 by etching. Thus, the FET of FIG. 3 is completed.

In the above embodiment, AlGaAs / GaAs
Although the present invention has been described using the s-system, AlGaAs / I
nGaAs / GaAs strained lattice system and AlInAs / G
The present invention is also applicable to FETs using other material systems such as aInAs / InP system.

[0020]

As is apparent from the above detailed description,
According to the present invention, an in-plane superlattice layer is provided at the interface between the electron supply layer and the channel layer in the inverted 2DEGFET structure, or the in-plane superlattice layer is provided at the interface between the channel layer and the substrate-side electron supply layer in the double hetero 2DEGFET structure. By providing the inner superlattice layer, a good one-dimensional confinement can be realized at a low current, and an increase in the parasitic resistance due to the thinning of the channel can be avoided. Can be obtained.

[Brief description of the drawings]

FIG. 1 is an element structure diagram of a first embodiment of an FET according to the present invention.

FIG. 2 is a band profile diagram in the first embodiment.

FIG. 3 is a device structural view of a second embodiment of the FET according to the present invention.

FIG. 4 is a band profile diagram in the second embodiment.

FIG. 5 is an element structure diagram of a conventional FET.

FIG. 6 is a band profile diagram in a conventional example.

[Explanation of symbols]

1 S. I. GaAs substrate 2,6,32,36,52 i-GaAs layer 3,33 i-AlGaAs layer 4,34,34 ', 56 n-type AlGaAs electron supply layer 5,35,54 (AlAs) (GaAs) in-plane super Lattice layer 5A, 35A, 54A i-GaAs rod 5B, 35B, 54B i-AlAs rod 7 n-type GaAs cap layer 8S, 8D Ohmic electrode 9 Gate electrode

Claims (2)

(57) [Claims] 1. An electron supply layer made of at least a first semiconductor material doped with an n-type impurity on a semiconductor substrate, and a rod made of a second semiconductor material having an electron affinity higher than that of the first semiconductor material. And an in-plane superlattice layer in which rods made of a third semiconductor material having a smaller electron affinity than the second semiconductor material are alternately arranged, and a non-doped channel layer made of a fourth semiconductor material are sequentially stacked, A field effect transistor, wherein electrons travel in a longitudinal direction of the rod made of the second semiconductor material. 2. An electron supply layer comprising a fifth semiconductor material having a smaller electron affinity than the fourth semiconductor material and doped with an n-type impurity, on an opposite side of the non-doped channel layer from the in-plane superlattice layer. The field effect transistor according to claim 1, further comprising: