JPH04299870A - Field effect transistor - Google Patents

Abstract

PURPOSE:To maintain one-dimensional confinement of carriers at the time of low current, realize excellent electron conveyance characteristics, and restrain the increase of parasitic source resistance caused by thinning a channel. CONSTITUTION:In an FET structure wherein an undoped channel layer 6 is formed on an electron supply layer 4, a superlattice layer 5 in a surface is formed on the interface between the electron supply layer 4 and the undoped channel layer 6. Said superlattice layer 5 is constituted by alternately arranging rods 5A and rods 5B composed of materials of different electron affinity. Electrons are made to transit in the longitudinal direction of the rods. When a suitable negative voltage is applied to a gate 9, the electron distribution under the gate moves toward the substrate 1 side, and therefore is confined in the superlattice layer 5, so that one-dimensional gas is formed. On the other hand, in a parasitic region of high electron density, electrons distribute in the undoped layer 6 on the gate 9 side, so that the increase of parasitic resistance caused by thinning a channel also can be restrained.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to the structure of a field effect transistor (FET) using a quantum wire as a channel.
In particular, it relates to an epitaxial layer structure that makes it possible to improve its performance.

0002

2. Description of the Related Art FIG. 5 shows an example of a quantum wire FET according to the prior art. The same figure (A) is an element structure diagram, the same figure (B) is an element cross-sectional view on the plane (X1-X2-X3-X4) including the gate electrode 9, and the same figure (C) is a plane on the same plane. 5 is a cross-sectional view of an inner superlattice layer 54. FIG. Such a quantum wire FET was described in Electronics Letters by Tsubaki et al.
nics Lett. ), Volume 24, No. 20, 12
Reported on page 67, 1988. This FET is
A semi-insulating (S.I.) GaAs substrate 1, a non-doped GaAs layer 52 constituting a buffer layer, an in-plane superlattice layer 54,
It is composed of an n-type AlGaAs layer 56 as an electron supply layer.

Here, as the GaAs substrate 1, [1-10
] Using a (001) GaAs substrate tilted by 1° in the direction,
An in-plane superlattice layer 54 in which non-doped GaAs rods 54A and non-doped AlAs rods 54B are alternately formed is fabricated by using a metal organic chemical vapor deposition (MOCVD) method. n-type G on the electron supply layer 56
A cap layer 7 made of aAs is formed, and the cap layer 7
A source electrode 8S and a drain electrode 8D are formed thereon by vapor deposition and are in ohmic contact with the 2DEG channel layer. Furthermore, a gate electrode 9 is formed in the recessed portion formed by removing the cap layer 7.

0004

FIG. 6 shows a potential profile in the direction from the substrate to the gate electrode of the conventional quantum wire FET shown in FIG. Figure 6(A),(C
) is on the line including the AlAs rod 54B (Y in FIG. 5(B)
1-Y2) are the potential profiles at low electron density and high electron density, respectively. Figure (B), (
D) is a potential profile on the line including the GaAs rod 54A (Z1-Z2 in FIG. 5(B)) at low electron density and high electron density, respectively. In the figure, E
C is the bottom of the conduction band, EF is the Fermi level, and n
represents the electron density distribution. Under conditions of high electron density, Figure 6
As shown in (C) and (D), as the electrons approach the vicinity of the hetero interface, the electrons are confined in the in-plane superlattice layer, and the G
A one-dimensional electron gas is formed in the aAs rod 54A. On the other hand, under conditions of low electron density, as shown in FIGS. 6(A) and 6(B), the confinement decreases and electrons begin to travel within the buffer layer 52, causing them to behave as a two-dimensional gas. Become.

In this way, the quantum wire FET according to the prior art
exhibits good electron transport characteristics due to the one-dimensional carrier structure at high currents, but exhibits similar characteristics to conventional two-dimensional electron gas FETs (2DEGFETs) at low currents. Generally, when using a FET as a high-frequency, low-noise device, it is essential that the transfer conductance (gm) at low currents be high. There was a problem that it was not reflected.

The present invention provides an epitaxial layer structure that maintains one-dimensional carrier confinement even at low currents and exhibits good electron transport properties by modifying the epitaxial layer structure of quantum wires. be.

[0007]

[Means for Solving the Problems] A field effect transistor of the present invention includes an electron supply layer made of a first semiconductor material doped with an n-type impurity on a semiconductor substrate, and having an electron affinity higher than that of the first semiconductor material. an in-plane superlattice layer in which rods made of a large second semiconductor material and rods made of a third semiconductor material having a smaller electron affinity than the second semiconductor material are arranged alternately; a non-doped layer made of a fourth semiconductor material; The method is characterized in that channel layers are sequentially laminated to allow electrons to travel in the longitudinal direction of the rod made of the second semiconductor material.

Furthermore, in the above field effect transistor, an n-type impurity is doped on the side of the non-doped channel layer opposite to the in-plane superlattice layer, and a fifth semiconductor material having a lower electron affinity than the fourth semiconductor material is doped with an n-type impurity. It is characterized in that an electron supply layer made of a semiconductor material is formed.

[0009]

[Operation] In the conventional quantum wire FET, under conditions of low electron density, electrons seep into the buffer layer and one-dimensional confinement is no longer maintained. In the present invention, an inverted 2DEGFET structure in which a non-doped channel layer is formed on an electron supply layer is used as a basic structure, and an in-plane superlattice layer is provided at the interface between the electron supply layer and the channel layer. With this structure, as the electron density decreases, the center of gravity of the electron distribution approaches the electron supply layer, so electrons are confined in the in-plane superlattice layer and a one-dimensional electron gas is formed in the GaAs rod. That is, the one-dimensional confinement becomes particularly strong at low currents, and as the electron transport characteristics improve, good noise characteristics are exhibited. On the other hand, under high electron density conditions, the electron distribution moves toward the gate, so many electrons are released from the in-plane superlattice layer and become two-dimensionally distributed in the non-doped channel layer. Therefore, by applying an appropriate negative voltage to the gate, one-dimensional confinement of electrons can be achieved only under the gate, and the other parasitic regions behave as a two-dimensional gas in the upper non-doped channel layer.
An increase in parasitic resistance due to channel thinning is also suppressed.

[0010] Also, such a structure is a double hetero 2DEGF in which the channel layer is sandwiched between two electron supply layers.
It is also possible to apply it to ET. In this case, an in-plane superlattice layer may be provided at the interface between the channel layer and the electron supply layer on the substrate side.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an element structure diagram of an FET according to a first embodiment of the present invention. Figure (A) is an element structure diagram, Figure (B) is a cross-sectional view of the element in the plane (X1-X2-X3-X4) including the gate electrode, and Figure (c) is a diagram of the element in the same plane. FIG. 3 is a cross-sectional view of an in-plane superlattice layer. A non-doped GaAs buffer layer 2 and a non-doped AlG layer are formed on a semi-insulating GaAs substrate 1.
aAs layer 3, n-type AlGaAs electron supply layer 4, in-plane superlattice layer 5 forming the first channel, non-doped GaAs
a second channel layer consisting of 6, an n-GaAs cap layer 7;
is formed.

FIG. 2 shows a potential profile in the direction from the substrate to the gate electrode of the FET shown in FIG. FIGS. 2A and 2C are potential profiles at low electron density and high electron density, respectively, on the line including the AlAs rod 5B (Y1-Y2 in FIG. 1B). 1B and 1D are potential profiles at low electron density and high electron density, respectively, on the line including the GaAs rod 5A (Z1-Z2 in FIG. 1B).

Under the condition of high electron density, FIGS. 2(C) and (D
), as the electrons approach the gate electrode side,
The electrons are distributed towards the second channel layer 6 and a two-dimensional electron gas is formed. On the other hand, under conditions of low electron density, Figure 2 (A
) and (B), the center of gravity of the electron distribution moves toward the substrate, so the electrons are confined in the in-plane superlattice layer 5 and the G
A one-dimensional electron gas is formed in the aAs rod 5A. In this way, in the first embodiment of the present invention, by applying an appropriate negative voltage to the gate, electrons undergo one-dimensional confinement only under the gate, and behave as a two-dimensional electron gas in areas with high electron density. . Therefore, while realizing high mobility and high drift speed associated with one-dimensional confinement under the gate, the other parasitic regions behave as a two-dimensional gas, and an increase in parasitic resistance can also be avoided.

[0014] Such an element is manufactured as follows. (001) GaAs tilted by 1° in the [1-10] direction
For example, a non-doped GaAs buffer layer 2 with a thickness of 1 μm and a non-doped Al layer is formed on the substrate 1 by the MOCVD growth method.
The thickness of the 0.3 Ga0.7 As layer 3 is 500 angstroms (hereinafter referred to as A), and the thickness of the n-type AlGaAs electron supply layer 4 (doping concentration 3 x 1018/cm3) is 200 angstroms.
Grows sequentially to A. Here, since a substrate tilted by 1° is used, steps with a period of 162A occur on the crystal plane. Along this step, an in-plane superlattice layer (GaAs) is grown by growing AlAs and GaAs alternately.
)0.75 (AlAs)0.255 is formed by 50A. Subsequently, a non-doped GaAs channel layer 6 was formed with a thickness of 200 nm.
A, n-type GaAs cap layer (doping concentration 5×10
18/cm3)7 grows sequentially to 500A.

A source electrode 8S and a drain electrode 8D are formed on the n-type GaAs cap layer 7 by vapor deposition, and then ohmic contact is established by alloying. here,
A source electrode and a drain electrode are respectively disposed on both ends of the semiconductor rod forming an in-plane superlattice. Furthermore,
A gate electrode 9 is formed in the recessed portion formed by etching away the n-type GaAs layer 7. Thus, the FE in Figure 1
T is completed.

FIG. 3 shows the element structure of an FET according to a second embodiment of the present invention. 3A is a device structure diagram, and FIG. 1B is a sectional view of the device in a plane (X1-X2-X3-X4) including the gate electrode. A non-doped GaAs buffer layer 32 and a non-doped AlGaA layer are formed on a semi-insulating GaAs substrate 1.
s layer 33, n-type AlGaAs electron supply layer 34, in-plane superlattice layer 35 forming the first channel, non-doped GaA
A second channel layer made of s36, an n-type AlGaAs electron supply layer 34', and an n-GaAs cap layer 7 are formed.

FIG. 4 shows a potential profile in the direction from the substrate to the gate electrode of the FET shown in FIG. FIGS. 4A and 4C are potential profiles at low electron density and high electron density, respectively, on the line including the AlAs rod 35B (Y1-Y2 in FIG. 3). 3B and 3D are potential profiles at low electron density and high electron density, respectively, on the line including the GaAs rod 35A (Z1-Z2 in FIG. 3). Under high electron density conditions, as shown in Figures 4(C) and (D),
Since the electrons approach the gate electrode side, the electrons are distributed toward the second channel layer 36, and a two-dimensional electron gas is formed. On the other hand, under low electron density conditions, as shown in FIGS. 4A and 4B, the center of gravity of the electron distribution moves toward the substrate, so electrons are confined in the in-plane superlattice 35 and the GaAs rods 35
A one-dimensional electron gas is formed in A. In this way, the second embodiment of the present invention uses the same principle as the first embodiment to achieve high mobility and high drift speed associated with one-dimensional confinement under the gate, while eliminating other parasitic Since it behaves as a two-dimensional gas in the region, an increase in parasitic resistance can also be avoided.

Such an element is manufactured as follows. (001) GaAs tilted by 1° in the [1-10] direction
For example, a non-doped GaAs buffer layer 32 with a thickness of 1 μm and a non-doped A
l0.3 Ga0.7 As layer 33 at 500A, n-type A
lGaAs electron supply layer (doping concentration 3×1018/
cm3)34 grows sequentially to 200A. Here, 1
Since we use a substrate tilted by 1°, there is a 1°
A step of 62 A periods occurs. By growing AlAs and GaAs alternately along this step,
In-plane superlattice layer (GaAs) 0.75 (AlAs) 0.2
535 is formed by 50A. Continuing, non-doped Ga
The second channel layer 36 made of As is made of 150A, n-type Al.
GaAs electron supply layer (doping concentration 3×1018/c
m3) 34' to 250A, n-type GaAs cap layer (
Doping concentration 5×1018/cm3)7 at 500A
grow sequentially. After forming a source electrode 8S and a drain electrode 8D on the n-type GaAs cap layer 7 by vapor deposition, ohmic contact is established by alloying. Here, a source electrode and a drain electrode are arranged on both ends of the semiconductor rod forming an in-plane superlattice. Further, a gate electrode 9 is formed in the recessed portion formed by etching away the n-type GaAs layer 7. In this way, the FET shown in FIG. 3 is completed.

In the above embodiments, AlGaAs/GaA
Although the present invention has been explained using the s system, AlGaAs/I
nGaAs/GaAs strained lattice system and AlInAs/G
It is also applicable to FETs using other material systems such as aInAs/InP system.

[0020]

[Effect of the invention] As is clear from the above detailed explanation,
According to the present invention, an in-plane superlattice layer is provided at the interface between the electron supply layer and the channel layer in an inverted 2DEGFET structure, or an in-plane superlattice layer is provided at the interface between the channel layer and the substrate side electron supply layer in the double hetero 2DEGFET structure. By providing an inner superlattice layer, it is possible to achieve good one-dimensional refinement at low currents, and it is also possible to avoid an increase in parasitic resistance due to thinning of the channel, making it an ideal FET as a high-frequency, low-noise device. can be obtained.

[Brief explanation of drawings]

FIG. 1 is an element structure diagram of a first embodiment of an FET according to the present invention.

FIG. 2 is a band profile diagram in the first embodiment.

FIG. 3 is an element structure diagram of a second embodiment of the FET according to the present invention.

FIG. 4 is a band profile diagram in a second embodiment.

FIG. 5 is an element structure diagram of an FET according to the prior art.

FIG. 6 is a band profile diagram in a conventional example.

[Explanation of symbols]

1 S. I. GaAs substrate 2, 6, 32, 36, 52 i-GaAs layer 3, 33
i-AlGaAs layer 4, 34, 34', 56 n-type AlGaAs electron supply layer 5, 35, 54 (AlAs) (GaAs) in-plane superlattice layer 5A, 35A, 54A i-GaAs rod 5B, 3
5B, 54B i-AlAs rod 7 n-type GaA
s cap layer 8S, 8D ohmic electrode 9 gate electrode

Claims (2)

[Claims] 1. An electron supply layer made of a first semiconductor material doped with at least an n-type impurity on a semiconductor substrate, and a rod made of a second semiconductor material having a higher electron affinity than the first semiconductor material. and an in-plane superlattice layer in which rods made of a third semiconductor material having a lower electron affinity than the second semiconductor material are arranged alternately, and a non-doped channel layer made of a fourth semiconductor material are sequentially stacked, A field effect transistor characterized in that electrons are caused to travel in the longitudinal direction of the rod made of the second semiconductor material. 2. An electron supply layer made of a fifth semiconductor material having a lower electron affinity than the fourth semiconductor material and doped with an n-type impurity, on the side of the non-doped channel layer opposite to the in-plane superlattice layer. 2. The field effect transistor according to claim 1, comprising: