JPH0645368A - Heterojunction semiconductor device - Google Patents
Heterojunction semiconductor deviceInfo
- Publication number
- JPH0645368A JPH0645368A JP19735092A JP19735092A JPH0645368A JP H0645368 A JPH0645368 A JP H0645368A JP 19735092 A JP19735092 A JP 19735092A JP 19735092 A JP19735092 A JP 19735092A JP H0645368 A JPH0645368 A JP H0645368A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- doped
- gaas
- spacer
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高電子移動度トランジ
スタ等のヘテロ接合を備えた半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a heterojunction such as a high electron mobility transistor.
【０００２】[0002]
【従来の技術】ノンドープのＧａＡｓ層上にｎ型のＡｌ
ＧａＡｓ層を形成したときにそのヘテロ接合界面に発生
する高い移動度の２次元電子ガスの濃度をゲート電極に
より制御する高電子移動度トランジスタ（以下、ＨＥＭ
Ｔという。）が考案されている。このＨＥＭＴは、高速
スイッチング素子、マイクロ波素子として有望なので、
その特性をさらに向上させるために構造面、および材料
面から研究が盛んに行われている。2. Description of the Related Art n-type Al is formed on a non-doped GaAs layer.
A high electron mobility transistor (hereinafter referred to as HEM) that controls the concentration of a high mobility two-dimensional electron gas generated at the heterojunction interface when the GaAs layer is formed by a gate electrode.
T. ) Has been devised. Since this HEMT is promising as a high-speed switching element and a microwave element,
In order to further improve the characteristics, research is actively conducted from the structural and material viewpoints.
【０００３】まず、構造面では、ＧａＡｓとＡｌx Ｇａ
1-x Ａｓとの間にＩｎy Ｇａ1-y Ａｓを入れたヘテロ構
造を有するｎ−ＡｌＧａＡｓ／ＩｎＧａＡｓ／ＧａＡｓ
系Ｐｓｅｕｄｏ ｍｏｒｐｈｉｃ ＨＥＭＴがある。従
来のＨＥＭＴではｘ＝０．３近傍を用いるためにＤＸセ
ンターが多量に存在し、素子特性に悪影響を及ぼしてい
たが、このＨＥＭＴではｘ＝０．１５、ｙ＝０．１５程
度を用いるためＤＸセンターの影響は少なく、かつＡｌ
ＧａＡｓとＩｎＧａＡｓとの間に十分大きなコンダクシ
ョンバンドオフセットがあるため、デバイス動作に必要
なキャリアが確保される。また、チャネルとなるＩｎＧ
ａＡｓはＧａＡｓと格子不整合であるが、その厚みを臨
界膜厚以下とするため、転位のないｓｔｒａｉｎｅｄ
ｌａｙｅｒとなり、従来のＧａＡｓをチャネルとしたＨ
ＥＭＴよりも電子輸送特性が向上する。First, in terms of structure, GaAs and Al x Ga are used.
N-AlGaAs / InGaAs / GaAs having a heterostructure in which In y Ga 1-y As is inserted between 1-x As and
There is a system Pseudo morphic HEMT. In the conventional HEMT, a large amount of DX centers are present because x = 0.3 is used, which adversely affects the device characteristics. However, in this HEMT, x = 0.15 and y = 0.15 are used. DX center is less affected and Al
Since there is a sufficiently large conduction band offset between GaAs and InGaAs, carriers necessary for device operation are secured. Also, InG that becomes a channel
aAs has a lattice mismatch with GaAs, but since its thickness is set to the critical film thickness or less, it is strained without dislocations.
It becomes a layer, and H using the conventional GaAs as a channel
Electron transport characteristics are improved as compared with EMT.
【０００４】次に、材料面では、ＧａＡｓ基板に替わっ
てＩｎＰ基板を用い、ＩｎＰに格子整合したＩｎＧａＡ
ｓとｎ型のＩｎＡｌＡｓからなるヘテロ構造を有するｎ
−ＩｎＡｌＡｓ／ＩｎＧａＡｓ系ＨＥＭＴがある。この
系は、従来のＨＥＭＴよりもそれぞれ高い電子移動度、
電子飽和速度および２次元電子ガス濃度を示すため、よ
り高性能なＨＥＭＴを実現できるものとして注目されて
いる。また、従来からキャリア供給層として用いられて
きたｎ型ＡｌＧａＡｓの替わりにｎ型ＩｎＧａＰを用い
てヘテロ構造を形成したｎ−ＩｎＧａＰ／ＧａＡｓ系Ｈ
ＥＭＴもある。ｎ型Ｉｎ0.49Ｇａ0.51ＰはＧａＡｓに格
子整合し、ＡｌＧａＡｓで問題となるＤＸセンターは存
在しない。またＧａＡｓ系に対して選択的にエッチング
が可能なため、プロセス上も優れた材料である。ＧａＡ
ｓとのコンダクションバンドオフセットが比較的小さい
ため、ＧａＡｓとＩｎＧａＰとの間にＩｎＧａＡｓを入
れたヘテロ構造を有するｎ−ＩｎＧａＰ／ＩｎＧａＡｓ
／ＧａＡｓ系Ｐｓｅｕｄｏｍｏｒｐｈｉｃ ＨＥＭＴも
高性能なＨＥＭＴとして有望視されている。Next, in terms of materials, an InP substrate was used instead of the GaAs substrate, and InGaA lattice-matched to InP was used.
n having a heterostructure composed of s and n-type InAlAs
There is an InAlAs / InGaAs HEMT. This system has higher electron mobility than conventional HEMTs,
Since it shows the electron saturation velocity and the two-dimensional electron gas concentration, it is attracting attention as a device that can realize a higher performance HEMT. Further, an n-InGaP / GaAs system H in which a heterostructure is formed by using n-type InGaP instead of n-type AlGaAs which has been conventionally used as a carrier supply layer.
There is also EMT. The n-type In 0.49 Ga 0.51 P is lattice-matched to GaAs, and there is no DX center which is a problem in AlGaAs. In addition, since it can be selectively etched with respect to GaAs, it is an excellent material in terms of process. GaA
n-InGaP / InGaAs having a heterostructure in which InGaAs is inserted between GaAs and InGaP because the conduction band offset with s is relatively small.
The / GaAs-based Pseudomorphic HEMT is also regarded as a promising high-performance HEMT.
【０００５】ところで、このように接合面の垂直方向に
運動の自由度のない実質的には２次元チャネルが形成さ
れた構造のＨＥＭＴの動作にとって、ヘテロ接合界面近
傍の結晶性の良否、急峻性は非常に重要である。By the way, for the operation of the HEMT having a structure in which a substantially two-dimensional channel is formed in which there is no freedom of movement in the direction perpendicular to the junction surface, the crystallinity in the vicinity of the heterojunction interface and the steepness are high. Is very important.
【０００６】ＩｎＧａＰをキャリア供給層に用いたｎ−
ＩｎＧａＰ／ＩｎＧａＡｓ／ＧａＡｓ系Ｐｓｅｕｄｏ
ｍｏｒｐｈｉｃ ＨＥＭＴを第１の従来例として図３に
示す。図３において、１は半絶縁性ＧａＡｓ基板、２は
膜厚が５００ｎｍのノンドープＧａＡｓバッファ層、３
は膜厚が１５ｎｍのノンドープＩｎ0.2 Ｇａ0.8 Ａｓチ
ャネル層、５は膜厚が５ｎｍのノンドープＩｎx Ｇａ
1-x Ｐスペーサ層、６は膜厚が３５ｎｍのｎ−Ｉｎx Ｇ
ａ1-x Ｐキャリア供給層、７は膜厚が１０ｎｍのＩｎx
Ｇａ1-x Ｐノンドープ層、８は膜厚が１０ｎｍのＧａＡ
ｓコンタクト層であり、５，６，７の各層はＧａＡｓに
対して格子整合する条件であるｘ＝０．４９、またはシ
ョトキバリアハイトを大きくしかつ２次元電子ガス濃度
を高めるためにｘ＝０．４５程度で形成されている。N- using InGaP for the carrier supply layer
InGaP / InGaAs / GaAs Pseudo
A morphic HEMT is shown in FIG. 3 as a first conventional example. In FIG. 3, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs buffer layer having a thickness of 500 nm, 3
Is a non-doped In 0.2 Ga 0.8 As channel layer with a thickness of 15 nm, and 5 is a non-doped In x Ga with a thickness of 5 nm.
1-x P spacer layer, 6 is n-In x G with a thickness of 35 nm
a 1-x P carrier supply layer, 7 is 10 nm thick In x
Ga 1-x P non - doped layer, 8 is GaA with a thickness of 10 nm
The s-contact layer, which is a condition for lattice matching with GaAs, is x = 0.49, or x = 0.49 in order to increase the Schottky barrier height and increase the two-dimensional electron gas concentration. It is formed at about 0.45.
【０００７】この構造によれば、キャリア供給層６から
チャネル層３へ電子が供給される結果、該チャネル層３
に高移動度の２次元電子ガスが形成される。According to this structure, electrons are supplied from the carrier supply layer 6 to the channel layer 3 and, as a result, the channel layer 3
A two-dimensional electron gas with high mobility is formed at the surface.
【０００８】同じくＩｎＧａＰをキャリア供給層に用い
たｎ−ＩｎＧａＰ／ＩｎＧａＡｓ／ＧａＡｓ系Ｐｓｅｕ
ｄｏ ｍｏｒｐｈｉｃ 逆ＨＥＭＴを第２の従来例とし
て図４に示す。図４において、１は半絶縁性ＧａＡｓ基
板、９は膜厚が１００ｎｍのノンドープＧａＡｓバッフ
ァ層、１０は膜厚が２００ｎｍのノンドープＩｎx Ｇａ
1-x Ｐバッファ層、１１は膜厚が３５ｎｍのｎ−Ｉｎx
Ｇａ1-x Ｐキャリア供給層、１２は膜厚が５ｎｍのノン
ドープＩｎx Ｇａ1-x Ｐスペーサ層、１４は膜厚が１５
ｎｍのノンドープＩｎ0.2 Ｇａ0.8 Ａｓチャネル層、１
５は膜厚が１００ｎｍ程度のＧａＡｓノンドープ層、１
６は膜厚が１０ｎｍのＧａＡｓコンタクト層であり、１
０，１１，１２の各層はＧａＡｓに対して格子整合する
条件であるｘ＝０．４９で形成されている。Similarly, n-InGaP / InGaAs / GaAs system Pseu using InGaP for the carrier supply layer is used.
A do morphic reverse HEMT is shown in FIG. 4 as a second conventional example. In FIG. 4, 1 is a semi-insulating GaAs substrate, 9 is a non-doped GaAs buffer layer having a film thickness of 100 nm, and 10 is non-doped In x Ga having a film thickness of 200 nm.
1-x P buffer layer, 11 is n-In x with a thickness of 35 nm
Ga 1-x P carrier supply layer, 12 is a non-doped In x Ga 1-x P spacer layer having a thickness of 5 nm, and 14 is a thickness of 15
nm non-doped In 0.2 Ga 0.8 As channel layer, 1
5 is a GaAs non-doped layer having a thickness of about 100 nm, 1
6 is a GaAs contact layer having a thickness of 10 nm, and 1
Each of the layers 0, 11, and 12 is formed under the condition of x = 0.49, which is a condition for lattice matching with GaAs.
【０００９】この構造の場合でも、キャリア供給層１１
からチャネル層１４へ電子が供給される結果、該チャネ
ル層１４に高移動度の２次元電子ガスが形成される。Even in the case of this structure, the carrier supply layer 11
As a result of the electrons being supplied to the channel layer 14 from this, a two-dimensional electron gas with high mobility is formed in the channel layer 14.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら上記のよ
うな構造を例えば分子線エピタキシ法で形成する場合、
まず図３に示す第１の従来例では、チャネル層３の形成
後にスペーサ層５を形成する際に、チャンバー内に残留
しやすいＡｓがスペーサ層５に取り込まれるためＩｎＧ
ａＡｓＰ混晶からなる遷移領域１７が形成される結果、
急峻なＩｎＧａＡｓ／ＩｎＧａＰヘテロ接合が得られな
い。また、図４に示す第２の従来例では、スペーサ層１
２の形成後にチャネル層１４を形成する際に、チャンバ
ー内に残留しやすいＰがチャネル層１４に取り込まれる
ためＩｎＧａＡｓＰ混晶からなる遷移領域１８が形成さ
れる結果、急峻なＩｎＧａＰ／ＩｎＧａＡｓヘテロ接合
がやはり得られない。また、ＩｎＧａＡｓとＩｎＧａＰ
ではＩｎとＧａのビーム強度比が異なるため、成長中断
を余儀なくされることとなる。この成長中断の間チャネ
ル近傍に炭素が付着するため、あるいはＡｓやＰの再蒸
発が起こるため清浄な界面が得られない。これらのこと
は有機金属気相成長法においてもあてはまることであ
る。以上の理由から十分に高い移動度が得られないとい
う問題点を有していた。However, when the above-mentioned structure is formed by, for example, the molecular beam epitaxy method,
First, in the first conventional example shown in FIG. 3, when the spacer layer 5 is formed after the channel layer 3 is formed, As, which easily remains in the chamber, is taken into the spacer layer 5, and thus InG is used.
As a result of the formation of the transition region 17 composed of an aAsP mixed crystal,
A steep InGaAs / InGaP heterojunction cannot be obtained. In the second conventional example shown in FIG. 4, the spacer layer 1
When the channel layer 14 is formed after forming 2, the transition region 18 made of InGaAsP mixed crystal is formed because P, which tends to remain in the chamber, is taken into the channel layer 14. As a result, a steep InGaP / InGaAs heterojunction is formed. After all it cannot be obtained. InGaAs and InGaP
However, since the beam intensity ratio of In and Ga is different, the growth must be interrupted. During this growth interruption, carbon adheres to the vicinity of the channel, or As and P are re-evaporated, a clean interface cannot be obtained. These are also applicable to the metal organic chemical vapor deposition method. For the above reasons, there is a problem that a sufficiently high mobility cannot be obtained.
【００１１】本発明の目的は、ヘテロ接合界面に発生す
る２次元電子ガスの移動度を高めることにある。An object of the present invention is to increase the mobility of the two-dimensional electron gas generated at the heterojunction interface.
【００１２】[0012]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、ＩｎＧａＡｓチャネル層に対して同じＡ
ｓ系材料であるＡｌＧａＡｓからなるスペーサ層を相接
して形成することにより、急峻なヘテロ接合を実現する
こととしたものである。SUMMARY OF THE INVENTION To achieve the above object, the present invention uses the same A for InGaAs channel layers.
By forming spacer layers made of AlGaAs, which is an s-based material, in contact with each other, a steep heterojunction is realized.
【００１３】具体的には、請求項１の発明は、ＧａＡｓ
基板上に形成されたノンドープのＩｎＧａＡｓからなる
チャネル層と、該チャネル層に接するように形成された
ノンドープのＡｌＧａＡｓからなる最下層を少なくとも
有するスペーサ層と、該スペーサ層上に形成されたｎ型
のＩｎＧａＰからなるキャリア供給層とを備えた構成を
採用したものである。Specifically, the invention of claim 1 is GaAs
A channel layer made of non-doped InGaAs formed on the substrate, a spacer layer having at least a bottom layer made of non-doped AlGaAs formed in contact with the channel layer, and an n-type formed on the spacer layer. A structure including a carrier supply layer made of InGaP is adopted.
【００１４】また、請求項２の発明は、ＧａＡｓ基板上
に形成されたｎ型のＩｎＧａＰからなるキャリア供給層
と、ノンドープのＡｌＧａＡｓからなる最上層を少なく
とも有するように前記キャリア供給層上に形成されたス
ペーサ層と、該スペーサ層中のノンドープのＡｌＧａＡ
ｓからなる最上層に接するように形成されたノンドープ
のＩｎＧａＡｓからなるチャネル層とを備えた構成を採
用したものである。According to a second aspect of the present invention, the carrier supply layer is formed on the GaAs substrate so as to have at least a carrier supply layer made of n-type InGaP and an uppermost layer made of non-doped AlGaAs. Spacer layer and undoped AlGaA in the spacer layer
and a channel layer made of non-doped InGaAs formed so as to be in contact with the uppermost layer made of s.
【００１５】[0015]
【作用】本発明によれば、上記した構造によって、電子
が閉じこめられかつ電子が走行するチャネル層とスペー
サ層とのヘテロ接合が急峻かつ清浄な接合となるので、
十分に高い移動度が得られることになる。According to the present invention, due to the above structure, the heterojunction between the channel layer in which electrons are confined and the electrons travel and the spacer layer is a sharp and clean junction.
A sufficiently high mobility will be obtained.
【００１６】[0016]
【実施例】以下、本発明の２つの実施例に係るヘテロ接
合半導体装置について、図面を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Heterojunction semiconductor devices according to two embodiments of the present invention will be described below with reference to the drawings.
【００１７】図１は、本発明の第１の実施例に係るヘテ
ロ接合半導体装置の断面構造を示すものであって、前記
第１の従来例（図３）に対応するものである。図１にお
いて、１は半絶縁性ＧａＡｓ基板、２は膜厚が５００ｎ
ｍのノンドープＧａＡｓバッファ層、３は膜厚が１５ｎ
ｍのノンドープＩｎ0.2 Ｇａ0.8 Ａｓチャネル層、４は
本発明の中心となる膜厚が３ｎｍのノンドープＡｌ0.2
Ｇａ0.8 Ａｓからなる第１のスペーサ層、５は膜厚が２
ｎｍのノンドープＩｎx Ｇａ1-x Ｐからなる第２のスペ
ーサ層、６は膜厚が３５ｎｍでｎ型不純物を２×１０18
ｃｍ-3程度ドープしたｎ−Ｉｎx Ｇａ1-x Ｐキャリア供
給層、７は膜厚が１０ｎｍのＩｎx Ｇａ1-x Ｐノンドー
プ層、８は膜厚が１０ｎｍでｎ型不純物を５×１０18ｃ
ｍ-3程度ドープしたＧａＡｓコンタクト層であり、５，
６，７の各層はＧａＡｓに対して格子整合する条件であ
るｘ＝０．４９またはｘ＝０．４５で形成されている。FIG. 1 shows a sectional structure of a heterojunction semiconductor device according to a first embodiment of the present invention, and corresponds to the first conventional example (FIG. 3). In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is a film thickness of 500 n.
m non-doped GaAs buffer layer 3 has a thickness of 15 n
m is a non-doped In 0.2 Ga 0.8 As channel layer, and 4 is a non-doped Al 0.2 having a thickness of 3 nm which is the center of the present invention.
The first spacer layer 5 made of Ga 0.8 As has a film thickness of 2
second spacer layer made of non-doped In x Ga 1-x P of 5 nm, and 6 has a film thickness of 35 nm and 2 × 10 18 n-type impurities.
cm −3 doped n-In x Ga 1-x P carrier supply layer, 7 a 10 nm thick In x Ga 1-x P non - doped layer, 8 a 10 nm thick n-type impurity 5 × 10 18 c
It is a GaAs contact layer doped with about m −3 ,
Each of layers 6 and 7 is formed under the condition of lattice matching with GaAs such that x = 0.49 or x = 0.45.
【００１８】以上のように構成されたヘテロ接合半導体
装置によれば、キャリア供給層６から２層のスペーサ層
５，４を介してチャネル層３へ電子が供給される結果、
該チャネル層３に高移動度の２次元電子ガスが形成され
る。このとき、ノンドープＡｌ0.2 Ｇａ0.8 Ａｓからな
る第１のスペーサ層４を設けたことにより、従来とは違
って残留するＡｓがノンドープＩｎx Ｇａ1-x Ｐからな
る第２のスペーサ層５に取り込まれることはほとんどな
く、急峻かつ清浄なＩｎＧａＡｓ／ＡｌＧａＡｓヘテロ
接合が形成される結果、十分に高い電子移動度が期待さ
れる。その効果について、Ｉｎの組成をｘ＝０．４５と
したときのキャリア濃度と電子移動度とを従来例との比
較のために表１および表２に示す。According to the heterojunction semiconductor device having the above structure, electrons are supplied from the carrier supply layer 6 to the channel layer 3 through the two spacer layers 5 and 4,
A high mobility two-dimensional electron gas is formed in the channel layer 3. At this time, by providing the first spacer layer 4 made of non-doped Al 0.2 Ga 0.8 As, residual As is taken into the second spacer layer 5 made of non-doped In x Ga 1-x P unlike the conventional case. As a result of forming a sharp and clean InGaAs / AlGaAs heterojunction, a sufficiently high electron mobility is expected. Regarding the effect, the carrier concentration and the electron mobility when the In composition is x = 0.45 are shown in Tables 1 and 2 for comparison with the conventional example.
【００１９】[0019]
【表１】 [Table 1]
【表２】 [Table 2]
【００２０】図２は、本発明の第２の実施例に係るヘテ
ロ接合半導体装置の断面構造を示すものであって、前記
第２の従来例（図４）に対応するものである。図２にお
いて、１は半絶縁性ＧａＡｓ基板、９は膜厚が１００ｎ
ｍのノンドープＧａＡｓバッファ層、１０は膜厚が２０
０ｎｍのノンドープＩｎx Ｇａ1-x Ｐバッファ層、１１
は膜厚が３５ｎｍでｎ型不純物を２×１０18ｃｍ-3程度
ドープしたｎ−ＩｎxＧａ1-x Ｐキャリア供給層、１２
は膜厚が２ｎｍのノンドープＩｎx Ｇａ1-x Ｐからなる
第１のスペーサ層、１３は本発明の中心となる膜厚が３
ｎｍのノンドープＡｌ0.2 Ｇａ0.8 Ａｓからなる第２の
スペーサ層、１４は膜厚が１５ｎｍのノンドープＩｎ
0.2 Ｇａ0.8 Ａｓチャネル層、１５は膜厚が１００ｎｍ
のＧａＡｓノンドープ層、１６は膜厚が１０ｎｍでｎ型
不純物を５×１０18ｃｍ-3程度ドープしたＧａＡｓコン
タクト層であり、１０，１１，１２の各層はＧａＡｓに
対して格子整合する条件であるｘ＝０．４９で形成され
ている。FIG. 2 shows a sectional structure of a heterojunction semiconductor device according to a second embodiment of the present invention, which corresponds to the second conventional example (FIG. 4). In FIG. 2, 1 is a semi-insulating GaAs substrate, and 9 is a film thickness of 100 n.
m non-doped GaAs buffer layer, 10 has a thickness of 20
0 nm non-doped In x Ga 1-x P buffer layer, 11
Is an n-In x Ga 1-x P carrier supply layer having a film thickness of 35 nm and doped with n-type impurities at about 2 × 10 18 cm -3 , 12
Is a first spacer layer made of non-doped In x Ga 1-x P having a film thickness of 2 nm, and 13 is a film thickness 3 which is the center of the present invention.
second spacer layer made of non-doped Al 0.2 Ga 0.8 As having a thickness of 14 nm, and 14 having a thickness of 15 nm.
0.2 Ga 0.8 As channel layer, 15 has a film thickness of 100 nm
Is a GaAs non-doped layer, 16 is a GaAs contact layer having a film thickness of 10 nm and doped with n-type impurities of about 5 × 10 18 cm −3 , and each of the layers 10, 11, and 12 is a condition for lattice matching with GaAs. It is formed at x = 0.49.
【００２１】以上のように構成されたヘテロ接合半導体
装置によれば、キャリア供給層１１から２層のスペーサ
層１２，１３を介してチャネル層１４へ電子が供給され
る結果、該チャネル層１４に高移動度の２次元電子ガス
が形成される。このとき、ノンドープＡｌ0.2 Ｇａ0.8
Ａｓからなる第２のスペーサ層１３を設けたことによ
り、従来とは違って残留するＰがノンドープＩｎ0.2 Ｇ
ａ0.8 Ａｓからなるチャネル層１４に取り込まれること
はほとんどなく、急峻かつ清浄なＡｌＧａＡｓ／ＩｎＧ
ａＡｓヘテロ接合が形成され、十分に高い電子移動度が
実現される。According to the heterojunction semiconductor device configured as described above, electrons are supplied from the carrier supply layer 11 to the channel layer 14 via the two spacer layers 12 and 13, and as a result, the channel layer 14 is supplied to the channel layer 14. A two-dimensional electron gas with high mobility is formed. At this time, undoped Al 0.2 Ga 0.8
Since the second spacer layer 13 made of As is provided, the residual P is non-doped In 0.2 G unlike the conventional one.
Almost not captured in the channel layer 14 made of a 0.8 As, and is sharp and clean AlGaAs / InG
An aAs heterojunction is formed and a sufficiently high electron mobility is realized.
【００２２】なお、上記両実施例において、チャネル層
３，１４を構成するノンドープＩｎx Ｇａ1-x ＡｓのＩ
ｎの組成ｘは０．２、膜厚は１５ｎｍとしたが、ｘで決
まる臨界膜厚以下の膜厚であればどのようなｘと膜厚の
組み合わせでもよい。また、ｘ＝０であるＧａＡｓでも
よい。In both of the above embodiments, the I of non-doped In x Ga 1-x As forming the channel layers 3 and 14 was used.
Although the composition x of n is 0.2 and the film thickness is 15 nm, any combination of x and film thickness may be used as long as the film thickness is not more than the critical film thickness determined by x. Alternatively, GaAs with x = 0 may be used.
【００２３】また、チャネル層３，１４と接するスペー
サ層４，１３を構成するノンドープＡｌy Ｇａ1-y Ａｓ
のＡｌの組成ｙは０．２としたが、どのようなｙの値を
用いてもよい。また、その膜厚を３ｎｍとしたが、この
限りではない。Further, non-doped Al y Ga 1-y As forming the spacer layers 4 and 13 in contact with the channel layers 3 and 14 is formed.
Although the Al composition y of was set to 0.2, any value of y may be used. Although the film thickness is set to 3 nm, the thickness is not limited to this.
【００２４】ノンドープＩｎＧａＰからなるスペーサ層
５，１２の膜厚を２ｎｍとしたがこの限りではなく、な
くてもよい。Although the thickness of the spacer layers 5 and 12 made of non-doped InGaP is set to 2 nm, the thickness is not limited to this and may be omitted.
【００２５】[0025]
【発明の効果】以上説明してきたとおり、本発明によれ
ば、ＩｎＧａＡｓチャネル層と接するようにＡｌＧａＡ
ｓスペーサ層を形成した構成を採用したので、電子が閉
じこめられかつ電子が走行するチャネル層とスペーサ層
とのヘテロ接合が急峻かつ清浄な接合となる結果、十分
に高い２次元電子ガスの移動度が得られる。As described above, according to the present invention, the AlGaA layer should be in contact with the InGaAs channel layer.
Since the structure in which the s spacer layer is formed is adopted, the heterojunction between the channel layer in which electrons are confined and the electrons travel and the spacer layer is sharp and clean, resulting in a sufficiently high mobility of the two-dimensional electron gas. Is obtained.
【図１】本発明の第１の実施例に係るヘテロ接合半導体
装置の断面図である。FIG. 1 is a cross-sectional view of a heterojunction semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例に係るヘテロ接合半導体
装置の断面図である。FIG. 2 is a sectional view of a heterojunction semiconductor device according to a second embodiment of the present invention.
【図３】第１の従来例に係るヘテロ接合半導体装置の断
面図である。FIG. 3 is a cross-sectional view of a heterojunction semiconductor device according to a first conventional example.
【図４】第２の従来例に係るヘテロ接合半導体装置の断
面図である。FIG. 4 is a cross-sectional view of a heterojunction semiconductor device according to a second conventional example.
１ 半絶縁性ＧａＡｓ基板 ２ ノンドープＧａＡｓバッファ層 ３ ノンドープＩｎ0.2 Ｇａ0.8 Ａｓチャネル層 ４ ノンドープＡｌ0.2 Ｇａ0.8 Ａｓスペーサ層 ５ ノンドープＩｎx Ｇａ1-x Ｐスペーサ層 ６ ｎ−Ｉｎx Ｇａ1-x Ｐキャリア供給層 ７ Ｉｎx Ｇａ1-x Ｐノンドープ層 ８ ＧａＡｓコンタクト層 ９ ノンドープＧａＡｓバッファ層 １０ ノンドープＩｎx Ｇａ1-x Ｐバッファ層 １１ ｎ−Ｉｎx Ｇａ1-x Ｐキャリア供給層 １２ ノンドープＩｎx Ｇａ1-x Ｐスペーサ層 １３ ノンドープＡｌ0.2 Ｇａ0.8 Ａｓスペーサ層 １４ ノンドープＩｎ0.2 Ｇａ0.8 Ａｓチャネル層 １５ ＧａＡｓノンドープ層 １６ ＧａＡｓコンタクト層 １７ Ａｓの取り込みにより形成されたＩｎＧａＡｓ
Ｐ（遷移領域） １８ Ｐの取り込みにより形成されたＩｎＧａＡｓＰ
（遷移領域）1 semi-insulating GaAs substrate 2 non-doped GaAs buffer layer 3 non-doped In 0.2 Ga 0.8 As channel layer 4 non-doped Al 0.2 Ga 0.8 As spacer layer 5 non-doped In x Ga 1-x P spacer layer 6 n-In x Ga 1-x P Carrier supply layer 7 In x Ga 1-x P non - doped layer 8 GaAs contact layer 9 non-doped GaAs buffer layer 10 non-doped In x Ga 1-x P buffer layer 11 n-In x Ga 1-x P carrier supply layer 12 non-doped In x Ga 1-x P spacer layer 13 non-doped Al 0.2 Ga 0.8 As spacer layer 14 non-doped In 0.2 Ga 0.8 As channel layer 15 GaAs non-doped layer 16 GaAs contact layer 17 InGaAs formed by incorporation of As
InGaAsP formed by incorporation of P (transition region) 18 P
(Transition area)
Claims (2)
のＩｎＧａＡｓからなるチャネル層と、 前記チャネル層に接するように形成されたノンドープの
ＡｌＧａＡｓからなる最下層を少なくとも有するスペー
サ層と、 前記スペーサ層上に形成されたｎ型のＩｎＧａＰからな
るキャリア供給層とを備えたことを特徴とするヘテロ接
合半導体装置。1. A channel layer made of non-doped InGaAs formed on a GaAs substrate, a spacer layer having at least a bottom layer made of non-doped AlGaAs formed in contact with the channel layer, and a spacer layer formed on the spacer layer. A heterojunction semiconductor device comprising a formed carrier supply layer made of n-type InGaP.
ＧａＰからなるキャリア供給層と、 ノンドープのＡｌＧａＡｓからなる最上層を少なくとも
有するように前記キャリア供給層上に形成されたスペー
サ層と、 前記スペーサ層中のノンドープのＡｌＧａＡｓからなる
最上層に接するように形成されたノンドープのＩｎＧａ
Ａｓからなるチャネル層とを備えたことを特徴とするヘ
テロ接合半導体装置。2. An n-type In formed on a GaAs substrate
A spacer layer formed on the carrier supply layer so as to have at least a carrier supply layer made of GaP and an uppermost layer made of non-doped AlGaAs, and formed so as to contact the uppermost layer made of non-doped AlGaAs in the spacer layer. Undoped InGa
A heterojunction semiconductor device comprising a channel layer made of As.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4197350A JP2994863B2 (en) | 1992-07-24 | 1992-07-24 | Heterojunction semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4197350A JP2994863B2 (en) | 1992-07-24 | 1992-07-24 | Heterojunction semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0645368A true JPH0645368A (en) | 1994-02-18 |
| JP2994863B2 JP2994863B2 (en) | 1999-12-27 |
Family
ID=16373025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4197350A Expired - Fee Related JP2994863B2 (en) | 1992-07-24 | 1992-07-24 | Heterojunction semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2994863B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2758207A1 (en) * | 1997-01-07 | 1998-07-10 | Fujitsu Ltd | High speed compound semiconductor device production |
| GB2358736A (en) * | 1999-09-28 | 2001-08-01 | Showa Denko Kk | High electron mobility transistors |
| US6462361B1 (en) | 1995-12-27 | 2002-10-08 | Showa Denko K.K. | GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure |
| JP2004207472A (en) * | 2002-12-25 | 2004-07-22 | Sumitomo Chem Co Ltd | Compound semiconductor epitaxial substrate and its manufacturing method |
-
1992
- 1992-07-24 JP JP4197350A patent/JP2994863B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462361B1 (en) | 1995-12-27 | 2002-10-08 | Showa Denko K.K. | GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure |
| FR2758207A1 (en) * | 1997-01-07 | 1998-07-10 | Fujitsu Ltd | High speed compound semiconductor device production |
| US5939737A (en) * | 1997-01-07 | 1999-08-17 | Fujitsu Limited | High-speed compound semiconductor device having a minimized parasitic capacitance and resistance |
| US6586319B1 (en) | 1997-01-07 | 2003-07-01 | Fujitsu Limited | High-speed compound semiconductor device having a minimized parasitic capacitance and resistance |
| GB2358736A (en) * | 1999-09-28 | 2001-08-01 | Showa Denko Kk | High electron mobility transistors |
| GB2358736B (en) * | 1999-09-28 | 2004-06-23 | Showa Denko Kk | GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure |
| US6841435B2 (en) | 1999-09-28 | 2005-01-11 | Showa Denko K.K. | Method for fabricating a GaInP epitaxial stacking structure |
| JP2004207472A (en) * | 2002-12-25 | 2004-07-22 | Sumitomo Chem Co Ltd | Compound semiconductor epitaxial substrate and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2994863B2 (en) | 1999-12-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0477515B1 (en) | Heterojunction field effect transistor with monolayer in channel region | |
| JP3224437B2 (en) | III-V compound semiconductor device | |
| EP0381396A1 (en) | Compound semiconductor devices | |
| JPH0815213B2 (en) | Field effect transistor | |
| US5489549A (en) | Method of fabricating n-type antimony-based strained layer superlattice | |
| WO2007030316A2 (en) | Strain compensated high electron mobility transistor | |
| JP2539268B2 (en) | Semiconductor device | |
| JP2994863B2 (en) | Heterojunction semiconductor device | |
| JPS63278277A (en) | Compound semiconductor device | |
| EP0558011B1 (en) | High electron mobility transistor | |
| JPH11214676A (en) | Semiconductor device | |
| JPH06244217A (en) | Heterojunction semiconductor device | |
| JPH04343438A (en) | Field effect transistor | |
| JP2730511B2 (en) | Heterojunction field effect transistor | |
| JP2567730B2 (en) | Heterojunction field effect transistor | |
| JP2879250B2 (en) | Field effect semiconductor device | |
| JP2000164852A (en) | Gallium-indium-nitride-arsenide based epitaxial wafer and high electron mobility transistor using the same | |
| JPH04294547A (en) | Inalas/ingaas heterojunction structure semiconductor device and field effect transistor using it | |
| JP2701568B2 (en) | Field effect transistor | |
| JPH09260643A (en) | High-electron mobility transistor | |
| JPH01120871A (en) | Semiconductor device | |
| JPS63172A (en) | Semiconductor device | |
| JPH09246529A (en) | Field effect transistor and its manufacture | |
| JP2002190588A (en) | Heterojunction fet | |
| JPH0695534B2 (en) | Heterostructure semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19991005 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081022 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091022 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091022 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101022 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111022 Year of fee payment: 12 |
|
| LAPS | Cancellation because of no payment of annual fees |