JPS61228725A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To set the titled device into the standby state by both an external signal and an internal signal by providing an operation control means of an oscillation circuit, a control means stopping and restarting the operation of the oscillation circuit and an operation control means for a counter and a timing generation circuit to an LSI including the oscillation circuit and the timing generation circuit. CONSTITUTION:When the external signal 33 goes to a logical 1, an F/F 30 is set, an output of an OR gate 34 goes to 1 and the oscillation circuit 10 and the timing signal generating circuit 20 are stopped. Further, a counter 70 is reset and brought into the standby state. When the signal 33 goes to logical '0', the circuit 10 and the counter 70 are brought into the operating state. The F/F 60 keeps the set state until an overflow signal of the counter 70 is outputted and the circuit 20 is in the stop state. When the operation of the circuit 10 is restarted, an overflow signal is generated from the counter 70 by using a signal 11 after the time required for oscillation stability elapses. Thus, the F/F 60 is reset and the circuit 20 starts also the operation. When a standby internal signal 42 is outputted, an F/F 40 is set to form the standby state. When a standby release signal 51 goes to logical 1, the F/F 40 is reset.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device having an oscillation circuit for a crystal or ceramic resonator, and whose operation is controlled by various timing signals created based on the oscillation circuit. Regarding equipment.

[Prior art]

In recent years, with the progress of integrated circuit technology, integrated circuit devices have become 0MO
8 is progressing rapidly. Along with this, in order to make effective use of the low power consumption feature of 0MO8, a function has been added that inhibits the operation of the internal circuit by stopping the primary oscillation of the oscillation circuit when the integrated circuit is in a non-operating state (standby). Integrated circuit devices (hereinafter referred to as LSI) are known.

[Problems to be solved]

As described above, in an LSI that uses a crystal or ceramic resonator as an oscillator, when the standby state is canceled and the operation is restarted, stable oscillation cannot be immediately obtained even if oscillation is started. For this reason, in the past, LSIs that used crystal or ceramic resonators did not have a standby function to stop oscillation, and even if they did, standby was only allowed to be released under special conditions. It was normal.

Specifically, since there is at least time required for oscillation to stabilize between the signal applied to the LSI to cancel standby and the time when the LSI actually resumes operation, the standby cancel signal is applied to the LSI reset signal. An appropriate oscillation stabilization time had to be set outside the LSI.

In addition, in order to execute standby processing in the event of an emergency such as a power failure, multiple instructions must be executed for that purpose.
High-speed processing was not possible. Therefore, conventionally, standby mode could only be set from the outside or by executing complex instructions internally.

[Means for solving problems]

The present invention provides an LSI that includes an oscillation circuit using a crystal or ceramic resonator and a timing generation circuit that generates various control timing signals based on an output signal from the oscillation circuit. a first control means for controlling the operation of the circuit; a second control means for stopping the operation of the oscillation circuit according to a second signal and restarting the oscillation circuit according to a third signal; It has a counter that counts output signals from the circuit and outputs the signal after a predetermined period of time has elapsed, and a third control means that operates the timing generation circuit based on the output signal of the counter, the third control means It is characterized in that it is adapted to respond to both the first and second control means.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 10 is an oscillation circuit (08C), 20 is a timing signal generation circuit composed of a frequency dividing circuit and other logic circuits, and 21 is a timing signal. 30, 40.
60 is a flip-flop (hereinafter referred to as F/F); 50 is an edge detection circuit for the signal 51; 70 is a counter that counts the signal from the oscillation circuit 1o and generates an overflow signal after a certain period of time; 31 is an AND gate; 3' 4 is or gate,
32 is an inverter. 33 is an external signal for standby control, 42 is a standby command signal (internal signal),
51 is a standby release signal.

Referring to FIG. 1 and FIG. 2 showing the operating signal waveforms,
Standby operation using external signals will be explained. The oscillation circuit output signal 11 is in an operating state, and when the external signal 33 becomes logic 1111 (hereinafter simply referred to as 1u) at time [21], the F/F 30 is set in synchronization with the timing signal 21, and the output of the OR gate 34 becomes 1111. becomes. At this time, the 9 oscillation circuit 10 is stopped, and since the F/F 60 is also set at the same time, the timing signal generation circuit 2° is also stopped. Also, the counter 70 is reset.

It is now in standby mode.

Next, at time 122, the external signal 33 becomes a logic 1IO
When u (hereinafter simply referred to as 1loII), F/F3
0 is reset and the output of the OR gate 34 becomes II□II
As a result, the oscillation circuit 10 and the counter 70 become operable. Since the F/F 60 maintains the set state until the overflow signal of the counter 70 is output, the timing signal generation circuit 20 is in a stopped state. Oscillation circuit 1
o operation resumes, and the oscillation circuit output signal 11 is output to the counter 7.
After the preset time required for the oscillation to stabilize, the counter 70 generates an over "7O-(i). As a result, the F/F 13Q is reset and the timing generation circuit 20 resumes operation, returning to normal operation. .

Next, standby by a standby command signal will be explained using FIG. 1 and FIG. 3 showing operating waveforms. Normally, prior to execution of the standby command, interrupt processing is executed in response to an external interrupt request or the like that notifies a power supply abnormality or the like. At the end of the interrupt process, the standby command signal 42 is output and the F/F 40 is set by executing the standby command.

In this case, the agate 34 becomes 11111, the oscillation circuit 1o stops, the counter 70 goes into a reset state, and the F
/F2O is set, so the timing generation circuit 20
It also stops and goes into standby mode. Next, at time 131, when the standby release signal 51 becomes 111, the edge detection circuit 50 outputs a one-shot hit pulse signal.
F/F4Q is reset. Hereinafter, similarly to the above explanation, the OR gate 34 and the 9 oscillation circuit 1 with >E l g l
0 becomes operational, the reset of the counter 70 is released, and the oscillation circuit output signal 11t-# is counted. After a certain period of time, the F/F 60 is reset by the overflow signal of the counter circuit 700, the timing generation circuit 20 becomes operational, and the operation of the LSI is restarted.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to set the standby state by both the standby control external signal and the standby command signal, and it is possible to use the standby state according to the degree of emergency, and to significantly reduce power consumption. A small standby is possible. Further, it is possible to provide an LSI that can obtain oscillation stabilization time when standby is released.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
3 and 3 are timing charts for explaining the operation. 10...Oscillation circuit, 20...Timing generation circuit, 21...Timing signal, 30.
40. 60...Flip-flop, 31.
...AND gate, 32...Inverter, 34...OR gate, 50...Edge detection circuit, 70...Counter. -16--ko

Claims (1)

[Claims] In an integrated circuit device including an oscillation circuit using a crystal or ceramic resonator, and a timing generation circuit that generates various control timing signals based on output signals from the oscillation circuit, the oscillation circuit is activated in response to a first signal. a first control means for controlling the operation; a second control means for stopping the operation of the oscillation circuit by a second signal and operating the oscillation circuit by a third signal; and a second control means for controlling the output signal from the oscillation circuit. a counter that counts and outputs a signal after a predetermined period of time has elapsed; and a third counter that re-operates the timing generation circuit based on a signal that the counter initialized by both the first and second control means outputs after a predetermined period of time has elapsed. An integrated circuit device characterized by having a control means.