JPH0222716A - Clock control circuit - Google Patents

Abstract

PURPOSE:To supply system reset signals proper to plural kinds of digital system by controlling a set signal to supply the system reset signal at a selected timing. CONSTITUTION:At the time of power-on, an output signal 42A of a counter circuit 42 goes to '0' because the power-on signal in a power-on reset circuit 1 is '0' and a signal 22A goes to '0' in a selecting circuit 2. Consequently, an operation clock 51A in an output stop circuit 5 goes to '0'. Thereafter, when a control signal 3A is set to '1' at the time of rise of the power-on signal to '1', an original oscillation signal 31A is outputted from a fundamental oscillating circuit 3. The signal 22A goes to '1', and the circuit 42 is counted up for each input of the signal 31A. When the circuit 42 is counted up, signals 41A and 42A go to '0' and '1' respectively, and the operation clock 51A outputted from the output stop circuit 5 has the same phase as the signal 31A. When the clock is outputted, the system reset signal of a reset timing circuit 6 goes to '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a clock control circuit, and particularly to a lock control circuit suitable for a CMOS LSI such as a CMOS microprocessor.

(Prior Art) Digital systems usually operate in synchronization with periodically generated pulses called clocks, and therefore require a clock control circuit or clock circuit to generate the clocks.

By the way, recent digital systems do not include circuits that are used in fields where high speed is particularly required.

CMOS LSI has become mainstream. Because, C
This is because MOSLSI has the great advantage of low power consumption.

(Problem to be Solved by the Invention) Taking a CMOS microprocessor, which is a typical CMOS LSI, as an example, the above advantages are utilized in the CMOS microprocessor as well, but the idle state such as the HALT state is not suitable for microprocessors. .

It is desired to further reduce power consumption in such a state.

Furthermore, it is necessary to externally apply a system reset signal to initialize a digital system such as a microprocessor. However, requirements for the system reset signal, such as the required length of the system reset signal and the necessity of synchronization with a clock, usually differ from system to system. Most conventional clock control circuits require a separate circuit to supply the system reset signal, and even clock control circuits that have the function of controlling the system reset signal are not compatible with a specific microprocessor or other system. I was just responding.

Furthermore, the original oscillation generated in the basic oscillation circuit of the clock control circuit is not stable for a while after power is turned on.
Conventional clock control circuits often use the original frequency as the system clock.

As a result, there was a problem in that the power supply was unstable and a lock was supplied when the power was turned on.

The present invention was made in view of the current situation, and
The first objective is to provide a clock control circuit that can supply appropriate system reset signals to a plurality of types of digital systems.

Another object of the present invention is to provide a clock control system that does not become unstable and does not output a lock upon power-on, and that can reduce power consumption in an idle state of a digital system, such as the IfALT state in a microprocessor. The purpose is to provide circuits.

(Means for Solving the Problems) The clock control circuit of the present invention includes a basic oscillation circuit that can stop two oscillations, an output blocking circuit that can prevent the output of the basic oscillation circuit from being derived, and a clock control circuit that can stop two oscillations when a reset signal is input. A reset timing circuit that can output system reset signals at multiple types of timing.

A circuit that selects, based on a setting signal, whether or not to instruct the basic oscillation circuit to stop oscillation when a control signal is input, and outputs a system reset signal in the reset timing circuit based on the setting signal. and a circuit that instructs the output blocking circuit to block output of the output for a predetermined period of time at least when the power is turned on, thereby achieving the above object.

(Example) The present invention will be described below with reference to Examples.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention.

Circuit diagrams of each part of this embodiment are shown in FIGS. 2 to 7.

The clock control circuit of this embodiment basically consists of a power-on reset circuit 19 a selection circuit 2. Basic oscillation circuit 3. Output derivation command circuit 4. It includes an output blocking circuit 5 and a reset timing circuit 6.

The basic oscillation circuit 3 generates a clock of a predetermined frequency, and is configured to be able to stop oscillation based on the signal 21^.

The output blocking circuit 5 connected to the output side of the basic oscillation circuit 3 controls the input signal 23A from the selection circuit 2 and the input signals 41A and 42A from the output derivation command circuit 4, etc. The circuit is capable of preventing the generated original vibration 31^ from being extracted to the outside.

The output derivation command circuit 4 receives an input signal 12A from the power-on reset circuit 1 and an input signal 22A from the selection circuit 2.
This circuit generates signals 418 and 42^ that instruct the output blocking circuit 5 to block the operation clock output based on the above, and includes a gate circuit 41 and a counter circuit 42.

The selection circuit 2 connected before the basic oscillation circuit 3 and the output blocking circuit 5 includes gate circuits 21 and 22 and a latch circuit 23. The selection circuit 2 is.

Based on the states of setting signals IA, 2A, etc., control signal 3A
Selects whether or not to instruct the basic oscillation circuit 3 to stop oscillation when the reset signal 14A is input.
is input, it is selected whether or not the output derivation command circuit 4 is instructed to block clock output to the output blocking circuit 5, and furthermore, the timing of the output of the system reset signal 43A in the reset timing circuit 6, which will be described later, is selected. is configured to do so.

Furthermore, when the power is turned on, the power-on reset circuit 1 cooperates with the output derivation command circuit 4, etc., to prohibit unstable operation clock output, and resets the system connected to this tarlock control circuit based on the reset signal 14A. This is a circuit for outputting a final system reset signal 43A from the reset timing circuit 6.

The reset timing circuit 6 is a circuit that outputs a system reset signal 43A at a timing selected based on a signal from the 2 selection circuit 2 or the like.

Normally, the system reset signal 43A is used to reset the system of a digital system such as a microprocessor sensor connected to this clock control circuit. The system reset signal 43^ is active when it is in the "0" state.

FIG. 2 is a circuit diagram of the power-on reset circuit 1.

The power-on reset circuit 1 is provided with an RC circuit including a resistor R1 and a capacitor C1 in order to generate a power-on signal PWON when the power is turned on. This R
A power-on signal PWON is generated in the C circuit, and this power-on signal PWON is applied to the inverter 11. An inverter 16 is connected to the output side of the inverter 11, and the inverter 16 provides an output signal 11A to the selection circuit 2 and the output blocking circuit 5.

The power-on signal PWON is also inverted by the inverter 11. It is applied to one input terminal of NAND gate 12. The NAND gate 1-12 constitutes a latch circuit together with a NAND gate 13 to which a signal 42A from a counter circuit 42 of an output derivation command circuit 4, which will be described later, is input.

The output signal 13A of the latch circuit is given to the reset timing circuit 6.

Power-on signal PWON inverted by inverter 11
is also applied to one input terminal of the NOR gate 17.

An inverter 18 is connected to the other input terminal of the NOR gate 17.
A reset signal 14A that is inverted at 1 is applied. NOR
N which receives the signal 22A from the output signal 2 selection circuit 2 of the gate 17 and the signal 42A from the output derivation command circuit 4.
The output signal 12A obtained by the circuit including the OR gates 14 and 15 and the inverter 19 is provided to the gate circuit 41 of the output derivation command circuit 4.

FIG. 3 shows the selection circuit 2. The selection circuit 2 includes gate circuits 21 and 22 and a latch circuit 23. The gate circuit 21 receives a setting signal IA, 2A, a control signal 3A, and a signal 15A from the power-on reset circuit l.
It is a circuit that inputs inverter 213゜221
, 222 , NAND gate 211 . It also has a NOR gate 212. After the gate circuit 21, there is a NAN
A latch circuit 23 consisting of D gates 231 and 232 is connected. The latch circuit 23 outputs a signal 218 instructing the basic oscillation circuit 3 to stop oscillation.

The gate circuit 22 receives a setting signal IA and a reset signal 1.
48.

and outputs a signal 22A based on the signal 11A from the power-on reset circuit 1, and the NOR gate 223. Inverter 224, NAND gate 225
and an inverter 226. The output signal 22A is
It is applied to the power-on reset circuit I, the output derivation command circuit 4 and the reset timing circuit 6 described above.

It is used to control the output and reset timing of the operating clock.

FIG. 4 shows the basic oscillation circuit 3. The basic oscillation circuit 3 mainly consists of an oscillation circuit consisting of an oscillator OSC and capacitors C2 and C3, and is further connected to a circuit consisting of NAND gates 31, 32 and inverters 33, 34.

It is possible to stop oscillation by input signal 21A. The original oscillation 318 is applied to the output blocking circuit 5 and the gate circuit 41.

FIG. 5 shows the output derivation command circuit 4. Here, a NOR gate 411 and an inverter 412 are installed after the gate circuit 22 of the selection circuit 2 and the power-on reset circuit 1.
, 413 is connected thereto. A counter circuit 42 consisting of N D flip-flops 1, DF2, . . . DFN is connected to the subsequent stage of the gate circuit 41. Q of D flip-flop DFN
The outputs are output via inverters 421 and 422 as signals 41A and 42A having opposite phases to each other.

Among the input signals, signal 128 is used by the master oscillator 314 to control whether or not to cause the counter circuit 42 to count, and signal 22A is used to reset the counter circuit 42.

FIG. 6 shows the output blocking circuit 5. The output blocking circuit 5 includes an inverter 52 and a NAND gate (51.
53. and 54 in combination. NAN
The first input terminal of the D gate 51 receives the original oscillation 31A, the second input terminal receives the signal 42A from the counter circuit 42, and the third input terminal receives the signal 42A from the counter circuit 42.
An output signal from a NAND gate 53 is applied to the input terminal of each of the NAND gates 53 and 53, respectively. The output signal of NAND gate 51 is inverted by inverter 52 to output operating clock 51A. The signal 23^ from the gate circuit 21 and the output signal 41A from the counter circuit 42 are input to the first and second input terminals of the NAND gate 53, respectively. Also,
A signal 11A from the power-on reset circuit 1 is input to the input terminal of the NAND gate 54.

The reset timing circuit 6 is shown in FIG. The reset timing circuit 6 includes four D flip-flops DI,
02. It has a shift register consisting of D3 and D4, and a gate circuit consisting of inverters 66, 67, 69 and a NAND gate 68. The shift register is driven by an operating clock 51A input through a circuit consisting of a NOR gate 61 and an inverter 62 connected to the clock terminal of the D flip-flop D1. The D input terminal of the D flip-flop D1 is set to "1". Each D flip-flop is a NAND gate 7
4 and an inverter 75
It is reset using 5A or 22A. In the gate circuit, the Q output of the D flip-flop D4 at the final stage of the shift register.

With signal 13^ and reset signal 14A as input signals.

A system reset signal 43A is obtained.

The clock control circuit of this embodiment has four input signals. The role of each input signal will be briefly described.

(1) Setting signals 18 and 2^ are signals for determining which of the four operating modes of the present tarlock control circuit to be selected, which will be explained in detail later in section 9.

(2) The control signal 3A is a signal for controlling the stop of oscillation in the basic oscillation circuit 3. Whether or not oscillation is stopped when the control signal 3A is manipulated depends on the operating mode.

(3) Reset signal 14^ is system reset signal 43
This is a signal for outputting A.

Next, the detailed operation of the above embodiment will be explained.

When the power is turned on, the power-on signal PWON in the power-on reset circuit 1 shown in FIG. 2 is "0" and the signal 228 in the 1 selection circuit 2 becomes "0", so that the counter circuit shown in FIG. 42 D flip-flop leaves 1
, DF2, . . . DFN is reset. As a result, the output Q of the D flip-flop N becomes "0", so the output signal 42A of the counter circuit 42 becomes "0".
becomes. Therefore, the output of the original oscillator 31A to the operating clock 51A in the output blocking circuit 5 of FIG. 6 is blocked, and the operating clock 51A becomes "0".

After that, when the power-on signal PWON rises to "1", both the reset signal 14A and the control signal 3A are set to "1".
1", the output signal 21 of the latch circuit 23
A becomes "1". Therefore, in the basic oscillation circuit 3 of FIG. 4, an original oscillation 318 is output.

Also, by changing the signal 11A to "1", the signal 2
28 becomes "IJ", and the reset state of the counter circuit 42 is released. At this time, the output signal 12A in FIG. 2 becomes "IJ".
0'', the counter circuit 42 in FIG. 5 counts up every time the fundamental oscillation circuit 3 falls to the original oscillation 31. This counter circuit.

It is set up in time 2()l-11T, and the Q output of flip-flop DFN becomes "1". Note that N is the number of D flip-flops in the counter circuit 42.

T indicates the period of the original vibration 31A.

When the Q output of the final stage D flip-flop N becomes "1", the signals 41A and 42A are r□, , r
l, becomes. Therefore, after the Q output of the D flip-flop N becomes IJ, the operating clock 51A becomes a signal in phase with the original oscillator 31A from the first rise of the original oscillator 31.

When the operating clock 518 is output, the shift register of the reset timing circuit 6 starts shifting. Since the shift register is composed of four stages of D flip-flops D4 to D4, the system reset signal 43A in FIG. ” stand up.

A timing chart of the above operation is shown in FIG.

Note that in the above operation, the setting signals IA and 2A are as follows.

It does not matter whether it is set to "0" or "1".

The clock control circuit of this embodiment uses setting signals 1^ and 2A.
Depending on the setting status of 'r RUN mode', '5TOP mode J, r RSTOP mode' and r5TOP
It operates in four types of operation modes: R mode. Below, operations in these four types of modes will be explained in order.

(a) nuN mode In the RUN mode, setting signals IA and 28 are both set to "1". The reset signal 14A and control signal logic are set to "1" to operate the clock control circuit. R.U.
In the N mode, even if the control signal 3A is set to "0", the output signal 21A in FIG.
Continuous output. A timing chart of the above operation is shown in FIG.

In RUN mode, system reset signal 43A
is synchronized with the reset signal 14A. This timing chart is shown in FIG. Note that the reset signal 14A may be asynchronous with the operating clock 51A.

(b) STOP mode In the 5TOP mode, setting signals IA and 2A are both set to "0". The reset signal 14A and the control signal 3A are set to "1" to operate the clock control circuit. After this, when the control signal is changed to "0" while the clock control circuit is operating, the output signal 218 in FIG.
0'', the basic oscillation circuit 3 stops oscillating, and both the original oscillation 31A and the operating clock 51A are fixed at rlJ. This timing chart is shown in FIG.

When the reset signal 14A is set to "0" in this state, the system reset signal 438 is synchronized with rQ,
becomes. At this time, when the control signal 38 is set to "1", the original oscillation 31A is output. After that, when the reset signal 14A is set to "1", the counter circuit 42 starts counting.
The counter circuit set time is "2 (N-11T) from the point of fall of the original oscillation 31A immediately after.

After , in synchronization with the falling edge of the original oscillation 31A.

An operating clock 51A is output. The system reset signal 43A becomes "1" in synchronization with the rising edge of the fourth clock after the output of the operating clock 51A. This timing chart is shown in FIG.

(C) R5TOP mode In the R3TOP mode, setting signals 18 and 2A are set to r□, , rl, respectively. Set the reset signal 148 and the control signal 3A to "1".

Operate the clock control circuit. After this, in the single-line mode, even if the control signal 3A is changed to "0" while the clock control circuit is operating, both the original oscillator 31A and the operating clock 51A do not stop and are continuously output. This behavior is RU
This is the same as in the N mode.

That is, the timing chart is as shown in FIG.

In this state, when the reset signal 14A is set to "0", the system reset signal 43A is set to "0" in synchronization with this.
”. At the same time, the counter circuit 42 is reset and the signal 42A becomes "0", so that the output to the operating clock 51 is stopped. After this, reset signal 14A is rlJ
Then, after the counter circuit set time has elapsed from the falling edge of the original oscillation 31A immediately after this, the original oscillation 31A
The operating clock 51.A is synchronized with the operating clock 51. A is output. After the output of the operating clock 51A, the system reset signal 43A becomes "1" in synchronization with the rising edge of the fourth clock. This timing chart is shown in FIG.

(d) 5TOPR mode In the 5TOPR mode, setting signals LA and 2A are set to ``rl'' and ``ro'', respectively. In this condition.

The reset signal 14A and the control signal 3A are set to "1" to operate the clock control circuit. After this.

When the control signal 3^ is set to "0" while the clock control circuit is operating, both the original oscillator 31A and the operating clock 51^ become "1".
” is fixed. The timing chart for this operation is 5T.
This is the same as the OP mode, as shown in FIG.

In this state, when the reset signal 14A is set to rQJ, the system reset signal 43A becomes "0" in synchronization with this.
becomes. At this time, when the control signal 3A is set to "1", the original oscillation 31A and the operating clock 51A are output. Thereafter, when the reset signal 14A is set to "1", the system reset signal 43A is set to "1" in synchronization with this.

This timing chart is shown in FIG.

As explained above, 5TOP mode and 5TOP
In the R mode, the original oscillation 31A and the operating clock 518 can be fixed at rlJ by setting the control signal 3A to "0". Therefore, by manipulating the control signal 3A, it is possible to effectively reduce the power consumption in the idle state of the CMO 5I, Sr, etc. that receive clocks from the clock control circuit of this embodiment.

Moreover, since the timing at which the system reset signal 43A returns to "1" and the presence or absence of output to the operation clock 51 while the signal is "0" differ depending on the operation mode, the digital system designer may A convenient operation mode can be selected when using this clock control circuit.

(Effects of the Invention) The clock control circuit of the present invention can supply a system reset signal at a selected timing by controlling a setting signal to a digital system using a single clock control circuit. Therefore, the clock control circuit of the present invention is compatible with a plurality of types of digital systems. Furthermore, the clock control circuit of the present invention can avoid unstable and locked outputs when the power is turned on. moreover.

Since the output of the clock can be stopped as necessary, it is possible to reduce power consumption in an idle state of a digital system using a two-clock control circuit.

4, ・″　　　　i′H FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a power-on reset circuit in the embodiment, and FIG. 3 is a circuit diagram showing a selection circuit.

4 is a circuit diagram showing a basic oscillation circuit, FIG. 5 is a circuit diagram showing an output derivation command circuit, FIG. 6 is a circuit diagram showing an output blocking circuit, FIG. 7 is a circuit diagram showing a reset timing circuit,
Fig. 8 is a timing chart for explaining the operation when the power is turned on, Fig. 9 is a timing chart showing the oscillation and clock output continuation state in RUN mode and RSTOP mode, and Fig. 10 is for 5TOPR mode and S↑O
A timing chart showing oscillation stop and clock output stop in PR mode, FIG. 11 is a timing chart showing system reset signal timing in RAIN mode, and FIG. 12 is a timing chart showing oscillation restart and system reset signal timing in 5TOP mode. FIG. 13 is a timing chart showing the timing of restarting clock output and the system reset signal in the RSTOP mode. FIG. 14 is a timing chart showing the timing of oscillation, restarting the clock output, and the system reset signal in the 5TOPR mode.

■...Power-on reset circuit, 2...Selection circuit.

3... Basic oscillation circuit, 4... Output derivation command circuit, 5
... Output blocking circuit, 6... Reset timing circuit.

that's all

Claims (1)

[Claims] 1. A basic oscillation circuit that can stop oscillation, an output blocking circuit that can prevent derivation of the output of the basic oscillation circuit, and a system reset signal that outputs a system reset signal at multiple types of timing when a reset signal is input. a reset timing circuit capable of outputting a reset timing circuit; a circuit that selects whether or not to instruct the basic oscillation circuit to stop oscillation based on a setting signal when a control signal is input; a circuit that selects, based on a setting signal, the reset timing; A clock control circuit comprising: a circuit that selects the timing of output of a system reset signal in the circuit; and a circuit that instructs the output blocking circuit to block derivation of the output for a predetermined period of time at least when power is turned on.