JPH0313782Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a memory backup device that prevents data loss in a data memory during a long-term power outage.

[Conventional technology]

Conventionally, there is a memory backup device used in a VTR as shown in FIG. That is, the oscillation circuit 2 is composed of a DC power supply 1 consisting of a rectifier and a storage battery, an oscillation circuit 2 connected to the DC power supply 1, a frequency dividing circuit 3, a clock counter 4, and a data memory 5.
A high frequency signal generated by a crystal oscillator (crystal oscillator) is converted into a low frequency signal by a frequency dividing circuit 3, this low frequency signal is counted by a clock time counter 4, and this counted clock signal is given to a data memory 5. It is.

[Problem that the invention attempts to solve]

In this device, when the AC power supply 6 is lost, the DC power supply 1 becomes only the storage battery, and DC voltage is applied from the storage battery to the oscillation circuit 2 etc. However, since the current in the oscillation circuit 2 and the frequency dividing circuit 3 is large, the storage battery is discharged in a short period of time, which not only causes the oscillation circuit 2 to stop, but also causes the problem that all the data in the volatile data memory 5 is erased.

This invention was made for the purpose of solving the problems of the prior art.

[Means for solving problems]

Means for solving the above problems will be explained below using FIG. 1 corresponding to the embodiment. This invention converts a high frequency signal generated by an oscillation circuit 2 into a low frequency signal by a frequency dividing circuit 3, counts this low frequency signal by a clock counter 4, and supplies the counted clock signal to a data memory 5. In a memory backup device, a power outage detection circuit 10 is connected to an AC power source and generates a binary signal of a power-on signal and a power outage signal, and a count signal is generated based on the power outage signal and the output signal of a frequency dividing circuit 3. a logic circuit 11 that starts counting by the count signal and is reset by the energization signal;
In addition, a counter 12 that generates a reset signal upon overflow, and a flip-flop 13 that generates an oscillation enable/stop signal that causes the oscillation circuit 2 to oscillate with the energization signal and stop the oscillation circuit 2 with the reset signal are provided. 12 overflows, the pre-oscillation circuit 2 is stopped to prevent data loss due to discharge of the storage battery of the data memory 5.

[Effect]

In the device configured in this way, the counter 12 overflows in the event of a long power outage, and the generated reset signal of the counter 12 causes the oscillation circuit 2 to stop, and DC power is supplied only to the data memory 5 from the storage battery. There is.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of this invention. In FIG. 1, 10 is a power failure detection circuit;
11 is a logic circuit, 12 is a counter, and 13 is a flip-flop. First, the configuration will be described. The power failure detection circuit 10 is connected to the AC power supply 6 and generates a binary signal of an energization signal (for example, a "1" signal) and a power failure signal (for example, a "0" signal). The power failure detection circuit 10 is composed of a transformer, a rectifier, a buffer amplifier, and the like.

The logic circuit 11 is composed of a NOT circuit and an AND circuit, the output terminal of the power failure detection circuit 10 is connected to the input terminal of the NOT circuit, and the output terminal of the NOT circuit and the frequency dividing circuit 3 are connected to the input terminal of the AND circuit. output terminal is connected.

The input terminal of the counter 12 is connected to the output terminal of the logic circuit 11, and the reset input terminal of the counter 12 is connected to the output terminal of the power failure detection circuit 10. When counter 12 overflows, it generates a reset signal.

The reset input terminal of flip-flop 13 is
It is connected to the output terminal of the power failure detection circuit 10, the reset input terminal of the flip-flop 13 is connected to the output terminal of the counter 12, and the output terminal of the flip-flop 13 is connected to the oscillation/stop input of the oscillation circuit 2.

Next, the operation will be explained. When the power is on, the power failure detection circuit 10 generates the power-on signal, so the flip-flop 13 is reset and generates the oscillation enable signal, and the oscillation circuit 2 is operating. . The high frequency signal generated by the oscillation circuit 2 is converted into a low frequency signal by the frequency dividing circuit 3, counted by the clock counter 4, and provided to the data memory 5 as a clock signal. In that case, the output signal of the NOT circuit is a "0" signal, so the logic circuit 11
is not generating a count signal, and counter 12
is not working.

Next, when the AC power supply 6 is lost, the power failure detection circuit 10 generates a power failure signal, but the state in which the flip-flop 13 generates the oscillation permission signal is maintained, and the oscillation circuit 2 continues to operate. Due to the power failure signal from the power failure detection circuit 10, the output signal of the NOT circuit becomes a "1" signal, so the logic circuit 11 generates a count signal and the counter 12 starts counting. When counter 12 overflows, it generates a reset signal, which resets flip-flop 13, generates an oscillation stop signal, and stops oscillation circuit 2 from operating.

By stopping the oscillation circuit 2, the frequency dividing circuit 3 and the clock counter 4 become inoperable, and the count signal of the logic circuit 11 and the reset signal of the counter 12 disappear, and the flip-flop 13 is maintained in the reset state. . Further, since the oscillation circuit 2 is stopped, DC current is supplied only to the data memory 5 from the storage battery.

Note that the time at which the counter 12 overflows is determined assuming the maximum power outage time so that the data in the data memory 5 will not be lost within the remaining time after the overflow.

Next, when energized, the power outage detection circuit 10 generates a energization signal, so the flip-flop 13 is reset and the oscillation circuit 2 operates.
The counter 12 is reset to prepare for the next power outage.

In a short power outage in which the counter 12 does not overflow, the oscillation circuit 2 etc. are operated in the same way as when the power is on, and in a long power outage in which the counter 12 overflows, the oscillation circuit 2 etc. are disabled and the data memory 5 is only supplies direct current. In this way, since the operating time of the oscillation circuit 2 and the like after a power outage can be controlled, it is possible to avoid a situation where the oscillation circuit 2 becomes inoperable and the data in the data memory 5 disappears due to discharge of the storage battery.

[Effect of idea]

As explained above, this invention includes a power outage detection circuit that is connected to an AC power source and generates a binary signal of a energization signal and a power outage signal, and a count signal based on the power outage signal and the output signal of the frequency dividing circuit. The count is started by the logic circuit that generates the , and the count signal, and is reset by the energization signal,
A counter that generates a reset signal upon overflow, and a flip-flop that generates an oscillation enable/stop signal that causes the oscillation circuit to oscillate with the energization signal and stop the oscillation circuit with the reset signal, The oscillation circuit is stopped in the event of a long-term power outage resulting in overflow, thereby eliminating data loss due to discharge of the storage battery of the data memory. Therefore, during a long power outage, DC current is supplied from the storage battery only to the data memory. Therefore, according to this invention, it is possible to obtain the effect that data in the data memory can be secured even during a long power outage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional technique. 1...DC power supply, 10...Power failure detection circuit, 11
...Logic circuit, 12...Counter, 13...Flip-flop.

Claims (1)

[Scope of utility model registration request] In a memory backup device, a high frequency signal generated by an oscillation circuit is converted into a low frequency signal by a frequency dividing circuit, this low frequency signal is counted by a clock counter, and the counted clock signal is provided to a data memory. a power outage detection circuit that is connected to an AC power source and generates a binary signal of a energization signal and a power outage signal; a logic circuit that generates a count signal based on the power outage signal and the output signal of the frequency dividing circuit; A counter that starts counting, is reset by the energization signal, and generates a reset signal upon overflow; and an oscillation enable/stop that causes the oscillation circuit to oscillate by the energization signal and stops the oscillation circuit by the reset signal. A memory backup device comprising: a flip-flop that generates a signal; the oscillation circuit is stopped in the event of a long-term power outage in which the counter overflows, thereby eliminating data loss due to discharge of a storage battery of the data memory.