JPS6286419A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent malfunction of a CPU by providing a reset delay circuit generated from a system clock generating circuit and retarding the release of the reset state of the CPU until a system clock signal fed to the CPU rises normally. CONSTITUTION:An operating clock generated by an oscillation circuit 2 is given to a system clock generating circuit 4, from which a system clock signal is outputted. A reset delay circuit 8 is operated by using the system clock signal and the circuit 8 starts counting the system clock signal after the release of the external reset signal is detected and when the count reaches the setting value in the reset delay circuit 8, a reset delay signal is generated to a reset circuit 10. Thus, the reset circuit 10 releases the CPU 6 from the reset state to start the operation to the CPU. Thus, malfunction of the CPU due to unmatched system clock at application of power is not caused and stable operation of a semiconductor device is guaranteed.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an integrated circuit device that operates stably without being affected by power supply noise during power supply or irregular signals generated in a system clock system.

2. Description of the Related Art Conventionally, an integrated circuit device as shown in the block diagram of FIG. 2 has been used.

A conventional integrated circuit device will be described below.

2B - 21 is an integrated circuit device, 22 is an oscillation N-path that starts operating when the power is turned on, 23d is a system clock generation circuit that operates based on the operating clock from the oscillation circuit 22;
4d, CPU (Central P) to which the system clock from the system clock generation circuit 23 is supplied;
25 is a reset circuit, 26 is a terminal to which an external reset signal for operating the l-circuit 26 is applied, and 27 is a line to which a reset release signal output from the reset circuit 25 is applied.

In the integrated circuit device configured as described above, first, when the power is turned on, the oscillation circuit 22 operates, and this operation clock causes the system clock generation circuit 23 to operate, and the CPU 2
4 to supply the system clock. On the other hand, the reset circuit 25 is activated by an external reset signal applied to the terminal 26, outputs a reset release signal, and the CPU 24 starts operating.

Problems that the Invention Attempts to Solve 1- However, in the above-mentioned conventional configuration, the external 7-way signal is required asynchronously with the integrated 1-way device 21.

Each circuit starts the above-mentioned operation when the power is turned on. However, if an external reset signal is generated while the system clock signal has not reached a normal frequency, the integrated circuit device 21 has a problem in that the CPU 24 interferes with normal operation and causes abnormal operation.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide an integrated circuit device that releases the internal reset of the integrated circuit device after waiting for the rise of a system clock signal.

Means for Solving the Problems To achieve this object, the integrated circuit device of the present invention releases the reset state of the CPU when the system clock signal generated from the system clock generation circuit and supplied to the CPU rises normally. It has a reset delay circuit that delays the .

Function: With this configuration, the reset state is maintained as long as the system clock signal rises sufficiently, so that malfunctions of the CPU due to irregularities in the system clock signal can be prevented.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the main parts of a semiconductor device according to an embodiment of the present invention. 1 is an integrated circuit device, 2 is an oscillation circuit that operates when the power is turned on, 3 is a line to which the operating clock output from the oscillator circuit 2 is applied, 4 is the operating clock input, and line 6 is a system clock. System clock generation that generates a signal r! it road, 6 i:
CPU to which the system clock signal is supplied, 7-bit 1
The terminal 8 to which an external reset signal is applied is a set delay circuit which is activated by a system clock signal and generates a reset delay signal after a predetermined period of time after detecting that the external reset signal has not been released. . Note that this reset delay circuit is composed of a counter that counts system clock signals.

9 is a line to which the reset delay signal outputted from the reset delay circuit 8 is added, and 1o is a reset circuit that cancels the system reset signal by the reset delay signal 6 (Peno signal). 11 is a line to which a system reset signal is applied.

When the integrated circuit device of this embodiment configured as described above is powered on, the oscillation circuit 2 first starts operating. Next, the system clock generation circuit 4 outputs the operating clock generated by the oscillation circuit 2 as a system clock signal. Then, the reset delay circuit 8 is activated using the system clock signal. This reset delay circuit 8
starts counting the system clock signal after detecting that the external reset signal applied to the terminal 7 is released, and when the set value of the counter in the reset delay circuit 8 is reached, the reset circuit 1o generates a reset delay signal. . As a result, the reset circuit 1° releases the CPUe from the reset state and causes the CPU to start operating.

Note that the above-mentioned counter is set to the time required for the oscillation circuit 2 to stabilize to a normal oscillation state.

6 < In addition, if the time required for the oscillation output to rise after power-on is 16, and the time until the external reset signal is released is tH, then when the power is turned on, the integrated circuit device 1 under the condition tH>t6 can operate at the regular clock frequency. therefore,
After the power is turned on, the integrated circuit device 1 remains in a reset state until the system clock signal becomes sufficiently stable, so that it is not affected by power supply noise or the like when the power is turned on.

Effects of the Invention By providing the beam set delay circuit of the present invention, the input of the reset release signal can be delayed until the system clock signal rises normally, and malfunctions due to an irregular system clock when the power is turned on can be prevented.
This has the excellent effect of ensuring stable operation of the semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a block diagram of main parts of a conventional integrated circuit device base. 4...System clock generation circuit, 6...
...CPU, 8...Reset delay circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

[Claims] Consisting of a system clock generation circuit that generates a system clock signal to be supplied to the CPU, and a reset delay circuit that delays release of the reset state of the CPU until the system clock signal normally rises after the system clock starts operating. An integrated circuit device characterized by: