JP2867617B2 - Standby circuit - Google Patents

Description

The present invention relates to a standby circuit built in a microcomputer or the like.

[Prior Art] FIG. 5 is a circuit diagram showing a conventional standby circuit.

The RS flip-flop 13 is provided with a standby flag set instruction (SBF / SET instruction) supplied from a CPU (not shown).
And reset by an edge signal V _DDE when the power supply voltage V _DD rises. The Q output of the RS flip-flop 13 is supplied to an internal circuit as a standby flag SBF. On the other hand, the reset signal RES is supplied to the CPU via the reset terminal 2 as an internal reset signal RESI.

[Problems to be Solved by the Invention] However, in the above-described conventional standby circuit, since the reset signal RES and the standby flag SBF are irrelevant, if the reset is performed by the reset signal RES even in the standby state, the CPU is initialized. You. For this reason, there is a disadvantage that the program before the standby cannot be continuously executed when the standby is released. Therefore, conventionally, such a defect has been solved in a program. That is, when a reset is applied in the standby state, the standby flag SBF is checked in the initialization routine. If the standby flag SBF is at "1" level, the process jumps to the standby state release routine. If the standby flag SBF is at "0" level, It jumps to the original initialization routine. As described above, in order to prevent the CPU from being initialized only by releasing the standby state even after resetting, conventionally, it is necessary to create a program for that purpose, which is complicated. Another problem is that extra time is required to run this program.

The present invention has been made in view of such a problem, and it is possible to prevent the internal circuit of a microcomputer from being initialized when a reset is performed in a standby state without taking measures in a program. It is an object of the present invention to provide a standby circuit that can effectively exhibit essential functions in a computer or the like.

Means for Solving the Problems A standby circuit according to the present invention sets a standby state by a stop signal and releases the standby state by a reset signal, and delays an output of the state setting circuit by a set time. A delay circuit, a logical product detection circuit for detecting a logical product of an output of the delay circuit and a standby flag, a reset control circuit for controlling an internal reset signal by an output of the logical product detection circuit, and an output of the state setting circuit. And a clock control circuit for controlling the internal clock signal.

[Operation] In the present invention, the state setting circuit sets the standby state by the stop signal, and releases the standby state by the reset signal. In this standby state,
The clock control circuit prohibits the supply of the internal clock signal to the internal circuit by the output of the state setting circuit. Further, the output of the state setting circuit is delayed by a predetermined time by a delay circuit,
The logical product of the delay output of the delay circuit and the standby flag is detected in the logical product detection circuit. The reset control circuit prohibits the supply of the internal reset signal to the internal circuit by the output of the AND detection circuit when both the delay output and the standby flag are active.
As described above, even if the standby state is released by the reset signal, the delay output is supplied from the delay circuit to the AND detection circuit for a predetermined time. Within the delay time, the supply of the internal reset signal can be prohibited. Therefore, even if the reset is performed by the reset signal in the standby state, only the standby state is released, and the internal circuit of the microcomputer is not initialized. Thereby, the program before the standby state can be continuously executed.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a standby circuit according to a first embodiment of the present invention.

The RS flip-flop (hereinafter, also referred to as RS-FF) 3 is
It is set by a stop signal STOP supplied from a CPU (not shown), and is reset by an external reset signal RES input from a reset terminal 2. The Q output of RS-FF3 is supplied to the delay circuit 4 and the AND gate 9. The delay circuit 4 receives the Q output of RS-FF3, delays this signal by a predetermined time, and outputs the signal. The AND gate 6 includes a standby flag SBF supplied from a CPU (not shown) and a delay circuit 4.
Is output, and the AND of both is taken and output. The AND gate 7 receives the inverted phase signal of the output of the AND gate 6 and the external reset signal RES, controls the external reset signal RES according to the output of the AND gate 6, and outputs the internal reset signal RESI. This internal reset signal RESI is supplied to the CPU. The AND gate 9 is a negative-phase signal of the Q output of the RS-FF3 and an external clock signal supplied from the clock terminal 8.
CLK, and outputs the internal clock signal CLKI by controlling the external clock signal CLK according to the Q output of RS-FF3.
This internal clock signal CLKI is supplied to the CPU.

Next, the operation of the standby circuit according to the present embodiment thus configured will be described.

FIG. 2 is a timing chart showing the operation of the standby circuit shown in FIG.

First, when the standby flag SBF is "1" level, the output of the delay circuit 4 is at the "0" level, the output of the AND gate 6 is "0" level, the external at time t ₁ to t ₂ When the reset signal RES goes to “1” level, the internal reset signal RESI goes to “1” level, and the CPU is initialized. At time t ₃ to t ₅ is the standby flag SBF is "1" level, when the stop signal STOP becomes "1" level, the output of the RS-FF3 is "1" level, the output of the delay circuit 4 at time t becomes "1" level at ₄ to t _7. And
When the external reset signal RES between times t ₅ to t ₆ becomes "1" level, since RS-FF3 although is reset, the delay circuit 4 the output of the AND gate 6 remains "1" level, The internal reset signal RESI remains at “0” level, and the CPU is not initialized. A standby flag SBF is "1" level, to output the time t ₈ the RS-FF3
"1" level at t _10, the output of the delay circuit 4 at time t ₉ to t ₁₁ becomes "1" level. Therefore, the time t ₁₀ to t ₁₁
In this case, even if the external reset signal RES becomes "1" level, this external reset signal RES is suppressed by the output of the AND gate 6, so that the internal reset signal RESI becomes "0".
Become a level. However, the output of the delay circuit 4 is "0"
After time t ₁₁ to a level, for the AND gate 7 outputs become "0" level of the AND gate 6 is inputted to the phase inverted signal, the internal reset signal RESI becomes "1" level, CPU is initialized Is done.

Meanwhile, after the standby flag SBF becomes "0" level at time t _13, since the output of the AND gate 6 is always "0" level, the external reset signal RES becomes "1" level at time t ₁₅ Corresponding to this, the internal reset signal RESI is set to “1”
Level, and the CPU is initialized.

Further, the AND gate 9, when the output of the RS-FF3 is "0" level, outputs the internal clock signal CLKI, when the output of the RS-FF3 is "1" level, i.e., the stop state (time t ₃ to t ₅ does not output the internal clock signal CLKI at time t ₈ to t ₁₀ and time t ₁₃ to t _15). Therefore, in this stop state, the internal clock signal CLKI is not supplied to the CPU.

Thus, according to the present embodiment, the standby flag SB
When F is active, in the stop state (standby state) set by the stop signal STOP,
Even if the stop state is released by the reset signal RES, the internal reset signal RESI is not output within a predetermined time due to the delay output of the delay circuit 4. Therefore, even if you reset it,
The CPU is never initialized.

FIG. 3 is a circuit diagram showing a standby circuit according to a second embodiment of the present invention. In the present embodiment, a flip-flop is used in place of the delay circuit 4. Therefore, in FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the detailed description of those portions is omitted.

As shown in FIG. 3, the flip-flop 11 has its D
The Q output of the RS flip-flop (RS-FF) 3 is input to the terminal, the external clock signal CLK is input to the C terminal, and when the external clock signal CLK is at the "1" level, the Q output of the RS-FF3 is output. It is designed to latch.

FIG. 4 is a timing chart showing the operation of the standby circuit shown in FIG.

As shown in FIG. 4, when the standby flag SBF is at the “1” level and the output of the RS-FF3 is at the “1” level, the time t ₁₈ at which the external clock signal CLK is at the “0” level
Or to "1" level external reset signal RES at between t _19, the output of the flip-flop 11 remains external clock signal until CLK becomes "1" level "1" level. Therefore, during this period, the output of the AND gate 6 is at the “1” level, and the AND gate 7 does not output the internal reset signal RESI, so that the CPU is not initialized by the internal reset signal RESI. Other operations are the same as in the first embodiment.

[Effects of the Invention] As described above, according to the present invention, even if the standby state is canceled by the reset signal, if the standby flag is active, the supply of the internal reset signal is prohibited within the delay time of the delay circuit. can do. Therefore, even if the reset is performed in the standby state, the internal circuit of the microcomputer is not initialized. Therefore, a program for performing such an operation can be created and the program before the standby state can be continuously executed without running.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a standby circuit according to a first embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG.
FIG. 4 is a circuit diagram showing a standby circuit according to a second embodiment of the present invention, FIG. 4 is a timing chart thereof, and FIG. 5 is a circuit diagram showing a conventional standby circuit. 3,13; RS flip-flop, 2; reset terminal, 4; delay circuit, 6, 7, 9; AND gate, 8; clock terminal, 11; flip-flop

Claims (1)

(57) [Claims] 1. A state setting circuit for setting a standby state by a stop signal and releasing the standby state by a reset signal, a delay circuit for delaying an output of the state setting circuit for a predetermined time, an output of the delay circuit and a standby flag A logical product detection circuit that detects a logical product of the logical product and a reset control circuit that controls an internal reset signal by an output of the logical product detection circuit; and a clock control circuit that controls an internal clock signal by an output of the state setting circuit. A standby circuit, comprising: