JPH04277809A - Clock signal control circuit - Google Patents

Abstract

PURPOSE:To secure stable time when starting an oscillation circuit in the case of using a resonator, to eliminate useless waiting time for stabilizing oscillation when being supplied a clock pulse from the outside and to improve responsiveness. CONSTITUTION:A flip-flop 1 is provided as a first control circuit to control the operation of an oscillator 2 under the control of a stop signal and a reset signal. A counter 3 is provided to be initialized by the output of the flip-flop 1, to count the output signal of the oscillator 2 and to output an overflow signal after the lapse of set time. A power on reset type flip-flop 4 is provided as the second control circuit. A flip-flop 5 is provided as the third control circuit to control the operation of a clock signal generating circuit 6 under the control of the flip-flop 1 and the flip-flop 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal control circuit, and more particularly to a clock signal control circuit for an integrated circuit device having a clock signal generation circuit.

0002

2. Description of the Related Art In recent years, with the advancement of integrated circuit technology, high-density semiconductor integrated circuits (hereinafter referred to as LSIs) are rapidly becoming CMOS. Along with this, in order to take advantage of the low power consumption characteristics of CMOS, LSIs are placed in a non-operating state (standby).
LSIs have been developed that have a clock signal control circuit that sometimes stops the original oscillation of the clock signal generation circuit, prohibits the operation of internal circuits, and minimizes power consumption.

In particular, CMOS microcomputers (
Many microcomputers (hereinafter referred to as microcomputers) are equipped with the above-mentioned clock signal control function. In these microcomputers, it is common to set the clock signal control circuit to a standby state by executing instructions from the microcomputer using a user program.

[0004] These LSIs are applied to various electronic devices, and a plurality of LSIs are often used, for example, in microcomputers and gate arrays. In this case, each L
Since it is uneconomical to use a resonator in an SI, even if the LSI is equipped with an oscillation circuit, clock pulses are generally supplied from another LSI.

[0005] In the conventional clock signal control circuit, when canceling the standby state that was set on the premise of using the resonator and restarting the operation, the clock signal control circuit does not control the clock signal to the internal circuit during the stabilization time at the rise of the oscillation circuit. It was configured not to provide any signal.

[0006]

[Problems to be Solved by the Invention] In this conventional clock signal control circuit, the clock signal is stopped during the stabilization time at the rise of the oscillation circuit, so the clock pulse is supplied from the outside without using a resonator. Even in this case, the problem is that the response is poor because the device does not operate again until the oscillation stabilization time described above has elapsed.

[0007] The purpose of the present invention is to solve the above problems,
To provide a clock signal control circuit that can secure oscillation stabilization time when using a resonator, and can cancel a standby state without wasteful waiting time when receiving a clock signal from an external source. It is.

[0008]

[Means for Solving the Problems] A clock signal control circuit of the present invention includes an oscillation circuit using a resonator and a clock signal generation circuit that generates a clock signal based on an output signal of the oscillation circuit. In the control circuit,
a first control circuit that is controlled by an external control signal and a reset signal to control the operation of the oscillation circuit; and a predetermined count value that is initialized by the first control circuit and counts the output signal of the oscillation circuit. a counting circuit that outputs a counting signal when the count signal is reached, a second control circuit that controls the counting signal, and a third control that controls the operation of the clock signal generation circuit by the first and second control circuits. It is configured with a circuit.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock signal control circuit according to the present invention.

This embodiment shows an example in which the present invention is applied to a clock signal control circuit of a microcomputer.

The clock signal control circuit of this embodiment is shown in FIG.
As shown in FIG. 2, the circuit includes flip-flops 1, 4, and 5, an oscillator 2, a counter 3, a clock signal generation circuit 6, an inverter A1, and OR gates A2 and A3.

Flip-flop 1 is an RS flip-flop, and is set by a stop signal S, which is a stop command signal of the microcomputer, and reset by R, which is obtained by inverting a low active reset signal RI input from a reset terminal TR by an inverter A1. The output of the oscillator 2 controls the operation of the oscillator 2.

The counter 3 receives the oscillation output OSC of the oscillator 2.
is counted, and when a predetermined count value is reached after a certain period of time has elapsed, an overflow signal (OVF) is output.

The flip-flop 4 is a power-on flip-flop (POF) that is initialized to logic '0' when the power is turned on and is set by executing a specific instruction.

Flip-flop 5 is a set priority RS flip-flop, and the output of flip-flop 1 and
The output of OR gate A3 is input, and the operation of clock signal generation circuit 6 is controlled by the output.

The clock signal generation circuit 6 outputs clock signals CK1 and CK2 based on the output OSC of the oscillator 2.

Next, the operation of this embodiment will be explained.

FIG. 2 is a time chart for explaining the operation when using the resonator of the present invention, and the operation will be explained below using FIGS. 1 and 2.

First, the power is turned on at time t0, and when the reset signal RI becomes '0', the flip-flop 1, the counter 3, and the logic circuit inside the LSI are initialized. Further, the flip-flop 4 becomes '0'. Regardless of whether the flip-flop 5 is '0' or '1', the reset signal RI when the power is turned on is normally 10 to 10, which is necessary for stabilizing oscillation.
Although there is no particular problem since it is set to '0' for 50 ms, it is set to '1' for convenience of explanation. Therefore, even if the oscillator 2 oscillates, the clock signal generation circuit 6 is in a stopped state.

Next, at time t1, the reset signal RI becomes '1'.
' However, since the output of the flip-flop 5 is '1', the clock signals CK1 and CK2 are not output.

When the OVF signal of the counter 3 is output at time t2, the OR gate A3 becomes '1' and the flip-flop 5 is reset, so that the clock signals CK1 and CK
2 is output and the internal operation of the LSI starts.

When stop signal S is input at time t3, flip-flops 1 and 5 are set, oscillator 2 is stopped, counter 3 is initialized, and clock signals CK1 and CK2 are stopped. For this reason, LSI
The power consumption of is minimized.

When the reset signal RI becomes '0' at time t4, the flip-flop 1 is reset and the oscillator 2 operates. When the reset signal RI becomes '1', the counter 3
operates and after counting a predetermined number, that is, time, the time t
5, the OVF signal is output, the flip-flop 5 is reset, and the clock signals CK1 and CK2 are output.

In this way, the output P of the flip-flop 4
By setting OF to '0', it is possible to secure the oscillation stabilization time when using a resonator, and therefore the LSI
reliable operation is possible.

Next, the case where clock pulses are supplied from the outside will be explained using FIG.

Here, only the differences from FIG. 2 described above will be explained. First, at time t6, the flip-flop 4 is set by a command signal.

Next, at t7, in order to set the standby state, when the stop signal S is output, the flip-flops 1,
5 is set, the output OSC of the oscillator 2 and the clock signals CK1 and CK2 are stopped, and power consumption becomes minimum. Here, the output POF of the flip-flop 4 is '1' and the output of the OR gate A3 is also '1', but the output of the flip-flop 5 remains '1' due to set priority.

When the reset signal RI becomes '0' at time t8, the outputs of the flip-flops 1 and 5 immediately become '0', and the oscillator 2 and clock signal generation circuit 6 operate to output clock signals CK1 and CK2. do. For this reason,
There is no wasted oscillation stabilization time, and the reset signal RI is '1'.
Immediately, the internal operation of the LSI becomes effective.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be modified in various ways.

For example, instead of a power-on flip-flop that is initialized to logic ``0'' when the power is turned on, the output logic value may be set to ``1'' when receiving a clock pulse from an external source, or a resonator. It goes without saying that in the case of using , a ROM each set to '0' by a photomask can be used as long as it does not depart from the spirit of the present invention.

[0032]

[Effects of the Invention] As explained above, the clock signal control circuit of the present invention secures the stabilization time at the rise of the oscillation circuit when using a resonator, and when receiving clock pulses from an external source. This has the effect of eliminating unnecessary waiting time for oscillation stabilization and improving responsiveness.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a clock signal control circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation when using a resonator in the clock signal control circuit of this embodiment.

FIG. 3 is a time chart showing an example of the operation of the clock signal control circuit of the present embodiment when receiving a clock pulse from the outside.

[Explanation of symbols]

1, 4, 5 Flip-flop 2 Oscillator 3 Counter 6 Clock signal generation circuit A1 Inverter A2, A3 Or gate

Claims (1)

[Claims] 1. A clock signal control circuit comprising an oscillation circuit using a resonator and a clock signal generation circuit that generates a clock signal based on an output signal of the oscillation circuit. a first control circuit that is controlled and controls the operation of the oscillation circuit; and a first control circuit that is initialized by the first control circuit and counts the output signal of the oscillation circuit and outputs a count signal when a predetermined count value is reached. It is characterized by comprising a counting circuit, a second control circuit that controls the counting signal, and a third control circuit that controls the operation of the clock signal generation circuit by the first and second control circuits. Clock signal control circuit.