JPH0289137A - Restarting device for microprocessor - Google Patents

Abstract

PURPOSE:To secure fail-safe by providing a delay circuit and a logical circuit and stopping a microprocessor by means of continuous light abnormality which occurs in a short time. CONSTITUTION:The delay circuit 1 delays a reset signal (a) for a fixed set time. When the light abnormality detection signal (e) of the microprocessor, which is detected in an abnormality detection circuit 7, can be obtained within the time which is set in the delay circuit 1, it is assumed to be the occurrence of light abnormality which is not accidental in the microprocessor since the output signal (d) of FF3 is turned off. The AND of the inverse signal of the output signal (d) from FF3 and the light abnormality detection signal (e) is taken in an AND gate 6b, and the stop signal (f) of the microprocessor is outputted to the output terminal. Thus, the microprocessor can be stopped and the safe operation of the microprocessor can be secured.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a microprocessor restarting device that determines a minor abnormality in a microprocessor to be an accidental abnormality and restarts the microprocessor when a slight abnormality occurs after a certain period of time has elapsed.

[Conventional technology]

FIG. 3 is a block connection diagram of a circuit implementing the conventional microprocessor restart method disclosed in, for example, Japanese Patent Publication No. 62-6262. In the figure, l is a delay circuit;
2 is a differential circuit, 3 is a flip-flop circuit (hereinafter referred to as FF)
), and between this FF3 and the differentiating circuit 2,
A logic circuit 4 is inserted. In the logic circuit 4, 4a and 4b are Nant gates;
c and 4d are sot circuits. Next, the operation will be explained. FIG. 4 is a time chart showing the operation of the microprocessor restart method shown in FIG. A microprocessor reset signal I as shown in FIG. 4(a) is input to the terminal B of the delay circuit l. This reset signal A is delayed by a delay circuit 1, and outputted to its output terminal as a delayed signal port as shown in FIG. And, at the output end, there is a
) The output signal C appears as shown in (). At this time, even if the abnormality detection signal 2 occurs, if it recovers in a short time, there is no abnormality in the operation of the microprocessor, so the output signal C of the Nant gate 4a in FIG. It is not obtained at the output side of the NOT circuit 4c, therefore, the FF3 is not operated, and there is no change in the output signal of the FF3 (FIG. 4(f)). Furthermore, if there is an abnormality in the operation of the microprocessor and the abnormality detection signal 2 is output continuously as shown by the dotted line in FIG.
The logical product of a and the output signal c is taken by the Nantes gate 4b,
By inverting the output with the knot circuit 4c, F
A signal shown by a dotted line in FIG. 4(e), which is the output signal of the Nant gate 4a, is added to the set input terminal A of F3,
At the output terminal of the FF 3, an output shown by a dotted line in FIG. 4(f) appears, and this output signal is simultaneously fed back to the input terminal B of the delay circuit 1. The microprocessor is reset (restarted) again by the circuit shown in FIG. 3 if an abnormality is detected within a certain period of time after being reset.

[Problem to be solved by the invention]

Conventional microprocessor restart methods are implemented as described above. There were problems such as accidental abnormalities not being subject to restart. This invention was made to solve the above-mentioned problems, and when a minor abnormality detection signal occurs accidentally, the microprocessor is restarted, and continuous abnormality detection signals that occur within a short period of time are The present invention aims to provide a microprocessor restart device capable of stopping the microprocessor when a serious abnormality occurs or when a serious abnormality occurs.

[Means to solve the problem]

A microprocessor restart device according to the present invention delays a microprocessor reset signal by a delay circuit for a certain period of time, resets a flip-flop circuit using the output signal of the delay circuit, and outputs a microprocessor restart permission signal. On the other hand, a logic circuit is provided to stop the microprocessor when a minor abnormality detection signal of the microprocessor is generated within the set time of the delay circuit or when a major abnormality occurs, and the signal is generated after the delay time of the delay circuit has elapsed. The configuration is such that the microprocessor is restarted in the case of a minor abnormality detection signal.

[For use]

The delay circuit in this invention outputs a microprocessor reset signal with a certain period of time delay, sets a flip-flop circuit, outputs a microprocessor restart permission signal from the flip-flop circuit, and outputs a microprocessor reset signal within a certain period of time after resetting the microprocessor. If a minor abnormality detection signal is not generated from the abnormality detection circuit, the logic circuit creates a permission condition for restarting the microprocessor. It operates to stop the microprocessor when a serious abnormality detection signal is generated.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, l is a delay circuit that delays the reset signal of the microprocessor for a certain period of time. 2
is a differentiation circuit that differentiates the output of the delay circuit 1; 5 is a NOT circuit that inverts the output of the differentiation circuit 2, that is, the pulse; 3 is an FF, and the output of the NOT circuit 5 is introduced into the set input terminal A; Outputs a restart permission signal for the microprocessor. 6 is a logic circuit. Further, 6a is a component of the logic circuit 6, and is a NOT circuit that inverts the output signal of the FF3, 6b and 6c are AND gates, each of which is a component of the logic circuit 6, and 6d is also a component of the logic circuit 6. It is eggplant or gate. The AND gate 6b performs the logical product of the output of the NOT circuit 6a and the microprocessor's minor abnormality detection signal output from the abnormality detection circuit 7, and the AND gate 6b calculates the logical product of the output of the NOT circuit 6a and the microprocessor's minor abnormality detection signal outputted from the abnormality detection circuit 7. When one occurs, it produces an output that causes the microprocessor to stop. Further, the AND gate 6c performs a logical product of the output signal of the FF3 and the minor abnormality detection signal, and the minor abnormality detection signal is output from the delay circuit l.
This system outputs a signal that restarts the microprocessor based on an accidental signal that occurs after a predetermined set time has elapsed. Furthermore, the OR gate 6d is for immediately stopping the microprocessor in the event of a serious abnormality. 7 is an abnormality detection circuit that detects an abnormality in the microprocessor. For example, in the case of an abnormality that prevents the microprocessor from operating further, such as loss of the microprocessor operating clock or power cut to the microprocessor, a serious abnormality signal is generated. In contrast, in the case of an abnormality that occurs during switch operation (invalid address, writing to ROM), external memory abnormality, or other peripheral device abnormality, a minor abnormality signal is output. Output. Next, the operation will be explained. FIG. 2 is a time chart for explaining this operation, and the explanation will be made using FIG. 2 together. When the reset signal A of the microprocessor as shown in FIG. A delayed signal port as shown in Figure (b) is output. This delay signal port is differentiated by a differentiating circuit 2 to generate a pulse that falls at the rising edge of the delay signal port, and this pulse is inverted by a knot circuit 5 to produce a pulse as shown in FIG. 2(C). Become. This pulse C sets FF3 and generates an output signal 2 as shown in FIG. 2(d). This output signal 2 is a restart permission signal for the microprocessor. Now, in the case where the microprocessor's minor abnormality detection signal detected by the abnormality detection circuit 7 is obtained within the time set by the delay circuit 1, the minor abnormality detection signal H is as shown in FIG. 2(e). Since the output signal 2 of FF3 is off at this time, it is assumed that a non-accidental minor abnormality has occurred in the microprocessor. This FF3 output signal 2 (off) is Antogame 1-6c
is applied to one input terminal of the knot circuit 6a.
After being inverted at , it is also applied to one input terminal of AND gate 6b. And gate 6b. A slight abnormality detection signal E from an abnormality detection circuit 7 is applied to the other input terminal of 6C. The AND gate 6c performs the logical product of the output signal 2 of the FF3 and the minor abnormality detection signal H, and since the output signal 2 is off, the reset signal of the microprocessor is not output, but the AND gate 6b The inverted signal of the output signal 2 of the FF3 and the abnormality detection signal H are ANDed, and the output terminal of the AND gate 6b is outputted to the stop signal of the microprocessor as shown in FIG. 2(f). '3. ．． This causes the microprocessor to stop operating. In addition, the light abnormality detection signal T generated after the elapse of a certain period of time set by the delay circuit 1 (Fig. 2 (g))
In this case, the output signal 2 of FF3 is shown in Fig. 2(d).
Since it is on, its output signal 2 is the ant game.
The signal is applied as is to one input terminal of t-6c, but since the signal inverted by the NOT circuit 6a is applied to one input terminal of AND gate 6b, the output terminal of AND gate 6b receives a stop signal. or is not output, AND gate 6c
As shown in Figure 2 (h), the light abnormality detection signal and FF3
The logical product of the output signal 2 and the output signal 2 is taken to output a reset signal Q, and this reset signal Q restarts the microprocessor. If a minor abnormality detection signal occurs continuously after an accidental minor abnormality occurs, it will be treated as a non-accidental abnormality after restarting. Minor abnormalities with a high value can also be targeted for microprocessor shutdown. Further, when a serious abnormality occurs, the abnormality detection circuit directly outputs a serious abnormality detection signal to the game (or game) 6d, so that the microprocessor is immediately stopped regardless of the logic when the above-mentioned minor abnormality occurs. In the above embodiment, the positive logic delay circuit 1, FF3,
Although the differential circuit 2 with negative logic is used, these may be of opposite logic or may be a mixture thereof. Furthermore, in the above embodiment, the microprocessor's reset signal is used as the reset condition for the flip-flop circuit 3, but the reset condition may be created by combining it with the microprocessor's stop signal, or the microprocessor's reset signal can be used as the microprocessor's reset signal. A condition that the processor is not stopped may be added, and the same effect as in the above embodiment can be obtained. Furthermore, the delay circuit 1 may be prohibited from integrating time when the microprocessor is stopped, and the same effect as in the above embodiment can be obtained.

【Effect of the invention】

As described above, according to the present invention, an abnormality in a microprocessor is detected by the abnormality detection circuit as a minor abnormality and a major abnormality, and if a minor abnormality does not occur within a certain set time after resetting the microprocessor, the microprocessor Create permission conditions for restarting the processor, treat minor abnormalities that occur in the future as accidental, and restart the microprocessor; conversely, if an abnormality occurs within a certain period of time, the microprocessor will be stopped. With this configuration, continuous minor abnormalities that occur within a short period of time can be resolved by stopping the microprocessor.
There is something that can ensure the fail-safe operation of this microprocessor, increase the operating rate of this microprocessor, and also be able to stop the microprocessor in the event of a major abnormality regardless of whether it is a minor abnormality, thereby ensuring safe operation of the microprocessor. There are benefits to be gained.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram showing a microprocessor restart device according to an embodiment of the present invention, FIG. 2 is a time chart showing signals of each part of the block in FIG. 1, and FIG. 3 is a conventional microprocessor restart device. FIG. 4 is a block connection diagram showing a circuit implementing the starting method, and a time chart showing signals of each part of the block in FIG. 3. 1 is a delay circuit, 3 is a flip-flop circuit, 6 is a logic circuit, and 7 is an abnormality detection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1

Claims (1)

[Claims] A delay circuit that delays the reset signal of the microprocessor for a certain period of time; a flip-flop circuit that is reset by the output signal of this delay circuit and outputs a restart permission signal for the microprocessor; An abnormality detection circuit that detects abnormalities separately, and when a minor abnormality detection signal of the microprocessor occurs within the certain period of time or when the serious abnormality occurs, the microprocessor is stopped; and a logic circuit for restarting the microprocessor based on a restart permission signal of the flip-flop circuit when the detection signal is generated after the predetermined time has elapsed.