JPH06195160A - External interruption edge detecting circuit for microcomputer - Google Patents

Abstract

PURPOSE:To reduce the number of parts and power consumption required for external interruption edge detection by standing by a microcomputer in a stop mode at the time of an external interruption waiting state. CONSTITUTION:When any interruption factor occurs, a first edge generating part 11 generates an external interruption signal having a slow rising/falling edge for the interruption request. This external interruption signal is inputted to the interruption terminal of a microcomputer 10 and a second edge generating part 12. The second edge generating part 12 detect the external interruption signal sent from the first edge generating part 11 becomes to a prescribed threshold value, and outputs a pulse signal to a start input generating part 13. Based on this output pulse, the start input generating part 13 generates a start input signal and inputs it to the start terminal of the microcomputer 10. When prescribed processing is finished, the microcomputer 10 is set to an operation stop state by a stop mode function and on the other hand, an external interruption recognizing function is activated inputting the start input signal to release the stop state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external interrupt detection circuit for a microcomputer such as an ASIC having a stop mode function and an external interrupt recognition function.

[0002]

2. Description of the Related Art FIG. 4 shows an ASIC microcomputer system having a stop mode function and an external interrupt recognition function. In FIG. 4, reference numeral 1 is an interrupt factor generation unit, and an ON / OFF signal of a switch becomes an interrupt factor signal. This interrupt factor signal is input to the edge generation unit 2 ′ via the chattering prevention circuit 6 that absorbs chattering generated in the switch. The edge generator 2'generates an external interrupt signal 'having a steep rising / falling edge with respect to the interrupt factor signal and inputs it to the interrupt terminal of the ASIC microcomputer 4.

Reference numeral 5 denotes a start input generation section which generates a start input signal in response to a start request from each functional block (not shown) (controlled by the microcomputer 4) and inputs it to the start terminal of the microcomputer 4.

The microcomputer 4 comprises a standby canceling section 42, a CPU core 43, a clock control section 44, an interrupt detecting section 45 and the like. The CPU core 43 normally operates by receiving the clock for the CPU from the clock control unit 44, but when the required processing is completed, the CPU core 43 automatically shifts to the standby mode (also referred to as stop mode). In this standby mode, the CPU core 43 is instructed to stop the clock supply to the clock control unit 44.
To stop power consumption while receiving a standby release request from the standby release unit 42, the clock standby release request is issued to the clock control unit 44, and the clock control unit 44 returns the clock It is designed to start operating after receiving supply. When the clock control unit 44 receives this clock standby release request, it operates so as to restart the supply of the clock after a predetermined oscillation stabilization wait time has elapsed.

The external interrupt recognition section (or external interrupt macro) 41 detects a level change between H / L of the external interrupt signal from the edge generation section 2 ', and when there is a level change, recognizes it as an external interrupt. This is a part that outputs an interrupt request to the CPU core 43. The external interrupt recognizing unit 41 operates by receiving the internal clock supply from the CPU core 43 while the CPU core 43 is operating, but when the CPU core 43 stops operating, the internal clock supply is stopped and the operation thereof is stopped. Is supposed to stop.

In this microcomputer system, when the interrupt factor signal is generated by the interrupt factor signal generator 1, the interrupt factor signal is input to the edge signal generator 2'through the chattering prevention circuit 6 and the external interrupt signal is generated here. The signal 'is generated and input to the external interrupt recognition unit 41 of the microcomputer 4, and an interrupt request is generated and input to the CPU core 43 by detecting the level change, and the CPU core 43 starts the interrupt processing. . In this interrupt processing, the interrupt processing is performed again when the generation of the interrupt factor signal is stopped (that is, when the original level is changed again).
When the U core 43 is in the operation stop state, the external interrupt recognition unit 4
Since 1 also stops the supply of the internal clock and is in an operation stop state, the latter interrupt cannot be recognized. Therefore, for the interrupt factor signal, while it is being output,
The CPU core 43 continues to operate.

[0007]

In the conventional ASIC microcomputer system, in order to prevent chattering in the input to the edge generator 2 ', the chattering prevention circuit 6 is required in the preceding stage, and the chattering prevention circuit 6 is required. , The number of parts increases. Further, the external interrupt signal output from the edge generator 2'may cause a malfunction if the rising / falling edge is slow, so it is necessary to make the edge steep. For that purpose, the edge generator 2 ' Since it is necessary to flow a certain amount of current inside the ', power consumption in the edge generation unit 2'becomes large. Further, the CPU core 43 cannot stop its operation while the external interrupt signal is being output.
Also in No. 3, there is unnecessary power consumption.

The present invention has been made in view of the above problems, and an object thereof is to reduce the number of parts and power consumption required for detecting an external interrupt edge.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. The external interrupt edge detection circuit of the microcomputer 10 having the stop mode function and the external interrupt recognition function of the present invention generates the external interrupt signal having the rising / falling edge which is slow with respect to the interrupt factor to generate the external interrupt signal of the microcomputer 10. A first edge generation unit 11 that inputs to an interrupt terminal and a second edge generation that detects that an external interrupt signal from the first edge generation unit 11 has reached a predetermined threshold value and outputs a pulse signal Part 12 and
And a start input generation unit 13 for generating a start input signal based on the output pulse of the second edge generation unit 12 and inputting the start input signal to the start terminal of the microcomputer 10.
The stop mode function sets the microcomputer 10 to an operation stop state when a predetermined process is completed. When the start input signal is input, the microcomputer 10 releases the stop state and activates the external interrupt recognition function. The external interrupt recognition function recognizes an external interrupt by comparing the level of the interrupt terminal before the stop state and the level of the interrupt terminal when the microcomputer resumes operation.

[0010]

When the interrupt factor occurs, the first edge generator 1
1 generates an external interrupt signal having a slow rising / falling edge in response to the interrupt request. This external interrupt signal is input to the interrupt terminal of the microcomputer 10 and the second edge generator 12. The second edge generation unit detects that the external interrupt signal from the first edge generation unit 11 has reached a predetermined threshold value and outputs a pulse signal to the start input generation unit 13. Start input generator 1
3 generates a start input signal based on the output pulse of the second edge generator 12 and inputs it to the start terminal of the microcomputer 10. Microcomputer 10
When the predetermined processing is completed by the stop mode function, the microcomputer 10 is set to the operation stop state,
On the other hand, when the start input signal is input, the stop state is released and the external interrupt recognition function is activated. When activated, the external interrupt recognition function compares the level of the interrupt pin before the stop state with the level of the interrupt pin when the microcomputer resumes operation, and if the two differ, the level change is regarded as an external interrupt. Then, an interrupt request is issued to the microcomputer 10.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an external interrupt edge detection circuit of an ASIC microcomputer system according to an embodiment of the present invention. In FIG. 2, reference numeral 1 denotes an interrupt factor generator, which is composed of switches and the like as in the conventional example. Reference numeral 2 denotes an edge generation unit, which is a circuit for generating an external interrupt signal having an edge with respect to the interrupt factor signal from the interrupt factor generation unit 1. / The falling edge is gentle, so that the current flowing through the transistor of the edge generation unit 2 may be a small current. The external interrupt signal from the edge generator 2 is input to the interrupt terminal of the microcomputer 4 and the edge generator 3.

The edge generator 3 includes a resistor R, a capacitor C, a Schmitt circuit, an exclusive OR circuit, etc., and the level of the interrupt factor signal from the edge generator 2 exceeds a predetermined threshold value. When it falls below, it operates so as to generate and output a pulse signal of a constant width. This pulse signal is input to the start input generation unit 5.

The start input generator 5 is adapted to generate a start input signal for a pulse signal in the same manner as when a start input request is made from another functional block. It is input to the standby canceling unit 42 via the start terminal of.

The external interrupt recognition unit 41, the standby release unit 42, and the CPU core 4 in the microcomputer 4
3. The operation of the clock control unit 44 is almost the same as that described above, but the CPU core 43 performs the interrupt processing for the interrupt request from the external interrupt recognition unit 41 and automatically stops the operation when the processing ends. A standby mode (also referred to as a standby mode) that continues the stopped state until a standby release request is input from the standby release unit 42 is set. That is, the microcomputer 4 is made to wait in the stop mode when waiting for an external interrupt.

The operation of this embodiment circuit will be described below with reference to the time chart of FIG. In FIG.
(A) is an interrupt factor signal from the interrupt factor generator 1,
(B) is an external interrupt signal from the edge generator 2,
(C) shows a pulse signal from the edge generation unit 3, (d) shows an operation mode of the CPU core 43 in the microcomputer 4, and (e) shows an interrupt request from the external interrupt recognition unit 41.

When the interrupt factor generator 1 generates the interrupt factor signal, the edge generator 2 generates an external interrupt signal which rises / falls at the on / off change point of the interrupt factor signal. This external interrupt signal becomes gentle with its rising / falling edges having a time constant. When the rising edge of the external interrupt signal exceeds a predetermined threshold value, the edge generation unit 3 generates a pulse signal having a constant width and inputs this to the start input generation unit 5. In response to this, the start input generation unit 5 generates a start input signal and inputs it to the standby canceling unit 42 of the microcomputer 4. As a result, the standby canceling unit 42 issues a standby cancel request to the CPU core 43.

The CPU core 43, which has been in the stop mode until then, receives the standby release request from the standby release unit 42, releases the stop mode, and issues a clock standby release request to the clock control unit 44. As a result, the clock control unit 44 supplies the clock to the CPU core 43 after a predetermined oscillation stabilization wait time (for example, about 10 mS) has elapsed. Then, the CPU core 43 restarts the operation and supplies the internal clock to the external interrupt recognition unit 41 to operate it.

The external interrupt recognizing unit 41 is in the stop mode and is in a standby state in the standby state before the stop (the level state of the external interrupt signal is "L" level in the example of FIG. 3) before the stop.
After the operation is started, the level of the interrupt terminal at that time (“H” level in the example of FIG. 3) is monitored. The level of this interrupt terminal, that is, the level of the external interrupt signal does not change from "L" to "H" rapidly, but after the oscillation stabilization wait time has passed, the microcomputer 4
Has changed to "H" when the operation is restarted, the external interrupt recognition unit 41 recognizes a pseudo edge by comparing the level before the stop and the monitored level to detect the level change, and Issues an interrupt request to the CPU core 43. When the CPU core 43 receives the interrupt request, the CPU core 43 performs the interrupt process, and automatically shifts to the stop mode when the predetermined interrupt process is completed.

Next, when the external interrupt signal falls, when the level falls below a predetermined threshold value, the edge generator 3 outputs a pulse signal of a constant width to the start input generator 5, and in the same manner as described above. The start input signal is input to the standby canceling section 42 via the start terminal of the microcomputer 4, and the CPU core 43 shifts from the stop mode to the operation mode again.

With the configuration of the above-described embodiment, the rising edge / falling edge of the external interrupt signal output from the edge generating section 2 is slow, so that even if a chattering prevention circuit is not provided in the preceding stage, The influence of chattering generated in the interrupt factor generation unit can be removed. Further, since the microcomputer 4 does not need to operate for the entire period, its power consumption can be reduced. Further, the edge of the output signal of the edge generator 2 does not have to be steep, and the current flowing through the transistor can be made small, so that the power consumption of the edge generator 2 can be reduced.

[0021]

As described above, according to the present invention, the number of parts used can be reduced by reducing the scale of peripheral circuits such as the need for a chattering prevention circuit. Moreover, since the ASIC microcomputer is normally in the stop mode, its power consumption can be reduced, and it is not necessary to sharpen the interrupt edge in the edge generation unit.
The edge generator does not need to supply a large current, and the power consumption can be reduced accordingly.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing an external interrupt edge detection circuit of a microcomputer as one embodiment of the present invention.

FIG. 3 is a time chart of signals of respective parts of the embodiment circuit.

FIG. 4 is a diagram showing a conventional example.

[Explanation of symbols]

 1 Interrupt factor generation unit 2, 2 ', 3 edge generation unit 4 ASIC microcomputer 5 Start input generation unit 6 Chattering prevention circuit 7 Original oscillator 41 External interrupt recognition unit 42 Standby release unit 43 CPU core 44 Clock control unit Interrupt factor signal external Interrupt signal Pulse signal Standby release request Clock Standby release request Clock Internal clock Interrupt request Start input signal

Claims (1)

[Claims] 1. An external interrupt edge detection circuit for a microcomputer (10) having a stop mode function and an external interrupt recognition function, which generates an external interrupt signal having a slow rising / falling edge with respect to an interrupt factor. A first edge generator (11) for input to the interrupt terminal of the microcomputer, and a pulse signal when it is detected that the external interrupt signal from the first edge generator has reached a predetermined threshold value. And a start input generator (13) for generating a start input signal based on the output pulse of the second edge generator and inputting the start input signal to a start terminal of the microcomputer. The stop mode function sets the microcomputer to an operation stop state when a predetermined process is completed. When the start input signal is input, the black computer releases the stop state and activates the external interrupt recognition function. The external interrupt recognition function is the level of the interrupt terminal before the stop state and the microcomputer. An external interrupt edge detection circuit of a microcomputer adapted to recognize an external interrupt by comparing the level of the interrupt pin when the operation is restarted.