JPS61224438A - Wiring pattern configuration for semiconductor device - Google Patents

Abstract

PURPOSE:To relax the concentration of stress to the cross parts of the upper and lower wiring patterns and to suppress the generation rate of crack by a method where- CONSTITUTION:A lower wiring pattern Al-I and an upper wiring pattern Al-II, which is provided on the lower wiring pattern Al-I through an interlayer insulating film.

Description

Detailed Description of the Invention [Summary] The present invention provides that when a semiconductor chip is encapsulated with a resin, the difference in thermal expansion between the resin and the semiconductor chip causes interlayer damage, especially at the intersection between the lower layer aluminum wiring and the upper layer aluminum wiring around the chip. This is to improve the problem of short circuits between wirings caused by troughs in the insulating film, and the edges of the wiring patterns in the lower and upper layers are now at an obtuse angle at the intersection, rather than at right angles as in the past. This eliminates stress concentration at the intersection and suppresses the occurrence of tarawak.

[Industrial application field]

The present invention relates to a semiconductor chip having lower and upper layer wiring patterns.

[Prior art]

Generally, when a two-layer Aβ wiring pattern is provided on the surface of a semiconductor chip, for example, the lower layer has only the horizontal direction, and the upper layer has only the vertical direction, and their intersections are perpendicular to each other with interlayer insulation such as a PSG film interposed therebetween. When the lower layer wiring and the upper layer wiring intersect perpendicularly, the side wiring pattern is usually a band-like pattern, so even if you pay attention to both edges, the edges of the upper and lower layers are still orthogonal.

[Problem that the invention seeks to solve]

When such a semiconductor chip is sealed with a resin, there is a problem in that stress from the resin is applied to the interlayer insulating film, causing cracks, because the thermal expansion coefficients of the resin covering the chip surface and the semiconductor chip are significantly different. This crank occurs at the periphery of the chip where the above-mentioned stress is greatest, and at the intersection of the lower layer and upper layer wiring patterns where there is a step on the surface.

FIG. 2 shows an overall view of a conventional chip and schematically shows the direction in which cracks and cracks occur. It has been confirmed that cracks 6 occur in the peripheral portion of the chip 2 in a direction perpendicular to a line extending from the chip center 4 to the outside.

Furthermore, as shown in Figure 3, the crank is mainly connected to the lower wiring A.
This occurs at the intersection of the upper layer wiring Al-2 and the upper layer wiring Al-2, and particularly occurs at the intersection of both pattern edges in a direction perpendicular to the line extending outward from the chip center 4. Therefore, even in the periphery of the chip, the locations where kralev occurs are different between the left and right sides.

Although the cause of the occurrence of such racks has not yet been elucidated, the inventors of the present invention have considered the following.

Figure 4 is a plan view, Figure 5 is a perspective view, Figure 6 is A of Figure 5.
-A' cross-sectional view is shown. As shown in FIG. 6, lower layer wiring A1-1. There are an interlayer PSC insulating film 10, an upper layer wiring A, a cover insulating film 12, and a sealing resin 14 thereon. As shown in this cross-sectional view, there is a difference at the intersection of the upper and lower wiring, and it is thought that the stress F from the sealant will be applied to the difference and the crank 6 will enter the interlayer insulating film 10 as shown in the figure. It will be done. This stress is applied in the direction toward the center of the chip. It has been confirmed that this crack 6 causes a short circuit between the upper and lower wiring An-1°.

The cause of this crank is probably that the upper and lower layer wirings intersect, especially at the intersection 16 of the pattern edge.
It is thought that cranking in the direction shown in FIG. 2 occurs because stress is concentrated on the step caused by the lower wiring and the stress direction is toward the center of the chip.

That is, as shown in Fig. 4.5, the stress on the intersection 16 is due to stress F2 applied to the surrounding lower layer wiring An-1 and stress F3 applied to the upper layer wiring A#-1 in addition to Fl. The component element in the direction of the wiring edge that is generated! Ifs+ is considered to be concentrated at the intersection 16. One of the reasons may be that the intersection 16, which is the stress concentration point, has the largest step difference because two layers of wiring overlap, and the cover insulating film there is weak. Furthermore, the stress along the edge f phantom, f31 is PSGIo,
Since it is applied in the direction of twisting with respect to 12, the influence is thought to be large.

[Means for solving problems]

The present invention aims to suppress the occurrence of cracks, which are the above-mentioned problems, and eliminate short circuits between the upper and lower wires. Nevertheless, the idea is to create a pattern so that the intersections form obtuse angles.

[Effect]

By making the angle obtuse in this way, it is thought that the above-mentioned concentration of stress at the intersection is alleviated and the occurrence of cranks is suppressed. In particular, this obtuse angle may be an obtuse angle with respect to an angle that includes a line extending outward from the center point of the chip. This is because the stress is in the direction along that line.

〔Example〕

FIG. 1 shows the configuration of the present invention, FIG. 7 shows its detailed view, and FIG. 8 shows a wiring pattern diagram of each part of the entire chip.

As shown in FIG. 1, first of all, the lower layer wiring Al-■ and the upper layer wiring An! -It are substantially orthogonal. In this example, the upper layer wiring An-If is straight in the horizontal direction, and the lower layer wiring A1-I runs substantially in the vertical direction, as is clear from the direction of the upper layer 20 and lower layer 22, so that both of them are substantially straight. are orthogonal to each other.

Second, the edge 24 of the lower wiring pattern Aβ-■ and the edge 26 of the upper wiring pattern AI-U intersect at an obtuse angle θ at the intersection. This can be achieved by bending the edge of either the upper layer or the lower layer; in the example shown in FIG. 7, the upper layer side is bent.

Third, the obtuse angle θ is an angle that includes a line 28 extending outward from the chip center 6. This is because the stress is in the direction of the line 28, so stress concentration associated with this is alleviated.

S Incidentally, reference numeral 18 denotes a parapet, which is provided at the periphery of the chip 2.

This is due to the fact that stress-induced cranks tend to occur in the peripheral areas.

The inventors' idea as to why stress concentration is alleviated will be explained with reference to FIG. Figure 7 shows the stress Fl
, F2, and FJ are shown in the same manner as in FIG.
It is thought that this will eliminate the components that are directed toward the target, and as a result, the concentration will be alleviated.

FIG. 8 shows an embodiment of the present invention for each peripheral portion of the entire chip 2. In FIG.

In the left peripheral part 30, center peripheral part 32, and right peripheral part 34, the directions of the obtuse angle θ are different because the lines (not shown) extending outward from the chip center point 6 are different.

In the above embodiment, the upper layer and the lower layer completely intersect, but for example, when the lower layer wiring is connected to the diffusion layer of the substrate directly under the upper layer wiring and the lower layer 22 of the lower layer wiring does not exist, both wirings may cross each other. are assumed to substantially intersect and fall within the scope of the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the concentration of stress on the intersection portion 16 is alleviated, thereby making it possible to suppress the occurrence rate of cranks occurring at that portion.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of the present invention, Fig. 2 is a plan view showing the entire conventional chip and the crank direction, Fig. 3 is a plan view showing the conventional two-layer wiring pattern and the crank, and Fig. 4 is the conventional pattern. 5 is a perspective view of the crank, FIG. 6 is a sectional view of the same, and FIG. 7 is a plan view of an embodiment of the present invention.
FIG. 8 is a plan view showing an example of the same location. 2 in the figure ----1. Semiconductor chip A#-I
-----...Lower wiring pattern Al-U ------
・Upper layer wiring pattern 24, 26−−−−−・Edge θ −・・−obtuse angle] ↓( 丑2, + Rough' Honne a11/L essence 1 n Conventional chip software ゛All and 7 Ratsukho Shun J1212]

Claims (1)

[Scope of Claims] A semiconductor chip, a lower layer wiring pattern formed on the surface of the chip, and an upper layer wiring provided on the lower layer wiring pattern via an interlayer insulating film and substantially perpendicular to the lower layer wiring pattern. A wiring pattern shape for a semiconductor device, further comprising an edge of the lower wiring pattern and an edge of the upper wiring pattern forming an obtuse angle at an intersection thereof.