JPS61218153A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the level margin of an input signal to a latchup occurred due to a protecting circuit by supplying a ground potential supplied to a protecting element for forming the protecting circuit by independent ground wirings. CONSTITUTION:Two ground wirings GND 1, GND1' are formed to be independently arranged from a bonding pad. In other words, the wirings GND 1 supply a ground potential to internal circuits. The wirings GND 1' supply a ground potential to a protecting circuit made of a resistor R and MOSFETQ formed in an input circuit. When the wirings GND 1' are formed to arrange on the outer periphery of a semiconductor chip, the ground wirings exclusive to the protecting circuit can be disposed extremely simply without crossing the wirings of the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective for use in, for example, a device including an input circuit configured by an 0MO3 (complementary MO3) circuit. It is.

[Background technology]

MOSFET (insulated gate field effect transistor)
In the input circuit configured as above, in order to protect the gate insulating film of the MOSFET from the external surge voltage applied to the external terminal, a protection circuit configured with, for example, a resistor and a MOS diode is provided (gate protection configuration). (see, for example, US Pat. No. 3,403,270).

However, when a CMOS circuit is used as an input circuit that receives a signal from the external terminal, when the internal circuit is in an operating state by being supplied with a power supply voltage, the negative signal supplied from the external terminal is MOS constituting the protection circuit, which is normally reverse biased by voltage (e.g. undershoot of external signal)
The drain of the FET and the substrate (or well region) may be forward biased, causing current to flow into the substrate (or well region). Such undesired currents cause latch-up, which turns on the well-known parasitic thyristor elements in CMO8 circuits.

The inventor of the present invention has discovered a phenomenon in which latch-up due to such a parasitic thyristor element occurs even with a relatively small negative voltage. A detailed study of this phenomenon revealed that the circuit ground potential supplied to the protection circuit is supplied by a common ground line with the ground potential supplied to the internal logic circuit. That is, the entire operating current of the internal logic circuit flows through the power supply voltage line and the circuit's ground line. Since the wiring in a semiconductor integrated circuit is formed by fine wiring, it contains a non-ignorable resistance component, and due to the flow of the operating current, the ground potential of the internal circuit is several times lower than the ground potential supplied from the outside. In some cases, the voltage can be increased by as much as 10 mV.

In this way, when the ground potential supplied to the protection circuit increases, even if the negative voltage supplied from the outside is relatively small, it becomes sufficient to forward bias the PN junction. As a result, the parasitic silice element as described above is activated.

[Purpose of the invention]

An object of the present invention is to provide a semi-quadrilateral integrated circuit device that exhibits high reliability with a simple configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the elements constituting the input protection circuit are supplied with the circuit's ground potential through a ground line that is provided independently from the ground line that supplies the circuit's ground potential to the internal circuit.

〔Example〕

FIG. 1 shows a static type RA to which the present invention is applied.
A block diagram of M is shown. This figure shows the internal configuration of a RAM with a storage capacity of approximately 64 bits and an output of 4 bits. In the figure, each circuit section surrounded by a broken line is formed on a single semiconductor substrate such as single crystal silicon using semiconductor integrated circuit technology.

Each static type RAM in this embodiment has 12
It has four matrices (memory arrays M-ARY1 to M-ARY4) with a storage capacity of 8 columns (rows) x 12a rows (columns) - 16384 bits (approximately 16 bits), resulting in a total of approximately 64 bits. It has a storage capacity of . An address circuit for selecting a desired memory cell MC from each memory array M-ARY1 to memory array M-ARY4 having a plurality of memory cells MC is as follows:
Address buffer ADB, row address decoder R
-DCR, column address decoder C-DCR, column switches C-5WI to C-5W4, etc.

Although not shown, each of the memory cells MC has the same configuration, and includes, although not particularly limited to, a pair of N-channel storage MO3FETs whose gates and drains are cross-connected to each other, and information provided on each drain. Holding resistor, memory MO5FET and a pair of complementary data lines.

The N-channel transmission gate MOS FET is provided between the N-channel transmission gate D and the N-channel transmission gate MOSFET. The memory cell MC maintains memory information by supplying the power supply voltage Vcc to the connection point of the resistor.

The above resistance is the memory cell M in the storage information retention state.
In order to reduce the power consumption of C, it is made to have a high resistance value, for example, several megohms to several gigaohms. Also,
The above resistance reduces the area occupied by the memory cell, so
For example, a signal circuit that handles device information readout/IF input is composed of a relatively high-resistance polysilicon layer formed on the surface of a semiconductor substrate forming a MOSFET via a relatively thick field insulating film. Although not particularly limited, the data input circuits DIBI to DIB4. Data output circuit DOB-DOB4. Sense amplifier SAI~
Consists of 5A16.

The timing circuit for controlling the information read/write operation includes, but is not particularly limited to, an internal control signal generation circuit COM-GE and a sense amplifier selection circuit GS.

The row address selection lines (word lines W1 to W128) have 128 lines obtained based on the address signals AO to A6.
A decoded output signal according to the row decoder R-DCR is sent out. This decode output signal is transmitted to two memory arrays M-ARYI arranged on the left and right sides of the row address decoder R-OCR, although there is no particular limitation.
M-ARY2 and memory array M-ARY3. M-ARY
It is commonly supplied to the four word lines W1 to W12B.

128 decoded output signals obtained based on the address signals A7 to A13 are sent from the column decoder C-DCR to the column-system address selection line Yl-Y128. This decoded output signal is not particularly limited, but
Two column switches C-3WI and C- are arranged on the left and right sides of the column address decoder C-DCR.
5W2 and C-5W3. Commonly supplied to C-3W4.

Address buffer ADB receives address signals AO to A13 supplied from external terminals and forms internal complementary address signals i0 to a13 based thereon. Note that the internal complementary address signal aQ is composed of an internal address signal aO having the same phase as the address signal AO, and an internal address signal 0 having a phase inverted with respect to the address signal AO. The remaining internal complementary address signals al to 13 are similarly composed of internal address signals a1-113 of the same phase and internal address signals al-a13 of phase inversion.

Of the internal complementary address signals lO to a13 formed by address buffer ADB, although not particularly limited,
Internal complementary address signals a7-a13 are supplied to column address decoder C-DCR. Column address decoder C7OCR receives these internal complementary address signals a7
~a13 is decoded, and the selection signal (decoded output signal) obtained by decoding is sent to the switch MO5FET (
Insulated gate field effect transistor) Q6゜Q6~Q7
．． Supplied to gates such as Q7.

Among word lines W1 to W128 in each memory array M-ARY 1-%-M-ARY4, one word line designated by a combination of address signals AO-A6 from the outside is connected to the above-mentioned row address decoder R-DCR.
selected by the column address decoder C mentioned above.
- Address signals A7 to A1 from the outside by DCR.
A pair of complementary data lines designated by a combination of 3 is selected from among 128 pairs of complementary data lines. As a result, each memory array M-ARY1 to memory array M
-ARY4, each one memory cell MC arranged at the intersection of the selected word line and the selected complementary data line is selected.

The storage information read from the selected memory cell MC is transmitted to four pairs of sub-common complementary data lines C. That is, the subcommon complementary data line CDl.

Like memory array M-ARYI, memory blocks M1 to 128 pairs of complementary data lines are divided into 32 pairs.
Compatible with M4. Sense amplifier SAI or SA4
is the divided subcommon complementary data IJIICD
l, CDl-CD4. Each one is provided corresponding to CD4.

In this way, subcommon complementary data lines CDI, CD1 to CD
4. Divide into 4 CDs, each with a separate amplifier SAI.
The purpose of providing SA4 is to divide (reduce) the parasitic capacitance of the common complementary data line and to speed up the information read operation from the memory cells.

The sense amplifier selection circuit GS receives the address signal A12.
．． A13 is decoded into four combinations to form a sense amplifier selection signal m l -y m4.

The above four sense amplifiers 5AI-5A4 (SA5~S
A8, SA9 to 5A12 and 5A13 to 5A16), one sense amplifier corresponding to the complementary data line selected by the column switch receives selection signals m1 to
is put into operation by m4 and timing signal Sac,
The output is transmitted to the common complementary data lines CDL, CDL.

The common complementary data lines CDL, CDL are coupled to the input terminal of the data output circuit DOB and the output terminal of the data input circuit DIB. In the write operation, the divided sub-common complementary data lines CD1. CDI~C
D4. CD4 is a transmission game that receives the write control signal we) M OS F'ETQ1. Ql~Q5. Shorted by Q5.

The internal control signal generation circuit COM-GS receives the two write enable signals) and generates an internal chip selection signal csl.
, sac (sense amplifier operation timing signal), w
e (write control signal), die (data input control signal)
and doc (data output control signal).

FIG. 2 shows a layout diagram of an embodiment of a static RAM similar to the above. In this example, 1
The structure is such that access is made in units of bits, and the column selection circuit ( column address decoder) for each memory array M-ARYI~
This circuit differs from the embodiment circuit shown in FIG. 1 in that M-ARY 4 is provided. Further, when the storage capacity is approximately 64 bits as shown in FIG. 1, the address terminals A12 to A15 are omitted to avoid complicating the drawing.

The column address decoder C-DCR and the row address decoder R-DCR include pre-address decoders R,
It is adapted to be operated by the predecoder output formed by the C-DCH. By dividing the address decoder into multiple stages in this manner, the circuit is simplified and the parasitic input capacitance is reduced, thereby increasing the speed of operation.

In this embodiment, two ground lines GNDI and GNDI° are connected from the bonding pad in order to increase the input level margin for the U-NOTI AMBU by the protection circuit described later.
are configured to run independently. That is, the ground wire G
NDI supplies the ground potential to each of the internal circuits. On the other hand, the ground line GNDi' supplies the ground potential to a protection circuit provided in the input circuit. Although not particularly limited,
The ground line 0NDI' is configured to run along the outermost periphery of the semiconductor chip. That is, it is configured to run in an area of the semiconductor substrate outside each circuit pattern including the bonding pad. This makes it possible to extremely easily arrange a dedicated grounding line to the protection circuit without intersecting any wiring constituting the internal circuit. Also,
Since the protection circuit is provided close to the external terminal, the layout of the ground line GNDI° as described above is extremely rational.

Note that the ground line GND2 supplies a ground potential to the data output circuit DOB. Also, of the two power supply voltage lines (ponding pads) Vccl and Vcc2, Vcc
2 supplies a power supply voltage to the data output circuit DOB. In this way, the reason why independent wiring and bonding bands are provided for the data output circuit DOB is to reduce the noise generated when the relatively large load drive current of the data output circuit flows through the wiring resistance and inductance, which cannot be ignored. This is to make it happen. Note that each of the above two bonding pads GND1. GND2 and Vccl, Vcc
2 are each connected to a common external terminal by wire bonding.

FIG. 3 shows a circuit diagram of one embodiment of address buffer ADB. In the same figure, MO3FETQ11 etc. with a straight line on the channel part are P-channel MO3FETQ11 etc.
It is an SFET and is distinguished from N-channel MO3FETQIO and the like.

3rd FI! In J, MO3FETQI 1. Ql
3 and Ql5 are P-channel type, MO3FET
QI O, Ql 2. Ql 4. Ql 6. Ql7°Ql8 is of N-channel type, and bipolar transistors TI and T2 are of NPN type.

Resistance R,! =M03FETQ10 means that MOSFETQ11. Q
A gate protection circuit is configured to protect the gate insulating film of l2. Ground potential GNDI of the circuit supplied to this protection circuit
' increases the level margin against chip-up due to the negative voltage of the external terminal Ai (so that the ground potential applied to the commonly connected gate and source of the diode-type MOSFET QIO is supplied by the ground line 0NDI'). .

MOSFETQI 1. Ql 2 and Ql 3. Ql4 is
A two-stage cascade-connected CMOS inverter circuit is constructed. This allows the CMOS inverter circuit (Ql
1. A signal in phase with the input signal of Ql2) is obtained from the output of the CMOS inverter circuit (Ql3, Ql4).

On the one hand, the output of the CMOS inverter circuit (Ql3.Ql4) is the address signal A from the external terminal.
It is transmitted to an output circuit that forms an internal complementary address signal al that is in phase with i. That is, the above output is supplied to the base of a charging output transistor TI of a capacitive load (not shown). The output transistor T2 connected in cascade with the output transistor T1 discharges the capacitive load, so that the base of the transistor T2 has a
The above CMO inverted by P-channel Mo SF ETQ 15 and N-channel MO5FETQI 6
The output signals of the S inverter circuits (Ql 3, Ql 4) are supplied. However, P channel MO3FETQ15
The source of is different from the above CMOS inverter circuit,
It is coupled to the connection point (output terminal) of transistors TI and T2.

On the other hand, the output of the CMOS inverter circuit (Ql3.Ql4) is the address signal Ai from the external terminal.
and is transmitted to an output circuit that forms an internal complementary address signal al having a phase opposite to that of the address signal al. That is, the above output is the same CM as above.
The signal is inverted by the OS inverter circuit IVI and supplied to the base of a charging output transistor T3 of a capacitive load (not shown). An output transistor T4 connected in cascade with the output transistor T3 discharges the capacitive load. Therefore, the output of the CMOS inverter circuit (Ql3, Ql4) is supplied to the base of this transistor T4 via the source follower MO5FETQ17. MOSFETQ18 has the above 7-s7rO'7
It not only operates as a load for M05FETQ1'7, but also operates as a switch MO5FET for discharging the charge accumulated in the base of transistor T4.

In addition, in order to prevent the transistor T2 from being driven in the saturation region, the source of the MO3FET QI 5 is connected to the collector of the transistor T2 instead of the power supply voltage VCC as described above, and the transistor T4 is similarly driven in the saturation region. To prevent this, MO3FETQI 7
The drain of the transistor T is not connected to the power supply voltage Vcc.
4 collector. This aims to speed up the switching operation.

In this embodiment, by using a bipolar transistor with a large current driving capacity in the output section of the address buffer, a relatively large capacitance such as a gate capacitance is added to the gates of many MOSFETs that constitute the address decoder as a load. It is possible to charge/discharge the parasitic capacitance that has been set to a value at high speed. Such an output circuit is similar to the address decoders R-DCR and C-DC in FIG.
The internal circuit of such an address buffer is provided with a ground line GND (not shown) to speed up the selection operation of the memory array by providing it also at the output part of the address buffer R.
1 gives the ground potential of the circuit, and is distinguished from the ground line GNDI° of the protection circuit.

FIG. 4 shows the MOSFET QI that constitutes the above protection circuit.
A cross-sectional view of an element structure of an embodiment of O is shown, and a plan view thereof is shown in FIG.

In FIG. 4, a P-type semiconductor and a substrate P-3OB are used, and the following semiconductor layers and the like are formed on the surface thereof by a semiconductor integrated circuit manufacturing method developed by the present inventor.

Selective P is applied to the element formation region on the surface of the substrate P-3UB.
A small buried layer P"BL is formed. This buried layer P+B
Of L, an N-sized buried layer N+BL is provided as a guard ring so as to surround the element formation area. A P-type well region P-WELL for forming an N-channel MO3FET QIO is formed on these surfaces.

The power supply voltage Vcc is supplied to the N"BL as a guard ring so as to surround this well region P-WE L L.
A mold contact hole CN is provided. N channel MO
3FETIO is composed of an N-sized source region S and a drain region formed in a well region P-WELL, and a gate electrode FC formed on the surface of this semiconductor substrate with a gate insulating film interposed therebetween. Note that in the MOSFET QI O of this embodiment, a source region is formed so as to surround a drain region, as is clear from the layout diagram described later. Therefore, bordering on the IIj% line in the same figure,
The structure is symmetrical, and only the element structure on the left side is shown in the figure. Further, in the figure, the shaded portion is an insulating film, and represents a gate insulating film and a field insulating film that constitute a MOSFET. The outer periphery surrounding the above element is P
A ◆ type semiconductor region is provided, and a ground potential is applied to the source and well regions by a ground line GND1''.
As is clear from the layout diagram below, this grounding wire is
It is also connected to the gate electrode FC of MOSFET QIO.

In FIG. 5, a ground line GNDI' made of an aluminum layer extending from the bottom to the top is arranged.

This aluminum layer is arranged on the surface of the P+ region shown by the dotted line on the source region constituting the MO3FET QIO and outside it, and the overall shape is V (J-shaped. In the figure, the square opening) is the contact point. The reason why such a large number of contact holes are arranged is to reduce the resistance value at the connection point and reduce the discharge time constant of the surge voltage. Also, MO3FETQIO
An aluminum layer for connecting to the drain of the transistor extends from the top to the bottom. That is, it extends from the U-shaped opening to above the central drain region, and is connected by a contact hole similarly shown by a square (b). In addition, CN indicated by a dotted line is placed on the outermost periphery, and above it,
An aluminum layer that supplies power supply voltage Vcc is formed in the shaded area. In the figure, the resistor R is represented only by a circuit symbol, and its pattern is omitted.

In this embodiment, a CMOS circuit and a bipolar transistor as described above are formed on the same semiconductor substrate, resulting in a relatively complicated element structure.
In the S circuit, the element structure is MOS F
It goes without saying that a child is constituted by ET.

〔effect〕

(1) By supplying the ground potential to the protection elements constituting the protection circuit through an independent ground line, in the operating state when the semiconductor integrated circuit device is powered on,
No current flows through the protection circuit, so the ground potential supplied to the protection circuit is set to the same low potential as the ground potential supplied from the external terminal, regardless of the operating current of the internal circuit.

Therefore, the potential of the external input terminal required to forward bias the PN junction of the elements constituting the protection circuit is relatively low. As a result, it is possible to increase the level margin of the input signal with respect to the rough drop caused by the protection circuit.

(2) By arranging the ground line that supplies the ground potential to the elements constituting the protection circuit at the outermost periphery of the semiconductor chip, it is possible to obtain the effect that reliability can be improved with a simple layout. In other words, there is an area on the outermost periphery of the semiconductor chip where no elements are formed, and by placing the ground line here, it will not intersect with any other wiring, making it possible to achieve high integration and wiring layout. without compromising the complexity.

(3) In an internal circuit that combines a CMOS circuit and a bipolar transistor, a relatively large current flows through the ground line due to the operation of the bipolar transistor, which has a larger current supply capacity than a MOSFET. . Therefore, the elevation of the ground wire is made relatively large. Therefore, by providing a ground line that supplies the ground potential to the protection circuit independently of the ground line of the internal circuit, it is possible to effectively prevent launch amplifiers caused by the protection circuit.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. For example, the internal circuit is C
Any device, such as a MOS circuit, may be used as long as it includes an element structure that forms a parasitic thyristor element together with elements that form a protection circuit. Further, the layout of the ground line that supplies the ground potential to the protection circuit can take various embodiments. Furthermore, M constituting the protection circuit
Similarly, the pattern of the OS diode can be modified in various ways.

(Field of Application) The present invention can be widely applied to semiconductor integrated circuit devices having an internal circuit such as a CMOS circuit having an element structure that constitutes a parasitic risk element together with elements that constitute a protection circuit.

[Brief explanation of the drawing]

Figure 1 shows a static type RAM to which this invention is applied.
FIG. 2 is a block diagram showing one embodiment, FIG. 2 is a layout diagram showing one embodiment, FIG. 3 is a circuit diagram showing one embodiment of the input circuit, and FIG. 4 is a configuration of the protection circuit. FIG. 5 is a schematic cross-sectional view of a MOS diode, and FIG. 5 is a plan view thereof. M-ARYI to M-ARY4...Memory array (memory matrix), MC...Memory cell. GS...Sense amplifier selection circuit, C-DCR, C-DC
RI~C-DC-R4...Column address decoder, S
AI~5A16...Sense amplifier, COM-GE...Internal control signal generation circuit, R-DCR...Row decoder, A
DB...address buffer, C-3WI~C-3W4...
・Column switch 2nd diagram lol! J3 diagram

Claims (1)

[Claims] 1. The grounding line that supplies the circuit grounding potential to the internal circuits including the CMOS circuit and the grounding line that supplies the circuit grounding potential to the elements constituting the electrostatic damage prevention circuit are independent from each other. 1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is arranged as follows. 2. Claim 1, characterized in that the ground line that supplies the circuit ground potential to the elements constituting the electrostatic damage prevention circuit is laid out so as to run along the outermost periphery of the semiconductor chip. The semiconductor integrated circuit device described in . 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the electrostatic damage prevention circuit is constituted by a resistor and a MOS diode. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the internal circuit including the CMOS circuit is a combination of a CMOS circuit and a bipolar transistor.