JPH0193922A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To extend an operation margin by making conductances of MOSFETs, which set a logic threshold voltage, different from each other to have an approximately fixed logic threshold voltage independently of voltage drop so that the voltage drop due to a distributed resistance of an internal power supply line is compensated. CONSTITUTION:The conductance of an N-channel MOSFET Q25 is set to a large value for the purpose of compensating DELTAV' rise of a logic threshold voltage VL'. That is, its channel width WN' is set to a large value. Consequently, the resistance value of the N-channel MOSFET Q25 is reduced in proportion to a reciprocal 1/WN' without changing the resistance value of a P-channel MOSFET Q24 to perform such compensation that it has a logic threshold voltage VL. Thus, an input signal level is approximately fixed, and the logic threshold voltage is fixed to a desired value, and the input level margin is extended.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, for example, a CMO device.
The present invention relates to a technique that is effective for use in semiconductor integrated circuit devices such as static RAMs that use a MO3 (complementary type MO3) inverter circuit as an input buffer.

[Conventional technology]

Static RAM (Random Access Memory) that uses a CMOS inverter circuit as an input buffer
For example, Nikkei McGraw-Hill, March 10, 1986, "Nikkei Electronics," pages 199 to 217.
There is.

[Problem that the invention seeks to solve]

Since the CMOS inverter circuit receives a TTL level input signal, the conductance ratio between the N-channel MOSFET and the P-channel MOSFET is set so that they have the same corresponding logic threshold voltage.

By the way, in general, in a semiconductor integrated circuit, a power supply voltage terminal and a circuit ground potential terminal are respectively supplied to opposing sides of a chip. As semiconductor integrated circuits become more highly integrated,
The power supply lines (power supply voltage line and ground line) tend to be longer and thinner.

Therefore, the voltage drop due to the distributed resistance in the power supply line cannot be ignored.

For example, a CMOS installed near the power supply voltage terminal
Considering an inverter circuit, the voltage drop due to the above-mentioned distributed resistance can be ignored for the power supply voltage supplied from the outside, but the ground potential of the circuit is given by the wiring extended from the opposite side of the chip. , the potential is set to be higher by the voltage drop corresponding to the current flowing through the distributed resistance. Therefore, if all circuits are set to have the same logic threshold voltage VL as described above, the actual logic threshold voltage of the CMOS inverter circuit provided near the power supply voltage terminal will be equal to the rise in the ground potential of the circuit. The price will be increased accordingly. Conversely, if we consider a CMOS inverter circuit installed near the ground terminal, the ground potential supplied from the outside can ignore the voltage drop due to the above-mentioned distributed resistance, but the power supply voltage is extended from the opposite side of the chip. Since the voltage is given by the distributed resistance wiring, the potential is lowered by the voltage drop corresponding to the current flowing through the distributed resistance. Therefore, the actual logic threshold voltage of the CMOS inverter circuit provided near the ground terminal is lowered in accordance with the reduction in the power supply voltage. From the above, in the CMOS inverter circuit provided near the power supply voltage terminal, the margin on the high level side deteriorates, and in the CMOS inverter circuit provided near the ground terminal, the margin on the low level side deteriorates. Therefore, in the entire semiconductor integrated circuit, a problem arises in that both the high level and low level margins deteriorate. □ An object of the present invention is to provide a semiconductor integrated circuit device that improves the production margin.

Another object of the present invention is to provide a semiconductor integrated circuit device that realizes high-speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in order to compensate for the voltage drop due to the distributed resistance in the internal power supply line, the conductance of the MOSFET that sets the logic threshold voltage is varied, so that the logic threshold voltage is constant regardless of the voltage drop.

[For production]

According to the above-mentioned means, since the actual logic threshold voltage can be set to a constant value, the operating margin can be expanded.

[Embodiment 1] FIG. 1 shows an equivalent circuit diagram of an embodiment in which the present invention is applied to a semiconductor integrated circuit device such as a CMOS gate array. Although each circuit element in the figure is not particularly limited by known semiconductor integrated circuit manufacturing technology,
It is formed on a single semicircular substrate such as single crystal silicon.

In the figure, a P-channel MOS FET is distinguished from an N-channel MO3FET by an arrow attached to its channel (back gate) portion. Furthermore, the resistance elements in the figure exemplarily show distributed resistance in the power supply line.

The power supply terminal Vcc supplies a power supply voltage (Vcc) to each circuit element formed within the chip via a power supply (voltage) supply line having distributed resistances RVI to RVm.

Similarly, the ground terminal GND has a distributed resistance RC,1 to RGk
A ground potential (GND) is supplied to each circuit element formed within the chip through a power (ground) supply line having a power supply (ground) supply line.

Generally, in a semiconductor integrated circuit, the power supply terminal Vc
c, and the circuit ground potential GND are provided on opposite sides of the chip. Correspondingly, in the figure, the power supply terminal Vcc is arranged at the right end, and the power supply line is extended leftward. Further, a ground terminal GND is arranged at the left end, and the power supply line is extended rightward.

For example, P channel MO5F located at the left end of the figure
Looking at the CMOS inverter circuit consisting of ETQ20 and N-channel MO3FETQ21, we see that the N-channel MO3
The source of the FETQ21 is directly supplied with the circuit's ground potential from the ground terminal GND, whereas the source of the P-channel MO3FET20 is connected to a distributed resistance RVI~
Power supply voltage Vcc is supplied through RVm. Therefore,
The operating voltage actually supplied to the source of P-channel MO8FETQ20 is the above E B1! Only a voltage lower than the voltage Vcc by the voltage drop across the distributed resistors RVI to RVm is supplied.

Conversely, the P-channel MO3FE located at the right end of the figure
C consisting of TQ24 and N-channel MO3FETQ25
Looking at the MOS inverter circuit, P channel MO3F
The source of the ETQ24 is directly supplied with the power supply voltage Vcc from the power supply terminal Vcc through the distributed resistor RVI, whereas the source of the N-channel MO3FET25 is supplied with the circuit ground potential through the distributed resistors RGI to RGk-1. Supplied. Therefore, N-channel MO3FETQ
The ground potential actually supplied to the source of 25 is the above OV
A high voltage raised by the voltage drop across the distributed resistor RGI-RGk-1 is supplied to the resistor RGI-RGk-1.

Any point n on the power supply line that supplies the power supply voltage Vcc-i
(n<n+-1), the distributed resistance RV 1- RV n
The power supply voltage Vcc is lowered by the voltage drop at , and is supplied to the source of the P-channel MO3FBTQ22. Power supply that supplies the ground potential GND of @ path! ,! i
At any point j−Hj <k−1) of l, the distributed resistance RG
1=The ground potential of the circuit is raised by the voltage drop at RVj-1, and the N-channel MO3FETQ23
source.

From this, each P channel MO3FET and each N
If the conductance ratio with the channel MOS FET is set to be the same as in the conventional case, the respective logic threshold voltages will differ by the amount of voltage fluctuation corresponding to the voltage drop in the power supply line. For example, to explain the CMOS inverter circuit consisting of the above-mentioned MO3FETQ24 and Q25, as shown in FIG.
VI supplies almost the same voltage as the power supply voltage Vcc supplied from the external terminal. On the other hand, the source of the N-channel MO3FET Q25 is supplied with a potential raised from the ground potential GND by a voltage ΔV corresponding to the voltage drop due to the distributed resistors RGI to RGk-1, as shown by the dotted line in the figure. Ru. Therefore, the channel width of the P-channel MO3FET Q24 is adjusted so as to obtain a desired logic threshold VL that is biased toward the low level side, such as the TTL (transistor-transistor-logic) level, ignoring the existence of the distributed resistance as in the conventional case. If the logic threshold voltage VL is set according to the resistance ratio corresponding to WP and the channel width WN of the N-channel MOSFET Q25 as shown by the dashed line, the following problem will occur. Here, it is assumed that the channel length and carrier surface mobility μ, ) of each MO3FET are the same. Therefore, the P channel length OS F ET
The conductance of the N-channel length OS FET is
Since it is determined in proportion to the channel widths WP and WN as described above, the resistance ratio is the reciprocal (1/WP): (1/WN
) corresponds to the ratio of Therefore, the above P-channel MO3FET Q24 and N-channel MO3FET
When applying the actual operating voltage considering the distributed resistance as described above to the CMOS inverter circuit consisting of Q25, the logic threshold voltage VL is shown by the dotted line.
' , which is increased by Δ■°.

In this embodiment, in order to compensate for the logic threshold voltage VL' increasing by the above voltage ΔV'',
The conductance of N-channel MO3FETQ25 is
It is set large. That is, its channel width WN'
Set to a large value.

As a result, the resistance value of N-channel MO3FET Q25 is reduced in proportion to its reciprocal 1/WN' without changing the resistance value of P-channel MO3FET Q24, and the resistance value of N-channel MO3FET Q25 is compensated to have the logic threshold voltage VL.

Although not shown, in a CMOS inverter circuit consisting of a P-channel MO3FETQ20 and an N-channel MO3FETQ21, the power supply voltage Vcc is supplied to the source of the P-channel MO3FETQ20, and its distributed resistance RV
Since it is lowered in accordance with I to RVm, the conductance of N-channel MO3FETQ21 is set to be smaller (resistance value is larger) accordingly.

In addition, the power supply voltage Vc supplied to the sources of the P-channel MO5FETQ22 and the N-channel MO3FETQ23
The conductance ratio of the P-channel MO3FETQ23 and the N-channel MO3FETQ24 is set in accordance with the voltage drop in c and the rise in the ground potential of the circuit so that the desired logic threshold voltage VL can be obtained.

In this case, it is convenient to, for example, keep the size (conductance) of the P-channel MOS FET constant and change the conductance of the N-channel MOS FET depending on the position where it is provided.

By doing this, each CMOS inverter circuit receives input signals from external terminals INI to IN3,
When forming an internal signal accordingly, the external terminal I
The input signal level supplied from NI to INS is supplied through a mounting board such as a printed wiring board, and is the same as V, so the input level margin can be expanded by making the logic threshold voltage constant as desired. . Note that the output signal of each CMOS inverter circuit has a signal level corresponding to the power supply voltage supplied thereto and the ground potential of the circuit. Logic gate circuits G1, G2 receiving output signals of CMOS inverter circuits for each input,
, G3, etc. are provided adjacent to each inverter circuit. Therefore, each of the above logic gate circuits Gl, G
2, 03, etc., there is no need to consider setting the logic threshold voltage according to the arrangement as described above.

For example, if the output signal formed by MO3FETQ20 and G21 is used in gate circuits G2 and G3, whose operating voltages and circuit ground potentials are significantly different,
The logic threshold voltage may be compensated accordingly.

[Example 2] FIG. 6 shows a static type RA to which this invention is applied.
A block diagram of M is shown. This figure shows the internal configuration of a RAM with a storage capacity of approximately 64 bits and an output of 4 bits. In the figure, each circuit section surrounded by a broken line is formed on a single semiconductor substrate such as single crystal silicon using semiconductor integrated circuit technology.

Each static type RAM in this embodiment has 12
It has four matrices (memory arrays M-ARY1 to M-ARY4) with a storage capacity of 8 columns (rows) x 128 rows (columns) = 16384 bits (approximately 16 bits), resulting in a total of approximately 64 bits. It has a storage capacity of . An address circuit for selecting a desired memory cell MC from each memory array M-ARY1 to memory array M-ARY4 having a plurality of memory cells MC is as follows:
Address buffer ADB, row address decoder R
-DCR, column address decoder C-DCR, column switches C-3WI to C-3W4, etc.

Although not shown, each of the memory cells MC has the same configuration. Although not particularly limited, the memory cell MC includes a pair of N-channel storage MO3FETs whose gates and doins are cross-connected to each other, and whose drains are connected to each other. It is composed of an information holding resistor provided, and an N-channel transmission gate MO3FET provided between the storage MO3FET and a pair of complementary data lines D, D, respectively. The memory cell MC has a power supply voltage Vc at the connection point of the resistor.
The memory information is held by being supplied with c.

The above resistance is the memory cell M in the storage information retention state.
In order to reduce the power consumption of C, it is made to have a high resistance value, for example, several megohms to several gigaohms. Also,
The above resistance is set to 1 in order to reduce the area occupied by the memory cell.
1. For example, it is composed of a relatively high-resistance polysilicon layer formed on the surface of a semiconductor substrate forming a MOS FET with a relatively thick field insulating film interposed therebetween.

Signal circuits that handle reading/writing of information are not particularly limited, but include data input circuits DIBI to DIB4. Data output circuit DOB-DOB4. Sense amplifier SAI~5
It is composed of A16.

The timing circuit for controlling the information read/write operation includes, but is not particularly limited to, an internal control signal generation circuit COM-GE and a sense amplifier selection circuit GS.

The row-related address selection lines (word lines W1 to W128) have 128 lines obtained based on the address signals AO-A6.
A decoded output signal according to the row decoder R-DCR is sent out. This decode output signal is transmitted from two memory arrays M-ARYI arranged on the left and right sides of the row address decoder R-DCR, although not particularly limited.
M-ARY2 and memory array M-ARY3. M-ARY
It is commonly supplied to the four word lines W1 to W128.

128 decoded output signals obtained based on address signals A7 to A13 are sent to column-system address selection lines Y1 to Y128 from a column decoder C-DCR. This decoded output signal is not particularly limited, but
Two column switches C-3WI and C- are arranged on the left and right sides of the column address decoder C-DCR.
3W2 and C-8W3. Commonly supplied to C-3W4.

Address buffer ADB receives address signal AO-A13 supplied from an external terminal and forms internal complementary address signals 10-13 based on this. Note that the internal complementary address signal 0 is composed of an internal address signal aQ having the same phase as the address signal AO, and an internal address signal aO whose phase is inverted with respect to the address signal AO. Similarly, signals l to a13 are composed of internal address signals a1 to a13 of the same phase and internal address signals a1 to a13 of phase inversion.

Internal #YJ formed by address buffer ADH
Of the +M address signals ao-a13, internal complementary address signals 7 to a13 are supplied to the column address decoder C-DCR, although this is not particularly limited. The column address decoder C-DCR decodes these internal complementary address signals 7 to 13, and outputs the selection signal (decode output signal) obtained by the decoding to the column switches c-swi to C-3W4. MO3F for switch
ET (insulated gate field effect transistor) Q6゜Q
6~Q7. Supplied to gates such as Q7.

Among word lines W1 to W128 in each memory array M-ARYI to M-ARY4, one word line designated by a combination of external address signals AO to A6 is selected by the above-mentioned row address decoder R-DCR. , the above-mentioned column address decoder C-DC
By R, a pair of complementary data lines designated by a combination of address signals A7 to A13 from the outside are 12
Selected from eight pairs of complementary data lines. As a result, each memory array M-ARY1 to memory array M-AR
At Y4, one memory cell MC arranged at the intersection of the selected word line and the selected complementary data line is selected.

The storage information read from the selected memory cell MC is transmitted to four pairs of sub-common complementary data lines CDI, CDI~
CD4. Appears on one of CD4. That is, the subcommon complementary data line CD I.

CD1~CD4. CD4 corresponds to memory blocks M1 to M4 in which 128 pairs of complementary data lines are divided into 32 pairs each, like the memory array M-ARY1 shown as a representative. Sense amplifiers SAI to SA4 receive the divided subcommon complementary data &%CD1. CDl
-CD4. Each one is provided corresponding to CD4.

In this way, the subcommon complementary data line CD1. CD1~CD
4. The purpose of dividing into CD4 and providing sense amplifiers SAI to SA4 for each is to divide (reduce) the parasitic capacitance of the common complementary data line and to speed up the information read operation from the memory cell.

The sense amplifier selection circuit GS receives the address signal A12.
．． Based on A13, it is decoded into four combinations to form sense amplifier selection signals m1 to m4.

The above four sense amplifiers SAI to SA4 (SA5 to S
A8, SA9 to 5A12 and 5A13 to 5A16), one sense amplifier corresponding to the complementary data line selected by the column switch receives the selection signal rn.
1 to m4 and the timing signal Sac, and transmit the output to the common complementary data wcCDL and CDL.

The common complementary data lines CDL, CDL are coupled to the input terminal of the data output circuit DOB and the output terminal of the data input circuit DIB. In the write operation, the transmission gate MOSFETs Ql, Ql to Q5 . Shorted by Q5.

The internal control signal generation circuit coM-cs receives two external control signals C5 (chip select signal) and WE (write enable signal), and generates internal chip selection signals csl and sa.
c (sense amplifier operation timing signal), we (write control signal), dic (data input control signal) and d
oc (data output control signal), etc.

FIG. 4 shows a layout diagram of an embodiment of a static type RAM similar to the above. RA of this example
M must be configured such that it can be accessed in units of bits, and multiple memory arrays M-ARYI to M-A.
In order to select only the memory array in which the selected memory cell is provided among RY4, the column selection circuit (column address decoders C-DCR1 to C-DCR4 and column switches c-swi to C-3W4) selects each memory. The circuit differs from the embodiment shown in FIG. 6 in that it is provided corresponding to arrays MARYI to M-ARY4. Further, when the storage capacity is approximately 64 bits as shown in FIG. 6, the address terminals A13 to A15 are omitted to avoid complicating the drawing.

In addition, the column address decoder C-DCR and the row address decoder R-OCR include a pre-address decoder R,
It is adapted to be operated by the pre-decoder output formed by the CPDEC. By dividing the address decoder into multiple stages in this way, it is possible to increase the speed of operation by making the circuit more cylindrical and reducing parasitic input capacitance.

In this embodiment, although not particularly limited, a pad and a wiring G that independently supply a ground potential to the data output circuit DOB are used.
ND2 is provided. The pad GNDI that supplies ground potential to other circuits and the corresponding pad GNDI are:
It is connected to a common ground terminal GND by wire bonding.

The purpose of providing independent wiring and bonding pads for the data output circuit DOB as described above is to prevent noise generated by the relatively large load drive current of the data output circuit flowing through the wiring resistance and inductance that cannot be ignored. This is to reduce the

A ground line GND1 supplies a ground potential to each of the internal circuits. The ground line GNDI has a branch corresponding to a pad so as to supply a ground potential to a protection circuit provided in an input circuit, which will be described later. Although not particularly limited, the ground line GNDI is configured to run along the outermost periphery of the semiconductor chip. That is,
It is configured to run in an area of the semiconductor substrate outside each circuit pattern including all bonding pads. As a result, the ground line can also be placed in the protection circuit without intersecting with any wiring constituting the internal circuit.

Further, the power supply voltage is supplied from the band VCC, and is supplied to each circuit through the voltage supply line VCC. Like this R
In the AM, the above-mentioned pads are arranged to the left and right in the figure, and include a pad Vcc for power supply voltage and a pad GNDi for ground potential.

GND2 is distributed and provided on the left and right opposing sides. Then, as shown in the figure, the address buffer R-AD
When the B and C-ADBs are placed together on the left side, the ground wire is made relatively long.

Therefore, the ground potential actually supplied to the CMOS inverter circuit constituting the address buffer is said to be raised with respect to the ground potential such as OV applied to the pad GND1 according to the distributed resistance in the ground line. Ru. Instead of this configuration, for example, address signals A6 to A9
If the column address buffer C-ADB, which is supplied with the same voltage as the column address buffer C-ADB, is placed on the right side, the length of the power supply vAVcc becomes longer, and the actually supplied power supply voltage decreases. Similarly, the CM that constitutes the input buffer corresponding to the write signal Din and the control signals C3 and WE
In the OS inverter circuit, as the length of the power supply line Vcc is lengthened as described above, the actual power supply voltage is reduced.

FIG. 5 shows a circuit diagram of one embodiment of address buffer ADB.

In Fig. 5, MO3FETQI, Ql3 and Ql5 are P-channel type, and MO3FETQIO
, Ql2. Ql4. Ql6. Ql7゜Ql8 are N-channel type, and bipolar type transistors TI, T2 .
T3. T4 is of NPN type.

Resistor R and MO3FETQIO are MOS FETQll, Q from external surge voltage applied to input terminal Ai.
A gate protection circuit is configured to protect the gate insulating film of l2.

MO3FETQI 1. Ql 2 and Ql 3. Ql4 is
A two-stage cascade-connected CMOS inverter circuit is constructed. This allows the CMOS inverter circuit (Ql
A signal in phase with the input signal of Ql, Ql2) is obtained from the output of the CMOS inverter circuit (Ql3, Ql4).

On the one hand, the output of the CMOS inverter circuit (Ql3.Ql4) is the address signal A from the external terminal.
It is transmitted to an output circuit that forms an internal complementary address signal ai that is in phase with i. That is, the above output is supplied to the base of a charging output transistor TI of a capacitive load (not shown). An output transistor T2 connected in cascade with the output transistor TI discharges the capacitive load. Therefore, the base temperature of this transistor T2 is
The above C inverted by P channel/lzMo SF ETQ 15 and N channel MO3FETQI 6
The output signals of the MOS inverter circuits (Ql3, Ql4) are supplied. However, P channel MO5FETQI
Unlike the CMOS inverter circuit described above, the terminal 5/- is coupled to the connection point (output terminal) between transistors TI and T2.

On the other hand, the output of the CMOS inverter circuit (Ql3.Ql4) is the address signal Ai from the external terminal.
and is transmitted to an output circuit that forms an internal complementary address signal at with a phase opposite to that of the address signal at. That is, the above output is the same CM as above.
It is inverted by the OS inverter circuit TVI and supplied to the base of a charging output transistor T3 of a capacitive load (not shown). An output transistor T4 connected in cascade with the output transistor T3 discharges the capacitive load. Therefore, the base of this transistor T4 is connected to the CMOS inverter circuit (Ql 3, Ql 4
) is supplied via the source follower MO3FETQ17. MO3FETQ18 is the above source 7o
It not only operates as a load for the '7M03FETQ17, but also operates as a switch MOS FET for discharging the charge accumulated in the base of the transistor T4.

In addition, in order to prevent the transistor T2 from being driven in the saturation region, the source of the MO3FET QI 5 is connected to the collector of the transistor T2 instead of the power supply voltage Vcc as described above, and the transistor T4 is similarly driven in the saturation region. To prevent this, MO3FETQI 7
The drain of the transistor T is not connected to the power supply voltage Vcc.
4 collector. This aims to speed up the switching operation.

In this embodiment, by using a bipolar transistor with a large current drive capacity in the output section of the address buffer, the gate capacitance added to the gates of the many MOS FETs constituting the address decoder as a load is relatively reduced. Charging a capacitive load with a large capacitance/
Discharge can be performed at high speed. Such an output circuit is similar to the address decoders R-DCR and C in FIG.
- By providing the output section of the DCR as well, it is possible to speed up the selection operation of the memory array (not shown).

FIG. 3 shows a simplified equivalent circuit diagram. In the configuration shown in Figure 4, column address buffer C
- When ADB is placed on the right side, address buffer C-AD corresponding to address signals A6 to A9, etc., as described above.
The CMOS inverter circuit configuring B consists of a P-channel MO3FETQ26 and an N-channel wide MO3FETQ.
As represented by 27, as the ground line is made relatively short, the ground potential of the circuit is applied through a relatively small resistance such as distributed resistance RGI, and conversely, when the power supply voltage supply line is made relatively long, Distributed resistance RVI~RV depending on
A power supply voltage is applied through a relatively large resistor such as m. The input terminal INI receives the above address signals A6 to A9.
These are representative input terminals. In addition, address buffer R-ADB corresponding to address signal AO-A5, etc.
The CMOS inverter circuit that constitutes the P-channel M
O3FETQ28 and N-channel MOS FETQ2
As represented by 9, as the ground line is made relatively long, the ground potential of the circuit is applied through relatively large resistances such as distributed resistances RGI to RGk, and conversely, the power supply voltage supply line is Distributed resistance RVI depending on being made relatively short
The power supply voltage is applied through a relatively small resistance such as . The input terminal IN2 is representative of the input terminals for the address signals AO to A5 and the like. Therefore, in this embodiment, the conductance of P-channel MO3FET Q26 and Q2B is the same (if set, the N-channel MO3FET
The conductance (channel width WN) of FETQ27 is set small, and the conductance (channel width WN) of N-channel MO3FETQ29 is set large.

When the CMOS inverter circuit corresponding to the above address signals A6 to A9, etc. is placed on the right side in FIG. 4, the length of the ground line in the CMOS inverter circuit on the right side is short because the semiconductor chip is configured horizontally. The conductance ratio of each CMOS inverter circuit may be uniformly set to the same value by assuming that the distributed resistances are equal, and by making the length of the power supply line longer than the length of the power supply line. Each C with greater precision
In order to equalize the logic threshold voltage with respect to the input signal level in the MOS inverter circuit, the conductance ratio of the P-channel width OS FET and the N-channel MOS FET may be individually set according to the respective wiring lengths. In this case, the conductance ratio is delicately set for each inverter circuit, taking into account the length of each wiring, in other words, the actual operating voltage applied to each. This means that the CMOS corresponding to address signals A1 to A5 and Al0 to Al2
The same applies when the inverter circuit is placed on the left side in FIG.

In particular, when a TTL level is input, the logic threshold voltage of the input signal level is shifted to the low level side compared to the CMOS level, and the signal amplitude is reduced. Therefore, by equalizing the logic threshold voltages of the input circuits as described above, the level margin of the input signal can be expanded. From another perspective, this means improving the operating speed. In other words, being able to increase the level margin of the input signal as described above means that, for example, when the output circuit is put into operation, it is possible to charge up or discharge the load capacitance consisting of relatively large parasitic capacitance on the mounting board, etc. is necessary. The output current flows through the wiring of the semiconductor chip, and noise is generated by the resistance component and inductance component contained therein. As described above, when the input signal is biased toward the low level side, such as the TTL level, the noise margin particularly on the high level side decreases. Therefore, there is a possibility that the input circuit may malfunction due to the above-mentioned noise because it regards the input circuit as a low level even though it is supplied with a high level. Therefore, in the output circuit, it is necessary to slow down the fall (discharge) of the output signal to suppress noise generated in the ground line. In this embodiment, since the margin of the input signal level is expanded as described above, the fall of the output signal can also be made faster, so that high-speed operation can be realized.

The effects obtained from the above examples are as follows. That is, (1) To compensate for the voltage drop due to the distributed resistance in the internal power supply line, the conductance of the MOS FET that sets the logic threshold voltage is varied to maintain a constant logic threshold voltage of Xo regardless of the voltage drop. By making it so that the logic threshold voltage has a constant value, it is possible to set the actual logic threshold voltage to a constant value, thereby achieving the effect that the operating margin can be expanded.

(2) Since the above (1) makes it possible to substantially expand the level margin of the input signal supplied from the external terminal, it is possible to increase the tolerance of the noise level generated in the ground line and the power supply line. This makes it possible to increase the operating current, thereby achieving the effect of realizing high-speed operation.

(In an internal circuit that combines a 31CM OS circuit and a bipolar transistor, a relatively large current flows through the ground line due to the operation of the bipolar transistor, which has a larger current supply capacity than a MOSFET. Therefore, the floating ground line is relatively thick. Therefore, by making the actual logic threshold voltage of the input circuit as described above uniform by X degrees, the level margin can be expanded to prevent malfunctions caused by the above noise. The effect is that it is possible to increase the speed while preventing the problem.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, as an input circuit, in addition to the above CMO3 circuit, a drive MOS F
It may be configured by an inverter circuit consisting of an ET and a load MO3FET. In this way, the input circuit may be of any type as long as the logic threshold voltage is determined according to the conductance ratio of the MOSFET. In addition, the input circuit is simply an inverter circuit,
It may have a gate function in which receiving an input signal supplied from an external terminal is controlled by a control signal.

The present invention can be widely used in input circuits in which a logic threshold voltage is set by the conductance ratio of a MOS FET as described above, and various semiconductor integrated circuits having logic circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, to compensate for the voltage drop due to distributed resistance in the internal power supply line, the conductance of the MOSFET that sets the logic threshold voltage is varied so that the logic threshold voltage remains constant regardless of the voltage drop. By doing so, the actual logic threshold voltage can be set at a constant value, and the operating margin can be expanded.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram of a semiconductor integrated circuit such as a CMOS gate array to which this invention is applied, Fig. 2 is a conceptual diagram for explaining its operation, and Fig. 3 is an equivalent circuit diagram of a semiconductor integrated circuit such as a CMOS gate array to which this invention is applied. A simplified equivalent circuit diagram of a static type RAM, FIG. 4 is a static type RAM to which the present invention is applied.
FIG. 5 is a layout diagram showing one embodiment of the input circuit; FIG. 6 is a static RAM to which the present invention is applied.
FIG. 2 is a block diagram showing one embodiment of the present invention. G1-G3...Gate circuit, M-ARY, M-ARY
1~M-ARY4...Memory array (memory matrix), MC...Memory cell, GS...-1! 7s 7
7 selection circuit 4, C-DCR, C-DCR1 to C-DC
R4・-Column decoder, SAI~5A16・・Sense amplifier, COM-GE・・Internal control signal generation circuit, R-
DCR...Row decoder, ADB...Address buffer, C-3WI~C-3W4...Column switch

Claims (1)

[Claims] 1. In order to compensate for the voltage drop due to distributed resistance in the internal power supply line, the conductance of the MOSFET that sets the logic threshold voltage is varied to maintain a substantially constant logic threshold regardless of the voltage drop. A semiconductor integrated circuit device characterized by having a plurality of logic circuits each having a voltage. 2. The semiconductor integrated circuit device according to claim 1, wherein the logic circuit is a CMOS inverter circuit that receives an input signal supplied from an external terminal. 3. The semiconductor integrated circuit device according to claim 1, wherein the input buffer for receiving an input signal supplied from an external terminal is a static RAM configured by a CMOS inverter circuit. circuit device.