JPS6353799A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To lower noise level without sacrificing the operating speed of reading of low-level output by distorting the logic threshold voltage for sense amplifiers that respectively receive read signals sequentially from the memory blocks in the order starting from the memory block close to a word line selection circuit sequentially. CONSTITUTION:The plural memory blocks M-ARY0-M-ARY7 are constituted to a common word line constituting a memory array M-ARY. The logic threshold voltage for the sense amplifiers SA0-SA7 that respectively receives a reading signal from the memory blocks M-ARY0-M-ARY7 in the order starting from the block M-ARY0 which is close to the word line selection circuit XDCR sequentially is distorted, in order to speed up the reading of storage information corresponding to the low level of output signals transmitted to an external terminal. Accordingly, since the read signals of storage information are outputted time-sequentially from said memory blocks in the order starting from the M-ARY0 close to the word line selection circuit XDCR sequentially the noise level can be lowered without sacrificing the operating speed of a reading of low-level output.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
MOSFET (insulated gate field effect transistor)
This technology is effective for use in EPROMs (erasable and programmable read-only memories) that read information consisting of multiple bits.

[Conventional technology]

A ROM in which a read signal consisting of 8 bits is sent out by a tri-state output buffer is known (for example,
(See "Hitachi IC Memory Data Book" published by Hitachi, September 1983, pp. 329-330).

[Problem that the invention seeks to solve]

In a ROM in which a plurality of bits are read as described above, a plurality of output buffer circuits are provided that drive a relatively large load capacitance in response to a sense output of a read signal from a memory array.

In each of the output sofa circuits mentioned above, a relatively large load capacitance (stray capacitance) consisting of stray capacitance existing in a mounting board such as a printed wiring board that is coupled to the output terminal and the input capacitance of a signal input device, etc. It is required to be able to drive.

Therefore, the output MO3FET causes a relatively large current to flow through the ground line of the circuit in order to discharge the load capacitance. Since the ground line of the circuit in the semiconductor integrated circuit has non-negligible resistance and inductance components, relatively large noise is generated when the output MOSFET is activated and discharges the load capacitance. Particularly, when outputting 8-bit signals in parallel as described above, in the worst case, a relatively large level of noise is generated on the ground line of the circuit due to the operation of outputting the 8-bit signals. This noise is fed back to, for example, an address buffer or a sense amplifier that amplifies a relatively small read signal from a memory array, causing a problem in that the level margin becomes i, and in the worst case, oscillation occurs.

Therefore, it is conceivable to reduce the peak value of the noise level by shifting the operation timings of the plurality of output sofas and temporally dispersing the noise generated in the ground line of the circuit. However, in this case, the signal propagation delay time is substantially increased, and as a result, it takes a relatively long time to send all bits to the external terminal, which hinders high-speed operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that reduces the noise level generated on a ground line during output operation and realizes high-speed operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of memory blocks are configured on a common word line that constitutes a memory array, and a sense amplifier receives a read signal from each memory block in order from the memory block located at a position close to the word line selection circuit. By biasing the logic threshold voltage of the memory, the memory information corresponding to the low level of the output signal sent to the external terminal is read out quickly.

[For production]

According to the above-mentioned means, since the readout signal of the stored information is outputted in a time-series manner starting from the memory block located close to the word line selection circuit, the operation speed is not sacrificed (no noise is generated). The level can be reduced.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a memory array section when the present invention is applied to an EFROM device.

Although not particularly limited, each circuit element in the figure may be a known CM.
With O3 (complementary MO3) integrated circuit manufacturing technology, 1
formed on a semiconductor substrate such as single crystal silicon.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MO3
An FET has a source region, a drain region formed on the surface of a semiconductor substrate, and a thin gate on the surface of the semiconductor substrate between the source region and the drain region. ! It is composed of a gate electrode made of polysilicon formed through a ll& film. The P-channel MO3FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate of a plurality of N-channel MOS FETs formed thereon, and is coupled to the reference voltage terminal Vss to which the ground potential of the circuit of FIG. 1 is applied. The N-type well region constitutes the substrate gate of the P-channel MO3FET formed thereon. The substrate gate of the P-channel MOS FET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

Although not particularly restricted, the EFROM device of this embodiment:
X, Y address signals AX, A supplied from external terminals
A complementary address signal formed through an address buffer receiving Y is supplied to an address decoder DCR. In the figure, an address buffer and an address decoder are shown as the same circuit blocks XADB-DCR and YADB-DCR, respectively. Although not particularly limited, the address buffers XADB and YADB are activated by an internal chip selection signal ce, take in address signals AX and AY from external terminals, and output an internal address signal having the same phase as the address signal supplied from the external terminal. A complementary address signal consisting of an address signal of opposite phase is formed.

Row (X) address decoder (X)DCR forms a selection signal for word line W of memory array M-ARY according to a complementary address signal of address buffer XADB.

Column (Y) address decoder (Y) DCR forms a selection signal for the data line of memory array M-ARY according to a complementary address signal of address buffer YADB.

The memory array M-ARY is typically 1
Two memory blocks are shown. This memory block is a MISFE with multiple floating gates.
T, e.g. FAMO3) transistors (non-volatile memory elements...MOS FETQ1 to Q6) and word line Wl
, W2 . . . and data lines D1 to Dn.

FAMo placed in the same row in the memory block
The control gates of the S transistors Q1 to Q3 (Q4 to Q6) are connected to the corresponding word line Wl (W2).
FAMO3) transistors Ql, Q4-Q3. The drains of Q6 are connected to corresponding data lines D1 to Dn, respectively. The above FAM
Although not particularly limited, the common source line C3 of the OS transistors is grounded via a depletion type MOSFET Q10 whose gate receives the write signal we.

Although the memory array M-ARY is not particularly limited,
As shown in FIG. 2, the above memory block is M
-ARYO to M-ARY7, a total of eight sets are provided. 8 sets of memory blocks M-AR
YO-M-ARY7 is arranged in the - column on the chip chip in the order of memory blocks M-ARYO-M-ARY7 from the side closest to the row address decoder XDCR. Row address decoder XDCR
The word line selected by this is extended in the horizontal direction in FIG.
Commonly located in RY7.

Although the MISFET QIO shown in FIG. 1 is not particularly limited, each memory block M-
They are provided corresponding to ARYO to M-ARY7, and their conductances are made relatively small by the low level of the internal control signal we during writing. This results in
The potential of the common source line CS is set to a relatively high potential by making the conductance of the MO3FET QIO relatively small. When the potential of this common source line C3 is made relatively high, the threshold voltage of the transistor FAMO3) is made relatively high. Therefore, by supplying a write high voltage to the data line and making the word line non-selected, the effective threshold voltage of the non-selected FAMO3) transistor is increased, so that the leakage current flowing therein can be reduced. As a result, the penetrating current supplied from the external terminal is efficiently supplied to the selected FAMO3) transistor, so that an efficient write operation can be performed. Note that during the read operation, the conductance of the MO3FETQIO is made relatively large by the high level of the control signal;1. This results in
This increases the read speed.

Each data line D1~ constituting one memory block above
Dn is connected to a common data line CD via a column 3y receiving a selection signal formed by the address decoder DCR(Y) and selection switches Mo5FETQ7 to Q9.
connected to. Common data icD is provided corresponding to each memory block. The common data 'IacD is connected to an output terminal of a data input cover sofa DIB for writing which receives a write signal input from an external terminal I10.

The other memory blocks M-ARYI to M-ARY7 shown in FIG. 2 are also provided with column selection circuit switches MO3FET similar to those described above, and selection signals are generated by corresponding address decoders YDCRO to YDCR3. Note that the address decoders YDCRO to YDCR3 are not particularly limited to, but are respectively connected to memory blocks M-ARYO and 1, M-ARY2 and 3, and M-A.
A common selection signal is formed for two memory blocks such as RY4 and RY5 and M-ARY6 and 7.

This allows one bit for each memory block.
Memory access is performed in units of 8 bits in total.

Each of the above memory blocks M-ARYO to M-ARY7
A first stage amplifier circuit PA, which constitutes an input stage circuit of sense amplifiers SAO to SA7 and will be described next, is provided on the common data line CD provided corresponding to each of the sense amplifiers SAO to SA7.

That is, in FIG. 7JiJ1, the common data IcD shown in the above column is provided with an N-channel amplification MO3FETQ11 whose source is connected. Between the drain of this amplification MOS FET Q11 and the power supply voltage terminal Vcc, there is a P-channel type load MOS to which the circuit ground potential is applied to its gate.
FETQ 12 is provided. Above load M OS
The FETQ 12 performs an operation such as flowing a precharge current to the common data line CD for a read operation.

In order to increase the anger level of the amplified MO3FETQI 1,
Voltage of common data line CD; N-channel type drive M
The signal is supplied to the gate of the drive MO3FETQ13, which is the input of the inverting amplifier circuit consisting of the OSFETQL3 and the P-channel type load MOSFETQI4.

The output voltage of this inverting amplifier 4■ circuit is
Supplied to the gate of TQI 1.

Further, in order to prevent wasteful current consumption during the non-operation period of the sense amplifier, an N-channel MO3FETQI5 is provided between the gate of the amplification MOS FETQll and the ground potential point of the circuit. This MO3FE
The sense amplifier operation timing signal s is commonly applied to the gates of TQI 5 and the P-channel MO3FETQ14.
c is supplied.

When reading a memory cell, the sense amplifier operation timing signal 7 is set to low level, and MO3FETQ
I4 is turned on and MOS FETQ15 is turned off. The memory cell has a threshold voltage higher or lower than the selected level of the word line, depending on the write data.

If the memory cell selected by each address decoder X-DCR, Y-DCR is turned off even though the word line is set to the selection level, the common data line CD is The current is supplied to a relatively high level. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level.

In this case, the high level of the common data line CD is limited to a relatively low potential by supplying a relatively low level output voltage formed by an inverting amplifier circuit that receives this high level potential to the gate of MO3FETQII. Ru. On the other hand, the low level of the common data JCD is limited to a relatively high potential by supplying a relatively high level voltage formed by an inverting amplifier circuit receiving the low level t to the gate of the MO3FET QI1. By restricting the high level and low level of the common data vACD, it is possible to speed up the readout, regardless of the existence of stray capacitance or the like that limits the signal change speed on the common data line CD. can. In other words, such a high-speed read operation can shorten the time it takes for one level of the common data line CD to change to the other level when data is read out one after another from a plurality of memory cells. for,
The conductance of the load MO3FETQI2 is set relatively large.

Note that the MO3FET QI 1 for amplification performs the amplification operation of the gate-grounded source input, and outputs the output signal to the CM
Sense amplifier S configured by OS inverter circuit
Tell A. The output signal of this sense amplifier SA is amplified by the corresponding data output buffer DOB, although not particularly limited, and is sent out from the external terminal I10.

Further, the write signal supplied from the external terminal I10 is transmitted to the common data line CD via the data input buffer DIR. Also between the common data line corresponding to other memory blocks and the external terminal, a read circuit consisting of an input stage circuit, a sense amplifier, and a data output buffer similar to the above, and a write circuit consisting of a data buffer sofa are provided, respectively. .

The timing control circuit C0NT is connected to an external terminal CB.

Internal control signals ce, wτ according to the chip enable signal, output enable signal, program signal and high voltage for writing supplied to OE, PGM and VPI)
, sc, etc., and a read low voltage Vcc/write high voltage Vpp to be selectively supplied to the address decoder.

For example, if the chip enable signal CE is at a low level, the output enable signal OB is at a high level, and the program signal PGM is at a low level, the write mode is set, and the internal signal ve is set at a low level and ce is set at a high level. And address decoder circuit XDCR,Y
A high voltage vpp is supplied to the DCR and data input circuit DIR as its operating voltage.

Furthermore, if the chip enable signal CB is at a low level, the output enable signal OE is at a low level, the program signal PGM is at a high level, and vpp is a high voltage for writing, the verify mode is entered, and the internal signals we and ce are
is raised to a high level.

In this verify mode, each circuit XDCR, YD
The operating voltage of CR and DIB is the above-mentioned high voltage vpp.
It is switched and supplied like the power supply voltage Vcc from .

Furthermore, if the chip enable signal CE is at low level, the output enable signal OE is at low level, the program signal PGM is at high level, and Vpp is a low voltage for reading (same level as Vcc), the read mode is entered, and the internal signal we and ce is set to high level.

In this embodiment, in order to reduce the noise level generated at the ground potential of the circuit during the read operation from the EFROM device, the logic threshold voltages of the sense amplifiers SAO to SA7 are set as follows. That is, the logic threshold voltage VL7 of the sense amplifier SAT corresponding to the memory block M-ARY7 located farthest from the address decoder XDCR, which is the word line selection means (circuit), on the chip shown in FIG. Although not particularly limited, as shown in FIG. 3, is set to an intermediate level of the output signal (read high level and low level) of the first stage amplifier circuit PA.

Based on this (VL7), the address decoder
Memory block M-AR located near the DCR
In the order of Y6 to M-ARYQ, the logic threshold voltages VL6 to VLO of the sense amplifiers SA6 to SAO are biased stepwise to the low level side. In other words, the logic threshold voltage VLO of the sense amplifier SAO corresponding to the memory block M-ARYO arranged adjacent to the address decoder XDCR is set to the lowest potential, and the sense amplifiers SA1 to S
In the order of A7, the logic threshold voltages VLI to VL7 are increased stepwise. The output signals of each of the sense amplifiers SAO to SA7 are sent to an external terminal via the data output buffer DOB which performs the amplification operation as described above. Setting the logic threshold voltage of the sense amplifiers SAO to SA7 as described above is based on the P-channel M03FET and N
This can be achieved by appropriately setting the inter-channel O3FET and the no-conductance ratio. For example, the sense amplifier SAT, in which the logic threshold voltage VL7 is set to the intermediate potential between the read high level and the low level, has a P-channel inter-channel O8FET and an N-channel MO8FE.
The conductance with T is made equal. The other sense amplifiers SA6 to SAO whose logic threshold voltages are biased to the low level side have their respective logic threshold voltages VL6 to VLO.
If the conductance of the P-channel length OS FET is made the same,
The conductance of S FET is set to increase in the order of lines SA6 to SAO. The conductance is set by taking into account the difference in the mobility of carriers (electrons or holes).
N-channel MOS FET and P-channel MO3F
This can be realized by appropriately setting the L/W (channel length/channel width) ratio with respect to ET.

When a low level read is performed after all bits have been read at the high level at the external terminal I10, the high level at the external terminal I10 is pulled out to the low level, so a large noise level appears on the ground line of the circuit. In such a worst case, as shown in FIG. 3, the high-level read signal M from the memory block M-ARYO located closest to the address decoder XDCR, which is the word line selection circuit, as described above.
O rises fastest due to the resistance component in the word line and its parasitic capacitance. Here, the signal MO is the common data 'acD corresponding to the memory block M-ARYO.
This is the output of the first stage amplifier circuit PA which receives the potential. Since the logic threshold voltage VLO of the sense amplifier SAO is biased to the lowest level side as described above, the output of the sense amplifier SAO changes from high level to low level at the earliest timing. In response to this, the output of the data output buffer DOB which outputs the read signal MO from the memory block M-ARYO to the external terminal I10 first changes from high level to low level. Due to the operation of one data output buffer, noise NO appears on the ground potential line (that is, the ground potential terminal Vss) of the circuit.

Below, memory blocks M-ARYI to M-ARY7
In this order, the read signals M1 to M7 change from a low level to a high level with a delay depending on the resistance component in the word line and its parasitic capacitance, and the logic threshold voltage VLI of the sense amplifier SAI to SAT that detects this changes. By setting the potentials of VL7 to VL7 stepwise from the low level side to the high level side, the output signals of the respective sense amplifiers SAI to SAT change from high level to low level in time series. Therefore, the output signal of each data output buffer DOB also changes from high level to low level in time series. Therefore, as a result of the fact that the actual operation timing of each data output buffer DOB is performed in chronological order, the noise N1 to N7 of the grounding line of the circuit also occurs in chronological order at each operation timing, and the average noise is level can be significantly reduced. In this case, as described above, the potential of the logic threshold voltage VL7 of the sense amplifier SAT corresponding to the memory block M-ARY7 located farthest from the address decoder Since the voltage is set to the potential, the noise level can be reduced as described above without sacrificing the operating speed.

Note that in a high-level read operation to an external terminal, since the logic threshold voltage of the sense amplifier SAO is biased toward the low level side, determination of the low level of the read signal from the memory block M-ARYO is delayed. However, this memory block M-
ARYO is placed closest to the word line selection circuit. Therefore, since the selection operation of the word line is performed quickly, it is possible to prevent the read operation of the high level to the external terminal from being delayed. This also applies to other memory blocks. The delay in high-level read operations caused by the setting of the sense amplifier's rosin threshold voltage can be offset by the time difference between word line selection operations.This prevents high-level read output operations from becoming faster. There isn't.

The effects obtained from the above examples are as follows. In other words, (1) A plurality of memory blocks are configured on a common word line constituting a memory array, and each memory block is read out in order from the memory block located at a position close to the word line selection circuit among the memory blocks. By biasing the logic threshold voltage of the sense amplifier that receives the signal,
By speeding up the readout of stored information corresponding to the low level of the output signal sent to the external terminal, the readout signal of stored information is read out in chronological order starting from the memory block located near the word line selection circuit. Therefore, the effect of reducing the noise level can be obtained without sacrificing the read operation speed of the output low level.

(2) According to (1) above, in the high-level output read operation, the delay caused by the deviation of the logic threshold voltage of the sense amplifier can be offset by the timing of the word line selection operation.
The effect is that the speeding up of the operation is not hindered.

(3) By using an extremely simple configuration in which the logic threshold voltage of the sense amplifier is biased in accordance with the layout position of the memory block with respect to the word line selection circuit, it is possible to reduce the noise level and increase the speed of operation. You can get the effect that you can.

Also, if you want to invert the output of the sense amplifier with an output sofa and output it to an external terminal, use the address decoder XD.
The logic threshold voltages of the sense amplifiers are increased in order from the sense amplifier corresponding to the memory block farthest to the CR toward the nearest memory block.

Note that in this case, noise generation is dispersed in consideration of the delay of the word line.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, the memory array M-ARY uses mask ROM, MNOS (metal nitride oxide semiconductor), and FLOTO in addition to those using the FAMOS transistors mentioned above.
It may be an X-type EEPROM (Electrically Erasable & Programmable ROM) or the like.

In addition to the word lines of all memory blocks selected by one common address decoder, the word lines of all memory blocks are
In the figure, the address decoder XDCR is located at the center of eight memory blocks (memory blocks M-ARY3 and M-A
RY4), and a pair of word lines may be arranged corresponding to memory blocks divided into left and right.

In this case, M-
ARY3 and M-ARY4 are arranged at the closest positions, and memory blocks M-ARYO and M-ARY7 are arranged at the farthest positions.

Due to the positional relationship of the memory blocks with respect to the word line selection circuit, each sense amplifier SAO to S
The biasing of the logic threshold voltage of A7 is performed as above.

In addition to the CMOS inverter circuit, the sense amplifier
It may also be a differential amplifier circuit. In this case, a logic threshold voltage set in the above level relationship is generated from a predetermined reference voltage generation circuit.

The above explanation has mainly been about the case where the invention made by the inventor of the present application is applied to an EF ROM device, which is the technical field behind the invention, but the invention is not limited to this, and the invention is not limited to this, and the invention is not limited to this. The present invention can be widely used in semiconductor memory devices in which a plurality of memory blocks are connected to a common word line.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, a plurality of memory blocks are configured on a common word line that constitutes a memory array, and a sense amplifier receives a read signal from each memory block in order from the memory block located near the word line selection circuit. By biasing the logic threshold voltage of the memory block to speed up the reading of stored information corresponding to the low level of the output signal sent to the external terminal, Since the readout signal of the stored information is outputted in a time-series manner, the noise level can be reduced without sacrificing the readout operation speed of the output low level.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an EPROM device to which the present invention is applied. FIG. 2 is a block diagram showing the entire memory array M-ARY, selection circuit, and sense amplifier. , is an operation waveform diagram for explaining an example of the read operation. XADB, YADB... address buffer, XDCR...
・X address decoder, YDCRO~3...Y address decoder, MARY...memory array, M-ARYO~
7...Memory block, 5A (SAO ~ 7)...Sense amplifier, DIR...Data input cover sofa, DOB...Data output buffer, C0NT...Timing control circuit Patent attorney Katsuma Ogawa, ・ ] Ni Fig. 1 -()Va. Ji Van Fig. 2 Fig. 3 v881Δ:---J~-

Claims (1)

[Claims] 1. A matrix arrangement of memory elements having substantially higher or lower threshold voltages with respect to selected levels of word lines coupled to gates according to stored information; , a memory array configured with a plurality of memory blocks on a common word line, and a plurality of data readout circuits corresponding to each of the memory blocks, and among the plurality of data readout circuits, a word line selection circuit is provided. In order from the memory block located closest to the
A semiconductor memory device characterized in that logic threshold voltages of sense amplifiers each receiving a read signal are biased to a level that speeds up reading of stored information corresponding to a low level of an output signal sent to an external terminal. 2. The logic threshold of the sense amplifier that receives the read signal from the memory block located farthest from the word line selection circuit among the memory blocks mentioned above is approximately an intermediate level between the high level and the low level of the read signal. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is set to .