JPH059879B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention relates to a semiconductor memory device.
Specifically, it relates to write operations in programmable read-only memory (ROM).

(Conventional technology) Generally, programmable read-only
The memory (PROM) is configured as shown in FIG. 6, for example. In FIG. 6, 11 is a memory cell array, and this memory cell array 11 is a floating gate type MOS as a memory cell.
The transistors 12 ₁₁ to 12 mn are arranged in a matrix. Each control gate of the floating gate type MOS transistors 12 ₁₁ to 12mn is connected to a low signal line 13 ₁ to 13m for each row, and each drain is connected to a column signal line 14 ₁ for each column.
~14n are connected, and a ground point is connected to each source. The output ends of the row decoder 15 are connected to the row signal lines 13 ₁ to 13m, and the column selection circuit 16 is connected to the column signal lines 14 ₁ to 14n. This column selection circuit 16 includes column selection MOS transistors 17 1 to ₁₇ whose conduction is controlled by decode outputs A ₁ to An of column decoders (not shown).
17n, these MOS transistors 17 ₁
The above column signal line 1 is connected to one end of ~17n, respectively.
4 ₁ to 14n are connected, and the other ends are commonly connected.
This common connection point has a
MOS transistor 18 and writing (program)
One end of each MOS transistor 19 is connected to each other. The above lead MOS transistor 18
The other end is connected to the input end of the sense circuit 20 and is also connected to the power supply _Vcc via a resistor 21.
Continuity is controlled by read mode signal RM. on the other hand,
A high voltage power supply _Vpp is connected to the other end of the programming MOS transistor 19, and conduction is controlled by the output of the programming gate circuit 22. This programming gate circuit 22 includes a buffer circuit 23 whose operating power supply is V _pp and whose output terminal is connected to the gate of the MOS transistor 19, and whose output terminal is connected to the input terminal of the buffer circuit 23 and receives a program mode signal PM. It is composed of an AND gate 24 that takes a logical product of program data.

In the above configuration, the read mode signal
RM is “1” level, program mode signal PM
When is at “0” level, MOS transistor 1
8 is on, the MOS transistor 19 is off, and the memory cell 12ij (i=1 to 1) selected by the row decoder 15 and column decoder
m, j=1 to n) is supplied to the sense circuit 20. Then, amplification is performed in this sense circuit 20, and read data Dout is obtained from its output terminal.

On the other hand, when the program mode signal PM is at the "1" level and the read mode signal RM is at the "0" level, the MOS transistor 18 is turned off, and when the data is "1", the output of the AND gate 24 is "1". level, and the MOS transistor 19 is turned on. As a result, the MOS _transistor 19,
and column selection MOS transistor 17j (j
A high voltage is applied to the column signal line 14j via the
is applied to Then, level "0" is written into the memory cell 12ij located at the intersection of the row selected by the row decoder 15 and the column selected by the column decoder. On the other hand, when the program mode signal PM is at the "1" level, the read mode signal RM is at the "0" level, and the data is "0", the output of the AND gate 24 is at the "0" level, and the MOS transistor 19 is turned off. Become. At this time, the MOS transistor 18 is also in an off state. Therefore, the memory cell 12 selected by the row decoder 15 and column decoder
No high voltage is applied to ij, and data "1" is written.

FIG. 7 focuses on the case where one memory cell is programmed in the circuit of FIG. 6, and shows necessary MOS transistors extracted.
Programming data "0" into the PROM memory cell 12ij is performed as follows. That is, the gate potentials of the programming MOS transistor 19, column selection MOS transistor 17j, and memory cell 12ij are set to the _Vpp level (21V or 12.5V), and each MOS transistor 1
9, 17j, and 12ij are set to the on state. As a result, the programming MOS transistor 19
Floating gate type as memory cell from high voltage power supply V _pp connected to the drain of
Source of MOS transistor 12ij (ground point GND)
A current I flows toward memory cell 1, and hot carriers (electrons) induced by this current I
2ij floating gate. This state is a state in which data "0" is written into the memory cell 12ij. On the other hand, when the gate potential of the programming MOS transistor 19 is set to the GND level, the MOS transistor 19 is turned off even if the gate potential of the column selection MOS transistor 17j and the control gate potential of the memory cell 12ij are at the V _pp level. For high voltage power supply
No current flows from _Vpp to memory cell 12ij. As a result, no electrons are injected into the floating gate of the memory cell 12ij, and the write data becomes "1". In the above description, the MOS transistors 19, 17j, and 12ij are all described as N-channel MOS FETs.

FIG. 8 shows the circuit shown in FIG. 7 rewritten to the state when data "0" is programmed. Assuming that a high voltage _Vpp is applied to the gate and source of the programming MOS transistor 19, this MOS transistor 19 is in an on state. At this time, the drain potential Va of the MOS transistor 19 does not reach the V _pp level, and if the MOS transistor 19 is an enhancement type and its threshold voltage is V _THN , then "Va≦V _pp -
V _THN ”. In reality, there is a potential difference between the drain potential Va and the substrate voltage (GND), so the back gate bias effect causes
The apparent threshold voltage of the MOS transistor 19 increases, and the drain potential Va becomes “V _pp −
V _THN ”. In addition, column selection MOS
The drain potential Vb of the transistor 17j is approximately equal to the above-mentioned Va, and as a result, the potential Va is applied to the source of the memory cell 12ij. At this time, if the level of the high voltage power supply V _pp is sufficiently high, there is no particular problem with programming. However, in recent years, there has been a trend towards lowering the level of the high voltage power supply _Vpp . This is because high-potential signal lines running inside an LSI can accelerate internal deterioration or cause latch-up in CMOS-LSIs. Another factor is that it is necessary to generate a high voltage externally, but generating this high voltage is difficult. As described above, when the level of the high voltage power supply _Vpp is lowered, it becomes necessary to flow a current sufficient to cause hot carriers between the source and drain of the memory cell 12ij even at a low voltage. For this, the above column selection MOS
It is necessary to bring the drain potential Vb of the transistor 17j as close to the _Vpp level as possible. However, as mentioned above, the programming MOS transistor 1
A drop in potential by the threshold voltage V _THN of 9 is unavoidable. For this reason, the current between the source and drain of the memory cell 12ij also decreases, which has the drawback of poor efficiency when writing "0" to the memory cell.

(Problems to be Solved by the Invention) As mentioned above, in conventional semiconductor memory devices (PROMs), the write voltage decreases by the threshold voltage of the programming MOS transistor, so the current between the source and drain of the memory cell decreases. The disadvantage is that the efficiency of injecting electrons into the floating gate is low.

This invention was made in view of the above circumstances, and its purpose is to supply sufficient current to the memory cell even when the write voltage is relatively low, and to inject electrons into the floating gate. An object of the present invention is to provide a semiconductor memory device that can improve time efficiency.

[Structure of the invention] (Means and effects for solving the problems) That is, in order to achieve the above object, in this invention, a P-channel type MOS transistor is provided as a MOS transistor for selecting a program mode. In addition, two types of column selection circuits are provided, one for read mode and one for program. N-channel MOS transistors are used for read mode, and P-channel MOS transistors are used for program mode.
By using MOS transistors, the write voltage is prevented from decreasing due to the threshold voltage of the N-channel MOS transistor.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, the same components as in FIG. 6 are given the same reference numerals, and the memory cell array 11 is formed by floating gate type MOS transistors 12 ₁₁ to 12 mn as memory cells arranged in a matrix. Ru. The above floating gate type MOS transistor 12 ₁₁
Each control gate of ~12mn has a
Row signal lines 13 ₁ to 13m are connected to each row, column signal lines 14 ₁ to 14n are connected to each column, and each source is connected to a ground point. The output end of the row decoder 15 is connected to the row signal lines 13 ₁ to 13m. In addition, the column signal lines 14 ₁ to 1
A column selection circuit 25 for reading and a column selection circuit 26 for writing are connected to 4n, respectively. The above readout column selection circuit 25
consists of N-channel type MOS transistors (read column selection MOS transistors) 27 ₁ to 27n whose conduction is controlled by decode signals A ₁ to An output from a read column decoder (not shown), and these MOS transistors 27 ₁ to 27n Each of the column signal lines 14 1 to 14n is connected to one end of the column signal line 14 ₁ to 14n.
are connected, and the other end is connected in common. On the other hand, the write column selection circuit 26 selects the decode signals ₁ to 1 of the write column decoder (not shown).
P-channel type MOS transistor (write column selection MOS transistor) whose conduction is controlled by 2
The column signal lines _{14 1 to} 14n are connected to one end of each of these MOS transistors 28 ₁ to 28n, and the other ends thereof are commonly connected. One end of the read N-channel MOS transistor 18 is connected to the common connection point on the other end side of the read column selection MOS transistors 26 ₁ to 26n, and the write column selection MOS transistors 28 ₁ to 28n have one end connected thereto. One end of a P-channel MOS transistor 29 for writing (programming) is connected to the common connection point on the other end side. The other end of the read MOS transistor 18 is connected to the input end of the sense circuit 20, and is also connected to the power supply _Vcc via a resistor 21, and conduction is controlled by the read mode signal RM. On the other hand, a high voltage power supply _Vpp is connected to the other end of the programming MOS transistor 29.
The conduction of the MOS transistor 29 is controlled by the output of the buffer circuit 23 whose operating power supply is _Vpp . The input terminal of this buffer circuit 23 has a program mode signal.
The output end of a NAND gate 30 that takes the logical product of PM and program data is connected.

Next, the operation in the above configuration will be explained. First, during read operation, the read mode signal RM is at "1" level, and the program mode signal
PM becomes the "0" level, the MOS transistor 18 is turned on, and the MOS transistor 29 is turned off. At this time, one of the outputs A ₁ to An of the read column decoder (not shown) becomes " ₁ " level, and the selected MOS transistor 27j (j=1 to n ) is turned on.
At this time, the decode outputs ₁ to 1 of the write column decoders are all at the _Vcc level, and the write column selection MOS transistors 28 ₁ to 28n are turned off. Therefore, the data read from the memory cell 12ij (i=1 to m, j=1 to n) selected by the row decoder 15 and the read column decoder is supplied to the sense circuit 20. The read data is amplified by this sense circuit 20, and the read data is output from its output terminal.
Get Dout.

On the other hand, in the write mode, the program mode signal PM is at the "1" level, the read mode signal RM is at the "0" level, and all the outputs of the read column decoders are at the GND level, and the MOS transistor 18 and the read selection All of the MOS transistors 27 ₁ to 27n are turned off. Here, when the program data is "1", the output of the NAND gate 30 is "0"
level, and the MOS transistor 19 is turned on. This allows the high voltage power supply _Vpp to
MOS transistor 29 and write column selection MOS transistor 28j (j=
1 to n), a high voltage is applied to the column signal line 14j. The memory cell 1 located at the intersection of the row signal line 13i in the row selected by the row decoder 15 and the column signal line 14j in the column selected by the write column decoder
Data “0” is written to 2ij. On the other hand, when the program mode signal PM is at the "1" level, the read mode signal RM is at the "0" level, and the data is "0", the output of the NAND gate 30 is "1".
level, and the MOS transistor 29 is turned off. At this time, the MOS transistor 18 is also in an off state. Therefore, the high voltage _Vpp is not applied to the memory cell 12ij selected by the column decoder for writing and the row decoder 15, and no writing is performed (data "1" is written).

Figure 2 focuses on writing "0" to one memory cell in the circuit of Figure 1 above, and shows the necessary information.
MOS transistors are extracted and shown. A GND level is applied to the gates of the program MOS transistor 29 and write column selection MOS transistor 28j, and a high voltage is applied to the back gates of these MOS transistors 29 and 28j.
V _pp is applied. The above MOS transistor 29,
Since MOS transistor 28j is of the P channel type, there is no drop in level due to the threshold voltage, and the drain potentials Vc and Vd of MOS transistors 29 and 28j are respectively the same potential as _Vpp , which is the source potential of MOS transistor 29. Therefore, memory cell 1
A high voltage _Vpp is applied between the source and drain of 2ij, and a sufficient current for writing data "0" is obtained.

Note that an N-channel MOS transistor and a P-channel MOS transistor are used for reading and writing, respectively.
Two column selection circuits 2 consisting of transistors
5 and 26 are provided for the following reasons. In other words, a P-channel type is used for writing.
Column selection circuit 26 consisting of MOS transistors
is used to apply the V _pp level to the drain of the memory cell as mentioned above, and the reason why an N-channel type MOS transistor is used for reading is when the source of the memory cell 12ij is at the GND level (memory cell 12 ₁₁ to 12mn are of N-channel type), this is to read out this GND level. In order to read the GND level, the read column selection MOS transistor needs to be an N-channel type. This is a P channel type MOS
If it is composed of a transistor, its drain potential will not be at the GND level, but will be V _THP higher than this.
This is because the potential becomes higher by (V _THP is the threshold voltage of the P-channel MOS transistor).

According to such a configuration, since there is no drop in the potential of the high voltage power supply _Vpp during programming of "0", efficient writing can be performed even if the level of the high voltage power supply _Vpp is set low. In addition, the above V _pp
By setting the level low, it is possible to prevent deterioration inside the LSI, prevent latch-up, and simplify the circuit that generates the high voltage V _pp inside the LSI.

FIG. 3 shows another embodiment of the invention. In FIG. 3, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.
That is, the read column selection circuit 25 and the write column selection circuit 2 in FIG.
6 is an N-channel MOS transistor 31 ₁ ~
31n and P channel type MOS transistor 32 ₁
It is constructed of complementary transmission gates 33 1 to 33n consisting of gates 33 ₁ to 33n. The column selection circuit 34 consisting of the transmission gates 33 ₁ to 33n operates in both read and write operation modes, and depends on the decode signals A ₁ to An of a column decoder (not shown) and its inverted signal ₁ to. controlled.

In the above configuration, the operation is basically the same as that of the circuit shown in Fig. 1, but the GND level during read operation is mainly output through the N-channel MOS transistor, and the _Vpp level during write operation is output mainly through the N-channel MOS transistor. is input mainly through a P-channel MOS transistor. Therefore, when writing data "0", the V _pp level does not drop by the threshold voltage V _THN of the N-channel MOS transistor, and when reading, the GND level is equal to the threshold voltage of the P-channel MOS transistor.
There is no increase in V _THP .

According to such a configuration, unlike the circuit shown in FIG. 1, there is no need for two column decoders for reading and writing, but it is sufficient to use the decoded output of one column decoder and generate its inverted signal. Therefore, the increase in pattern area due to application of the present invention can be reduced.

FIG. 4 shows another embodiment of this invention.
The column selection circuit 25 for reading and the column selection circuit 26 for writing in the circuit shown in FIG. 1 are distributed to both sides of the memory cell array 11 . In FIG. 4, the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. The reason for this configuration is that the memory cell array 11 is a floating gate type in order to increase the integration density.
Since the column signal lines 14 ₁ to 14n connecting the drains of the MOS transistors 12 ₁₁ to 12mn are arranged at very narrow pitches, if the column selection circuits 25 and 26 for reading and writing are located on the same side of the memory cell array 11 , , the signal line to the column decoder is an N-channel MOS transistor 2.
7 ₁ to 27n and P channel type MOS transistors 28 ₁ to 28n,
This is because a large pattern area is required for this portion, increasing wasted area for wiring. Also, if a P-channel MOS transistor and an N-channel MOS transistor are located close to each other, they will be susceptible to latch-up, so the P-channel MOS transistor
It is necessary to ensure element isolation between the MOS transistor and the N-channel MOS transistor (in program mode, a large current of several tens of mA flows through the write column selection MOS transistor, so a pattern that is resistant to latch-up is required). In order to solve these problems, the column selection circuits 25 and 26 for reading and writing are separated.

FIG. 5 shows an example of the pattern configuration of the write column selection circuit 26 in FIG. 4. In FIG. In FIG. 5, parts corresponding to those in FIG. 4 are given the same reference numerals, and 34 ₁ to 34 ₁₅ are aluminum wiring layers, 35 ₁ to 35 ₁₈ are contact parts, and 36 ₁ to 36 ₇ are polysilicon layers. Layer, 37 _1-3
7 ₂ is a diffusion layer, 38 ₁ to 38 ₄ are floating gates, and write column selection is done in the area surrounded by the broken line.
MOS transistors 28 ₁ to 28 ₄ are formed.

[Effects of the Invention] As explained above, the present invention provides a semiconductor memory that can supply sufficient current to the memory cell even when the write voltage is relatively low, and can improve the efficiency of injecting electrons into the floating gate. A device is obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a write operation in the circuit of FIG. 1, and FIGS. A circuit diagram for explaining another embodiment of the invention; FIG. 5 is a pattern plan view showing an example of the pattern configuration of the write column selection circuit in the circuit of FIG. 4;
FIG. 6 is a circuit diagram showing a conventional semiconductor memory device, and FIGS. 7 and 8 are diagrams for explaining the write operation in the circuit shown in FIG. 6, respectively. 12 ₁₁ ~12mn...Floating gate type
MOS transistor (memory cell), 11 ...memory cell array, 13 ₁ to 13m...low signal line,
15...Row decoder, _{141 to} 14n...Column signal line, ₁ to...Column decode signal for writing, 26...Column selection circuit for writing,
A ₁ ~ An……Column decode signal for reading,
25... Column selection circuit for reading, _Vpp ... High voltage power supply, 29... MOS transistor for writing, 18... MOS transistor for reading,
33 ₁ ~ 33n...transfer gate.

Claims (1)

[Scope of Claims] 1. A memory cell array composed of floating gate MOS transistors arranged in a matrix, a low signal line to which control gates of these floating gate MOS transistors are connected to each row, and this row a row decoder that supplies a row decode signal to a signal line to select the row direction of the memory cell array; a column signal line to which the drains of the floating gate MOS transistors are connected for each column; A column selection circuit for writing consists of a P-channel MOS transistor connected at one end and conduction controlled by a column decode signal for writing, and a column selection circuit for writing consisting of a P-channel MOS transistor connected at one end to the column signal line and controlled for conduction by a column decode signal for reading. a read column selection circuit composed of an N-channel MOS transistor; a column decoder that supplies the write column decode signal and read column decode signal to the write and read column selection circuits; and the write column decoder. A P-channel type write circuit that is connected to the other end of each P-channel type MOS transistor that constitutes the column selection circuit of , is turned on when writing to a memory cell, and supplies high voltage power to the selected memory cell. 1. A semiconductor memory device comprising a MOS transistor. 2. The P-channel MOS transistor of the write column selection circuit and the N-channel MOS transistor of the read column selection circuit constitute a transfer gate by connecting the corresponding MOS transistors in parallel for each column. 2. The semiconductor memory device according to claim 1, wherein the transfer gate is switching-controlled by a column decode signal outputted from the column decoder and its inverted signal. 3. The semiconductor memory device according to claim 1, wherein the writing column selection circuit and the reading column selection circuit are respectively arranged at both ends of the column signal line.