JPS61210461A - デ−タチェイン方式 - Google Patents

デ−タチェイン方式

Info

Publication number
JPS61210461A
JPS61210461A JP4871585A JP4871585A JPS61210461A JP S61210461 A JPS61210461 A JP S61210461A JP 4871585 A JP4871585 A JP 4871585A JP 4871585 A JP4871585 A JP 4871585A JP S61210461 A JPS61210461 A JP S61210461A
Authority
JP
Japan
Prior art keywords
register
subchannel
transfer
input
chain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4871585A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0378661B2 (enExample
Inventor
Toshiharu Oshima
大島　俊春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4871585A priority Critical patent/JPS61210461A/ja
Publication of JPS61210461A publication Critical patent/JPS61210461A/ja
Publication of JPH0378661B2 publication Critical patent/JPH0378661B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP4871585A 1985-03-12 1985-03-12 デ−タチェイン方式 Granted JPS61210461A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4871585A JPS61210461A (ja) 1985-03-12 1985-03-12 デ−タチェイン方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4871585A JPS61210461A (ja) 1985-03-12 1985-03-12 デ−タチェイン方式

Publications (2)

Publication Number Publication Date
JPS61210461A true JPS61210461A (ja) 1986-09-18
JPH0378661B2 JPH0378661B2 (enExample) 1991-12-16

Family

ID=12810995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4871585A Granted JPS61210461A (ja) 1985-03-12 1985-03-12 デ−タチェイン方式

Country Status (1)

Country Link
JP (1) JPS61210461A (enExample)

Also Published As

Publication number Publication date
JPH0378661B2 (enExample) 1991-12-16

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