JPS61208228A - Connection of integrated circuit element in ic card - Google Patents

Connection of integrated circuit element in ic card

Info

Publication number
JPS61208228A
JPS61208228A JP60048223A JP4822385A JPS61208228A JP S61208228 A JPS61208228 A JP S61208228A JP 60048223 A JP60048223 A JP 60048223A JP 4822385 A JP4822385 A JP 4822385A JP S61208228 A JPS61208228 A JP S61208228A
Authority
JP
Japan
Prior art keywords
integrated circuit
substrate
circuit element
card
cutout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60048223A
Other languages
Japanese (ja)
Inventor
Takayuki Okamoto
隆之 岡本
Takao Kitagawa
孝夫 北川
Kaname Tamada
玉田　要
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Priority to JP60048223A priority Critical patent/JPS61208228A/en
Publication of JPS61208228A publication Critical patent/JPS61208228A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

PURPOSE:To perform easy connection between an integrated circuit element and a substrate by connecting electrode parts of the integrated circuit element directly to those of the substrate without using conductors such as gold wires. CONSTITUTION:A member which is housed in an IC card is constituted by a substrate 2 on the surface of which wirings 1 on printed patterns are formed, a bottom plate 3 which is stuck to the substrate 2 and an integrated circuit 4. A cutout 5, in which the integrated circuit 4 is accomodated, is provided in the substrate 2 and wirings 1a are formed on the inside walls of the cutout 5. Electrode parts 6 which are connected to the wirings 1a are attached to the top edges of the integrated circuit element 4. The member is assembled with those components in such a manner that the integrated circuit element 4 is connected to the substrate 2. The IC card is formed by incorporating the substrate 2 accomodating the integrated circuit element 4 in this manner into the card body.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣカードに収納される基板に集積回路素子
を組込むに際して、該基板と素子との間の接続を有効に
行なう、ＩＣカードの集積回路素子を結線する方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides an IC card that effectively connects an integrated circuit element to a board housed in the IC card when the integrated circuit element is incorporated into the board. The present invention relates to a method of wiring integrated circuit elements.

〔従来の技術〕[Conventional technology]

一般に、ＩＣカードは印刷配線のパターンを施こした基
板に集積回路素子を組込み、この基板をカード本体に収
納することにより形成さる。そして、集積回路素子と基
板との間の接続は、従来はワイヤボンディングにより行
なうようにしていた。Generally, an IC card is formed by incorporating an integrated circuit element into a substrate having a printed wiring pattern, and housing this substrate in a card body. Conventionally, the connection between the integrated circuit element and the substrate has been made by wire bonding.

このワイヤボンディングは細い金線を使用し、この金線
の両端をそれぞれ素子側と基板側とに結着するものであ
る。さらに、この基板における素子収納部に合成樹脂に
よる封止を行なうことによって、当該ワイヤボンディン
グによる結線部分を保護するようにしていた。This wire bonding uses a thin gold wire, and both ends of the gold wire are bonded to the element side and the substrate side, respectively. Furthermore, by sealing the element housing portion of this substrate with synthetic resin, the connection portion by the wire bonding is protected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述したように、ワイヤボンディングにより集積回路素
子の接続を行なうために、極めて細い金属で結線する必
要があるが、２の結線作業は著しく困難かつ面倒となる
だけでなく、たとえ樹脂封止を行なっても、当該結線部
分を十分に保護することができず、ＩＣカードの曲げ、
ねじり試験を行なう際、また長期間使用中に前述の結線
部分が損傷する欠点があった。As mentioned above, in order to connect integrated circuit elements by wire bonding, it is necessary to connect them with extremely thin metal, but the connection work in step 2 is not only extremely difficult and troublesome, but even if resin encapsulation is used, However, the wiring part cannot be sufficiently protected, and the IC card may be bent or
There was a drawback that the above-mentioned connection portions were damaged during torsion tests and during long-term use.

本発明は軟土の点に鑑みてなされたもので、集積回路素
子の基板への接続を容易かつ効率的に行なうことができ
、しかもこの接続部分に必要な強度を持たせることがで
きるようにしたＩＣカードの集積回路素子の結線方法を
提供することを目的とするものである。The present invention was developed in consideration of the problem of soft soil, and it is possible to connect an integrated circuit element to a substrate easily and efficiently, and to provide the necessary strength to this connection part. The object of the present invention is to provide a method for connecting integrated circuit elements of an IC card.

ｃ問題点を解決するための手段〕 前述の目的を達成するために、本発明の方法は、表面に
印刷配線のパターンが施こされた基板を切り抜くことに
より切抜部を形成すると共に、該切抜部の内周壁に前記
印刷配線と接続された配線を形成し、前記基板に底板を
貼着することによって、前記切抜部により画成される素
子収納用凹部を形成し、周縁部に電極部を形成した集積
回路素子を該素子収納用凹部に収納して、該電極部を前
記内周壁の配線と結着する構成としたことを、その特徴
とするものである。Means for Solving Problem c] In order to achieve the above-mentioned object, the method of the present invention forms a cutout by cutting out a substrate having a printed wiring pattern on its surface, and A wiring connected to the printed wiring is formed on the inner peripheral wall of the part, and a bottom plate is attached to the substrate, thereby forming a recess for storing an element defined by the cutout part, and an electrode part is formed on the periphery of the part. It is characterized in that the formed integrated circuit element is housed in the element housing recess, and the electrode part is connected to the wiring on the inner circumferential wall.

〔実施例〕〔Example〕

以下、本発明の実施例を図面に基づいて詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.

まず、ＩＣカードに収納される部材は、第１図に示した
ように、表面に印刷配線のパターンを施こしてなる配ｖ
Ａ１が形成された基板２と、該基板２に貼着される底板
３と、集積回路４とからなり基板２には該集積回路素子
４を収納する切抜部５が開設されると共に、該切抜部５
の内周壁に配線１ａが形成されている。また、集積回路
素子４の上縁部には前記配線１ａと結線される電極部６
が取付けられている。そして、これらの各部材を組立て
ることにより集積回路素子４を基板２と結線した状態に
組込み、このようにして集積回路素子４を組込んだ基板
２は、カード本体に収納させることにより、ＩＣカード
が形成されることになる。First, as shown in Fig. 1, the components stored in the IC card are printed wiring patterns on the surface.
It consists of a substrate 2 on which A1 is formed, a bottom plate 3 attached to the substrate 2, and an integrated circuit 4. The substrate 2 is provided with a cutout 5 for accommodating the integrated circuit element 4, and Part 5
Wiring 1a is formed on the inner circumferential wall of. Further, an electrode portion 6 connected to the wiring 1a is provided at the upper edge of the integrated circuit element 4.
is installed. Then, by assembling these parts, the integrated circuit element 4 is installed in a state where it is connected to the board 2, and the board 2 with the integrated circuit element 4 installed in this way is housed in the card body, so that it can be used as an IC card. will be formed.

そこで、前述の集積回路素子４を基板２に組込んで、そ
れらを結線する方法について説明する。Therefore, a method of incorporating the above-mentioned integrated circuit element 4 into the substrate 2 and connecting them will be explained.

まず、第２図に示したように、表面に配線パターンを描
くことにより配線１が設けられた基板２に、その配線１
の端部位置に板厚方向に貫通する貫通孔７所謂スルーホ
ールを穿設し、この貫通孔７内に配線パターンを描く際
に使用したと同一の導電材を充填する。然る後に、該貫
通孔７を２分割する位置で基板２を切り抜くことにより
、内周壁に配線１ａを形成した切抜部５を形成する。こ
こで、この切抜部５は集積回路素子４を収納させるもの
で、該集積回路素子を略密嵌状に収納させるために、該
切抜部５の形状は、集積回路素子４の外形より僅かに大
きい寸法とするのが好ましい。First, as shown in FIG.
A so-called through hole 7 is formed at the end position of the plate and penetrates in the thickness direction of the plate, and the same conductive material used in drawing the wiring pattern is filled in the through hole 7. Thereafter, by cutting out the substrate 2 at a position where the through hole 7 is divided into two, a cutout 5 in which the wiring 1a is formed is formed on the inner peripheral wall. Here, the cutout 5 is used to house the integrated circuit element 4, and in order to house the integrated circuit element in a substantially tight fit, the shape of the cutout 5 is slightly smaller than the outer shape of the integrated circuit element 4. Larger dimensions are preferred.

次に、前記基板２に底板３を貼着することによって、該
基板２に形成された切抜部５と底板３とによって素子収
納用凹部８が形成されることになる。さらに、前述の素
子収納用凹部８内に集積回路素子４を収納させるのであ
るが、この場合において、集積回路素子４の電極部６を
取付けた位置にハンダボールを取付けておく。このハン
ダボールの作用により集積回路素子４は完全には素子収
納用凹部８内には収納されず、底板３から浮き上った状
態となっている。そこで、この状態で基板２を炉に入れ
て加熱すると、ハンダボールが溶解するので、上部より
集積回路素子４を上方から押圧すると、該集積回路素子
４は素子収納用凹部８内に埋入すると共に、このハンダ
部９を介して電極部６と配線１ａとが結線されることに
なる。Next, by attaching the bottom plate 3 to the substrate 2, an element housing recess 8 is formed by the cutout 5 formed in the substrate 2 and the bottom plate 3. Furthermore, the integrated circuit element 4 is housed in the aforementioned element housing recess 8, and in this case, a solder ball is attached to the position where the electrode part 6 of the integrated circuit element 4 is attached. Due to the effect of the solder balls, the integrated circuit element 4 is not completely housed in the element housing recess 8, but is lifted up from the bottom plate 3. Therefore, when the substrate 2 is placed in a furnace and heated in this state, the solder balls are melted, and when the integrated circuit element 4 is pressed from above, the integrated circuit element 4 is embedded in the element storage recess 8. At the same time, the electrode portion 6 and the wiring 1a are connected through the solder portion 9.

前述のようにして集積回路素子４を組込んだ基板２は、
ＩＣカードのカード本体における基板収納用凹部内に収
納した状態に装着されて使用される。而して、集積回路
素子４における結線部は金線等による配線を使用しては
おらず、ハンダ付けにより直接接続させるようにしてい
るから、当該結線部分の強度は著しく゛良好で、ＩＣカ
ードに比較的大きな曲げ力やねじり力が作用しても、当
該結線部分が損傷するおそれはない。そして、底板３を
ステンレス板等の大きな強度を有する部材で形成すれば
、集積回路素子４は素子収納用凹部８内に密嵌し、極め
て安定的に保護されるようになリ、また基板２は軽量の
部材で必要最小限度、即ち集積回路素子４の厚みより僅
かに肉厚に形成でき、全体重量の軽減化薄肉化を図るこ
とができる。The substrate 2 incorporating the integrated circuit element 4 as described above is
The IC card is used by being installed in a board storage recess in the card body of the IC card. Since the wiring in the integrated circuit element 4 does not use wires such as gold wire, but is directly connected by soldering, the strength of the wiring is extremely good, and the IC card is Even if a relatively large bending force or twisting force is applied to the wire, there is no risk of damage to the wire connection portion. If the bottom plate 3 is made of a material having high strength such as a stainless steel plate, the integrated circuit element 4 will be tightly fitted into the element housing recess 8 and will be protected extremely stably. is a lightweight member and can be formed to the minimum necessary thickness, that is, slightly thicker than the thickness of the integrated circuit element 4, so that the overall weight can be reduced and the thickness can be reduced.

なお、前述の実施例では、切抜部５の内周壁に配線１ａ
を施こす方法として、基板２に貫通孔７を穿設し、この
貫通孔７に導電材を注入するようにしたが、例えば切抜
部５の内周壁に導電性のペーストを付着させ、これを焼
成することによっても配線を形成することができる。ま
た、集積回路素子４の電極部６と配線１ａとの間の接続
も前述と同様、導電性ペーストを介して行なうこともで
きる。In addition, in the above-mentioned embodiment, the wiring 1a is provided on the inner circumferential wall of the cutout 5.
As a method of applying this, a through hole 7 is made in the substrate 2 and a conductive material is injected into the through hole 7. Wiring can also be formed by firing. Further, the connection between the electrode section 6 of the integrated circuit element 4 and the wiring 1a can also be made via a conductive paste, as described above.

さらに、本発明の結線方法によれば、結線部分に十分な
強度が付与されるので、必ずしも樹脂封止を行なう必要
はないが、集積回路素子４の防湿保護を図るためには樹
脂封止等を行なうようにしてもよい。Furthermore, according to the wiring method of the present invention, sufficient strength is imparted to the wiring portion, so resin sealing is not necessarily required. You may also do this.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、集積回路素子の
電極部を金線等による配線を介することなく、直接基板
と接続させる構成としたから、その間における結線を容
易に行なうことができ、しかもこのようにして結線され
な部分は十分な機械的強度を有し、比較的大きな曲げ力
やねじリカ等がＩＣカードに作用しても、当該結線部分
が損傷するおそれはない。また、基板の切抜部内周壁に
形成される配線を、該基板の板厚方向に貫通する貫通孔
を穿設し、この貫通孔に導電材を充填した後に、当該部
位を切抜くことにより形成するようにすれば、この内周
壁における配線パターンを容易に設けることができるよ
うになる。As explained above, according to the present invention, since the electrode portion of the integrated circuit element is directly connected to the substrate without using wiring such as gold wire, wiring between them can be easily made. Furthermore, the unconnected portions have sufficient mechanical strength, and even if a relatively large bending force, screwdriver, etc. are applied to the IC card, there is no risk of damage to the connected portions. Further, the wiring to be formed on the inner peripheral wall of the cutout part of the substrate is formed by drilling a through hole penetrating the substrate in the thickness direction, filling the through hole with a conductive material, and then cutting out the part. By doing so, it becomes possible to easily provide a wiring pattern on this inner circumferential wall.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の方法により組付けられる部材の分解
斜視図、第２図は基板の切抜き加工前の状態を示す斜視
図、第３図は集積回路素子の組込み状態を示す断面図で
ある。 １．１ａ・・・配線、２・・・基板、３・・・底板、４
・・・集積回路素子、６・・・電極部、７・・・貫通孔
、８・・・素子収納用凹部。 ３Ａり仮 ４：稟穆−シ ６：思脳卸 第３図FIG. 1 is an exploded perspective view of members to be assembled by the method of the present invention, FIG. 2 is a perspective view showing the state before cutting out the board, and FIG. 3 is a cross-sectional view showing the integrated circuit element assembled. be. 1.1a... Wiring, 2... Board, 3... Bottom plate, 4
. . . Integrated circuit element, 6. Electrode portion, 7. Through hole, 8. Recessed portion for housing element. 3A Ripari 4: Rinmu-shi 6: Thinking Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）　表面に印刷配線のパターンが施こされた基板を
切り抜くことによって切抜部を形成すると共に、該切抜
部の内周壁に前記印刷配線と接続された配線を形成し、
該基板に底板を貼着することによって前記切抜部により
画成される素子収納用凹部を形成し、周縁部に電極部を
設けた集積回路素子を該素子収納用凹部に収納して、該
電極部を前記内周壁に形成した配線と結着させたことを
特徴とするＩＣカードにおける集積回路素子の結線方法
。(1) Forming a cutout by cutting out a substrate with a printed wiring pattern on the surface, and forming wiring connected to the printed wiring on the inner peripheral wall of the cutout,
A bottom plate is attached to the substrate to form a device storage recess defined by the cutout, and an integrated circuit device having an electrode portion on the periphery is stored in the device storage recess. A method for connecting an integrated circuit element in an IC card, characterized in that a portion of the integrated circuit element is connected to a wiring formed on the inner circumferential wall. （２）　前記切抜部内周壁における配線を、前記基板の
板厚方向に貫通する貫通孔を穿設し、該貫通孔に導電材
を充填した後に、当該貫通孔を分割する状態に切抜くこ
とにより形成したことを特徴とする特許請求の範囲第１
項記１のＩＣカードにおける集積回路素子の結線方法。(2) By drilling a through hole penetrating the wiring in the inner circumferential wall of the cutout in the thickness direction of the board, filling the through hole with a conductive material, and then cutting out the through hole to divide it. The first claim characterized in that
A method for connecting integrated circuit elements in the IC card according to item 1.
JP60048223A 1985-03-13 1985-03-13 Connection of integrated circuit element in ic card Pending JPS61208228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60048223A JPS61208228A (en) 1985-03-13 1985-03-13 Connection of integrated circuit element in ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60048223A JPS61208228A (en) 1985-03-13 1985-03-13 Connection of integrated circuit element in ic card

Publications (1)

Publication Number Publication Date
JPS61208228A true JPS61208228A (en) 1986-09-16

Family

ID=12797415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60048223A Pending JPS61208228A (en) 1985-03-13 1985-03-13 Connection of integrated circuit element in ic card

Country Status (1)

Country Link
JP (1) JPS61208228A (en)

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