KR200177247Y1 - Tack type semiconductor package - Google Patents
Tack type semiconductor package Download PDFInfo
- Publication number
- KR200177247Y1 KR200177247Y1 KR2019940021974U KR19940021974U KR200177247Y1 KR 200177247 Y1 KR200177247 Y1 KR 200177247Y1 KR 2019940021974 U KR2019940021974 U KR 2019940021974U KR 19940021974 U KR19940021974 U KR 19940021974U KR 200177247 Y1 KR200177247 Y1 KR 200177247Y1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor package
- lead
- tack
- circuit board
- printed circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 외부리드(3b)가 압정 형태로 형성된 압정형 반도체 패키지로서, 종래의 반도체 패키지가 가지고 있었던 외부리드 성형 작업시 외부리드의 잘못된 휨으로 인한 반도체 패키지의 불량과, 장착작업의 곤란함 및 반도체 패키지의 취급상 어려움을 해결하기 위한 것이다. 본 고안은 반도체 패키지(1)의 내부리드(3a)의 길이방향 중앙부를 절곡하여 반도체 패키지(1)의 저면에서 돌출됨과 아울러 그 절곡부인 돌출단부가 첨예한 압정형 외부리드(3b)를 형성한 것으로, 외부리드(3b)의 첨예한 돌출단부를 인쇄회로기판(6)상의 장착부위에 대고 눌러 반도체 패키지(1)를 가고정하거나 인쇄회로기판의 핀삽입홀(6')에 삽입하여 가고정한 후 납땜하여 장착하도록 한 것이다. 이러한 본 고안을 통해 외부리드(3b)가 휨으로 인한 종래 반도체 패키지의 문제점을 완전히 해결할 수 있게 되고 반도체 패키지의 취급이 용이하게 되는 장점이 있다.The present invention is a tack-type semiconductor package in which the outer lead 3b is formed in the form of a tack, and the defect of the semiconductor package due to the incorrect bending of the outer lead during the external lead forming operation of the conventional semiconductor package, the difficulty of the mounting operation, and This is to solve the difficulty in handling the semiconductor package. The present invention bends the central portion in the longitudinal direction of the inner lead 3a of the semiconductor package 1 to protrude from the bottom of the semiconductor package 1, and to form a tack type outer lead 3b having a sharp protruding end thereof. By pressing the sharp protrusion end of the outer lead 3b against the mounting portion on the printed circuit board 6, the semiconductor package 1 is temporarily fixed or inserted into the pin insertion hole 6 'of the printed circuit board. After soldering and mounting. Through the present invention, the external lead 3b can completely solve the problems of the conventional semiconductor package due to bending, and there is an advantage in that the handling of the semiconductor package is easy.
Description
제1도는 종래의 반도체 패키지를 도시한 것으로, 제1a도는 표면실장형 반도체 패키지의 단면도.1 illustrates a conventional semiconductor package, and FIG. 1A illustrates a cross-sectional view of a surface mount semiconductor package.
제1b도는 핀삽입실장형 반도체 패키지의 단면도.1B is a cross-sectional view of a pin-mount semiconductor package.
제2도는 종래 반도체 패키지의 실장상태를 보인 도면으로, 제2a도는 표면실장형 반도체 패키지의 실장상태를 보인 단면도.2 is a view showing a mounting state of a conventional semiconductor package, Figure 2a is a cross-sectional view showing a mounting state of a surface-mount semiconductor package.
제2b도는 핀삽입실장형 반도체 패키지의 실장상태를 보인 단면도.2B is a cross-sectional view showing a mounting state of a pin insertion type semiconductor package.
제3도는 본 고안 반도체 패키지의 구성을 보인 단면도.Figure 3 is a cross-sectional view showing the configuration of the semiconductor package of the present invention.
제4도는 본 고안 반도체 패키지의 실장상태를 보인 도면으로, 제4a도는 표면실장상태를 보인 단면도.Figure 4 is a view showing a mounting state of the semiconductor package of the present invention, Figure 4a is a cross-sectional view showing a surface mounted state.
제4b도는 핀삽입실장상태를 보인 단면도.Figure 4b is a cross-sectional view showing a pin insertion state.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 패키지 3 : 리드1: semiconductor package 3: lead
3a : 내부리드 3b : 외부리드3a: Internal lead 3b: External lead
4 : 칩4: Chip
본 고안은 반도체 패키지에 관한 것으로, 특히 인쇄회로기판에의 접합 및 반도체 패키지의 취급이 용이하도록 반도체 패키지를 압정형태로 형성한 압정형(Tack type)반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a tack type semiconductor package in which a semiconductor package is formed in a pushpin form to facilitate bonding to a printed circuit board and handling of the semiconductor package.
종래의 반도체 패키지는 제1도에서 보인 바와 같이 제1a도에 도시된 표면실장형 반도체 패키지(SMD형 반도체 패키지)와 제1b도에 도시된 핀삽입실장형 반도체 패키지의 두가지 종류가 있다.There are two types of conventional semiconductor packages, as shown in FIG. 1, a surface mount semiconductor package (SMD type semiconductor package) shown in FIG. 1A and a pin insertion type semiconductor package shown in FIG. 1B.
먼저, 표면실장형 반도체 패키지(1)는 칩(Chip)(4)이 반도체 패키지(1)의 내부중앙에 배치되어 있고 칩(4)내부의 회로와 반도체 패키지(1)의 외부로 연장되는 리드(Lead)(3)를 전기적으로 연결하는 와이어(2)가 반도체 패키지(1)의 내부에 있다.First, the surface mount semiconductor package 1 includes a chip in which a chip 4 is disposed in the center of the semiconductor package 1 and extends to the circuit inside the chip 4 and to the outside of the semiconductor package 1. A wire 2 electrically connecting the lead 3 is inside the semiconductor package 1.
그리고 상기 칩(4), 와이어(2) 및 리드(3)는 합성수지 등의 재료로 된 컴파운드(5)로 몰딩되어 하나의 반도체 패키지(1)를 형성한다.The chip 4, the wire 2 and the lead 3 are molded with a compound 5 made of a material such as synthetic resin to form one semiconductor package 1.
이때 반도체 패키지(1)의 측면을 통해 외부로 연장된 외부리드(3b)는 인쇄회로기판(6)에 장착되기에 적합한 모양으로 성형되는 포밍공정과 인쇄회로기판(6)상에 반도체 패키지를 고정하는 납땜작업을 거쳐 제2a도에 도시된 바와 같이 인쇄회로기판(6)에 실장된다.At this time, the external lead 3b extending to the outside through the side of the semiconductor package 1 is formed into a shape suitable for mounting on the printed circuit board 6 and the semiconductor package is fixed on the printed circuit board 6. After the soldering operation is mounted on the printed circuit board 6 as shown in Figure 2a.
제1b도에 도시된 핀삽입실장형 반도체 패키지는 표면실장형 반도체 패키지의 내부 구조는 동일하나 외부로 연장된 외부리드(3b)의 모양은 반도체 패키지(1)를 인쇄회로기판(6)의 핀삽입홀(6')에 끼워 납댐을 통해 장착될 수 있도록 성형된다. 핀삽입실장형 반도체 패키지가 인쇄회로기판(6)상에 실제로 장착된 모양이 제2b도에 도시되어 있다.In the pin-mounted semiconductor package shown in FIG. 1B, the internal structure of the surface-mount semiconductor package is the same, but the shape of the external lead 3b that extends to the outside is such that the semiconductor package 1 is the pin of the printed circuit board 6. Inserted into the insertion hole (6 ') is formed so that it can be mounted through the lead dam. The shape in which the pin-mount semiconductor package is actually mounted on the printed circuit board 6 is shown in FIG. 2B.
그러나 상기한 바와 같은 종래의 반도체 패키지는 반도체 패키지의 외부리드를 성형하는 포밍공정중에 외부리드가 잘못 휘어 불량으로 처리되는 경우가 종종 있었으며, 인쇄회로기판상에 반도체 패키지가 장착된 후에도 외부에서 가해지는 힘에 의해 외부리드가 휘어지게 되어 견고하게 부착되지 않고, 특히 표면실장형 반도체 패키지를 인쇄회로기판상에 장착하기 위해서는 납땜장치와 납땜용 재료를 양손에 잡은 상태에서 반도체 패키지를 인쇄회로기판상에 장착하여야 하는 작업상의 어려움이 있었다.However, in the conventional semiconductor package as described above, during the forming process of forming the external lead of the semiconductor package, the external lead is often bent and treated as a defect, and is applied externally even after the semiconductor package is mounted on the printed circuit board. The external lead is bent by force, so that it is not firmly attached. In particular, in order to mount the surface-mount semiconductor package on the printed circuit board, the semiconductor package is placed on the printed circuit board with both the soldering device and the soldering material held by both hands. There was a difficulty in the work to be fitted.
또한 다수의 반도체 패키지를 하나의 용기에 모아 두게 되면 반도체 패키지의 외부 리드가 서로 엉켜서 취급하기가 불편한 난점이 있었다.In addition, when a plurality of semiconductor packages are collected in one container, external leads of the semiconductor packages are entangled with each other, making it difficult to handle.
상기한 외부리드의 휨을 방지하기 위해 외부리드에 튜브나 트레이(Tray)를 사용하여 작업을 보조하기도 하지만 이것 역시 튜브나 트레이를 사용해야 하는 불편함이 있고 휨을 방지하는 것을 제외하고는 종래 기술의 다른 문제점들은 여전히 가지고 있었다.In order to prevent the warpage of the outer lead, the use of a tube or a tray on the outer lead may assist the work, but this also has the inconvenience of using a tube or a tray, and other problems of the prior art except for preventing the warp. They still had.
본 고안은 상술한 바와 같은 종래 기술의 문제점을 해소하기 위해 안출한 것으로서 반도체 패키지 외부리드의 휨을 방지하고, 인쇄회로기판상에 견고하게 장착되며, 취급하기에 용이한 압정형 반도체 패키지를 제공함을 목적으로 하는 것이다.The present invention has been made to solve the problems of the prior art as described above, to prevent the bending of the semiconductor package external lead, to provide a tack-type semiconductor package that is firmly mounted on the printed circuit board, easy to handle. It is to be done.
상기한 본 고안의 목적은 반도체 패키지의 내부리드의 길이방향 중앙부를 절곡하여 반도체 패키지의 저면에서 돌출됨과 아울러 그 절곡부인 돌출단부가 첨예한 압정형 외부리드를 형성한 것을 특징으로 하는 압정형 반도체 패키지를 제공하는 것에 의해 달성된다.An object of the present invention described above is a tack-type semiconductor package, characterized in that the center portion of the inner lead of the semiconductor package is bent to protrude from the bottom surface of the semiconductor package, and a tack-type outer lead having a sharp protruding end thereof is formed. By providing it.
이러한 본 고안을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.This invention is described in detail with reference to the accompanying drawings as follows.
제3도에 도시된 본 고안의 반도체 패키지(1)를 살펴보면, 먼저 칩(4)이 서로 대향하는 리드(3)위에 올려져 반도체 패키지(1)의 내부 중앙에 배치되고, 칩(4)의 내부 회로와 리드(3)를 전기적으로 연결하는 와이어(2)가 내부에 설치되고, 상기 리드(3)의 길이방향 중간부를 V자형으로 절곡하여 반도체 패키지(1)의 저면에서 돌출됨과 아울러 그 절곡부인 돌출단부가 첨예한 압정형 외부리드(3b)를 형성하여서 구성된다.Referring to the semiconductor package 1 of the present invention shown in FIG. 3, first, the chip 4 is placed on the lead 3 facing each other and disposed at the inner center of the semiconductor package 1. A wire 2 for electrically connecting the internal circuit and the lead 3 is installed therein, and the longitudinal middle portion of the lead 3 is bent in a V-shape to protrude from the bottom surface of the semiconductor package 1 and to be bent. The female protruding end portion is formed by forming a sharp tack type outer lead 3b.
또한 상기한 칩(4), 와이어(2) 및 리드(3)는 컴파운드(5)로 몰딩되어 있다.In addition, the chip 4, the wire 2, and the lead 3 are molded with the compound 5.
이러한 반도체 패키지(1)를 기판(6)상에 실장한 상태가 제4a도 및 제4b도에 도시되어 있다.The state in which the semiconductor package 1 is mounted on the substrate 6 is shown in FIGS. 4A and 4B.
제4a도는 표면실장형 실장예로서, 압정 형태로 된 외부리드(3b)를 인쇄회로 기판(6)상의 접합 부위에 대고 눌러 가고정한 후 납땜장치로 납땜하여 인쇄회로기판(6)상에 실장하게 된다.4A shows an example of surface mount type mounting. The external lead 3b in the form of a tack is pressed against the junction portion on the printed circuit board 6 to be temporarily fixed, and then soldered with a soldering device to be mounted on the printed circuit board 6. do.
제4b도는 핀삽입형 실장예로서, 미리 준비된 핀삽입홀(6')에 반도체 패키지의 압정형 외부리드(3b)의 첨예형 돌출단부를 삽입하여 가고정한 후 납땜을 하여 고정시켜 인쇄회로기판(6)에 장착하게 된다.FIG. 4B is a pin insertion type example, in which a sharp protrusion end of a tack type external lead 3b of a semiconductor package is inserted into a pin insertion hole 6 'prepared in advance, temporarily fixed, and soldered to fix the printed circuit board 6 )).
도면중 미설명 부호 7은 납땜접합부위를 나타낸다.In the figure, reference numeral 7 denotes a solder joint.
상기한 바와 같은 본 고안은 몰딩공정 후 외부리드를 성형하는 포밍공정을 필요로 하지 않으므로 외부리드의 잘못된 휨으로 인한 반도체 패키지의 불량을 방지할 수 있으며, 공수가 줄게 되어 작업이 간단하게 되고, 표면실장형 또는 핀삽입실장형의 양자 구별없이 반도체 패키지를 사용할 수 있으며, 외부리드가 외부로 길게 연장되어 있지 않으므로 서로 엉키지 않아 취급이 편리하고, 인쇄회로기판상에 장착된 후에도 견고하게 장착 상태를 유지할 수 있는 효과가 있다.The present invention as described above does not require a forming process for molding the outer lead after the molding process, it is possible to prevent the defect of the semiconductor package due to the wrong bending of the outer lead, the labor is reduced, the operation is simplified, the surface The semiconductor package can be used regardless of whether it is mounted or pin-insert type, and since the external lead does not extend to the outside, it is easy to handle because it does not get tangled with each other and remains firmly mounted even after being mounted on the printed circuit board. It can be effective.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940021974U KR200177247Y1 (en) | 1994-08-29 | 1994-08-29 | Tack type semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940021974U KR200177247Y1 (en) | 1994-08-29 | 1994-08-29 | Tack type semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960009278U KR960009278U (en) | 1996-03-16 |
| KR200177247Y1 true KR200177247Y1 (en) | 2000-04-15 |
Family
ID=19391821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019940021974U KR200177247Y1 (en) | 1994-08-29 | 1994-08-29 | Tack type semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200177247Y1 (en) |
-
1994
- 1994-08-29 KR KR2019940021974U patent/KR200177247Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960009278U (en) | 1996-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02239651A (en) | Semiconductor device and mounting method thereof | |
| JPS59161851A (en) | Electronic component parts | |
| US5398165A (en) | Electronic circuit component and mounting method therefor | |
| KR950002193B1 (en) | Semiconductor device parts | |
| KR200177247Y1 (en) | Tack type semiconductor package | |
| KR970009495A (en) | Surface-mounted electronic parts and manufacturing method thereof | |
| JPH01235360A (en) | Semiconductor integrated circuit device | |
| JPS62118555A (en) | Integrated circuit package | |
| JPS6175553A (en) | Electronic part | |
| JP3546926B2 (en) | Manufacturing method of electronic components and seat plate for the same | |
| JPH0145235B2 (en) | ||
| KR910000018B1 (en) | Semiconductor device using the lead-frame and method of manufacture there of | |
| JPS59110146A (en) | Outer lead terminal of package type module | |
| KR860001060Y1 (en) | Connector | |
| JPH0412665Y2 (en) | ||
| KR0125856Y1 (en) | Structure of outer lead support of package | |
| KR100201397B1 (en) | Package for inserting semiconductor package | |
| JPH10256421A (en) | Semiconductor device and mounting method thereof | |
| KR0119088Y1 (en) | Semiconductor package | |
| JPH01161707A (en) | Chip component | |
| KR0181796B1 (en) | Power module package apparatus | |
| JPS6334285Y2 (en) | ||
| KR200244925Y1 (en) | Body-mount package and its mounting structure | |
| JPS5910755Y2 (en) | semiconductor rectifier | |
| JPH0432740Y2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20080102 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |