JPS61207069A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61207069A JPS61207069A JP4880285A JP4880285A JPS61207069A JP S61207069 A JPS61207069 A JP S61207069A JP 4880285 A JP4880285 A JP 4880285A JP 4880285 A JP4880285 A JP 4880285A JP S61207069 A JPS61207069 A JP S61207069A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- polysilicon layer
- electrodes
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 3
- 238000000605 extraction Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
、〔産業上の利用分野〕
本発明は半導体装置に関し、特に段付電極トランジｘ
タ（Ｓ ｔｅｐｐｅｄ Ｅｌｅｃｔｒｏｄｅ Ｔｒａｎ
ｓｉｓｔｅｒ ：以後ＳＥＴと称す）といわれる半導体
装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a stepped electrode transistor x
Stepped Electrode Tran
The present invention relates to the structure of a semiconductor device called sister (hereinafter referred to as SET).
ＳＥＴは、周知のとおり、逆台形状の不純物含有ポリシ
リコン層を半導体上に形成し、これを拡散源としてエミ
ッタ領域を形成すると共に、これの形状を利用してエミ
ッタ電極とベース電極とを上下の方向で分離するもので
ある。この構造によれば、外部ペース領域が極力小さく
なり、高周波動作が行なわれるが、トランジスタとして
実用する場合、外部ケースとの引き出し用電極を必要と
する。引出電極の形成として、従来は第２図又は第３図
に示すような構造をとっていた。As is well known, in SET, an inverted trapezoidal impurity-containing polysilicon layer is formed on a semiconductor, this is used as a diffusion source to form an emitter region, and the shape of this layer is used to connect an emitter electrode and a base electrode vertically. It separates in the direction of . According to this structure, the external space area is made as small as possible and high frequency operation is performed, but when it is put to practical use as a transistor, an electrode for leading out from the external case is required. Conventionally, the extraction electrode was formed using a structure as shown in FIG. 2 or 3.
第２図において、シリコン基板上のシリコン酸化膜２に
設けられた開口により区画された部分にベース領域３が
形成され、逆台形加工されたポリシリコン層４はペース
領域３の一部と接触して酸化膜２上に長く伸ばして形成
され、ポリシリコン層４からの不純物拡散によりエミッ
タ領域９が形成されている。金属の垂直方向蒸着により
上下方向に分離されたエミッタ電極５およびベース電極
６が形成される。エミッタ電極５はポリシリコン層４の
上部のみに形成され、一方、ベース電極６はポリシリコ
ン層４の周囲を取り囲み、かつポリシリコン層４と反対
側の酸化膜２上にペース引出し電極を構成している。な
お、１０および１１はポリシリコン層４の側面保護のた
めの酸化膜および窒化膜である。In FIG. 2, a base region 3 is formed in a portion defined by an opening provided in a silicon oxide film 2 on a silicon substrate, and a polysilicon layer 4 processed into an inverted trapezoid is in contact with a part of a pace region 3. The polysilicon layer 4 is formed in a long manner on the oxide film 2, and an emitter region 9 is formed by impurity diffusion from the polysilicon layer 4. An emitter electrode 5 and a base electrode 6 separated in the vertical direction are formed by vertically evaporating metal. The emitter electrode 5 is formed only on the top of the polysilicon layer 4, while the base electrode 6 surrounds the periphery of the polysilicon layer 4 and constitutes a paste extraction electrode on the oxide film 2 on the opposite side from the polysilicon layer 4. ing. Note that 10 and 11 are an oxide film and a nitride film for protecting the side surfaces of the polysilicon layer 4.
このような構造では、ベース電極６とエミッタ電極４と
は、逆台形状のポリシリコン４によって分離されている
ため、構造上の問題がない。しかし、この構造では、ベ
ース電極６が大きくなるためベース・コレクタ間容量が
大きくなり、高周波特性が劣化する。またエミッタ電極
４上に外部ケースから接続するとき、ボンディングの位
置が少しずれると、ＥＢ間が短絡してしまうので、ボン
ディング部を大きくする必要があり、エミッターコレク
タ間容電も大きくなって、高周波特性が劣化するという
問題があった。In such a structure, since the base electrode 6 and the emitter electrode 4 are separated by the inverted trapezoidal polysilicon 4, there is no structural problem. However, in this structure, since the base electrode 6 becomes large, the base-collector capacitance becomes large, and the high frequency characteristics deteriorate. Furthermore, when connecting the emitter electrode 4 from the external case, if the bonding position is slightly shifted, a short circuit will occur between EB, so the bonding part needs to be made larger, and the emitter-collector capacitance also increases, resulting in high frequency There was a problem that the characteristics deteriorated.
これに対し、第３図に示すような構造が考案された。こ
の構造の特徴は、ポリシリコン層４を小さくすると共に
酸化膜２上のポリシリコン端部は逆台形ではなくてほぼ
垂直にし、この構造とホトレジストのパターニングとで
一度の金属蒸着工程によりエミッタ電極５をポリシリコ
ン層４からは化膜２上にまで延ばしたことである。これ
によりベース−コレクタ間、エミッターコレクタ間の容
量は小さくなり、高部波特性が改善された。しかし、新
らたな問題が発生した。即ち、第２図の場合、エミッタ
およびベース電極５，６は、逆台形ポリシリコン層４に
より分離していたのが、第３図の場合、エミッタおよび
ベース電極５，６を分離するために、７，８の部分に示
すように逆台形状ポリシリコン層４の角部を露出するよ
うホトレジストをパターニングする必要がある。逆台形
状ポリシリコン層４の形状のためフォトレジスト形状が
不安定であり、この結果、確実に電極を分離することが
困難となシ、パターニングのずれＫよってエミッターベ
ース間短絡不良が急増した。In response, a structure as shown in FIG. 3 was devised. The feature of this structure is that the polysilicon layer 4 is made small, the polysilicon edge on the oxide film 2 is made almost vertical instead of an inverted trapezoid, and the emitter electrode 5 is formed by a single metal vapor deposition process that combines this structure and photoresist patterning. is extended from the polysilicon layer 4 to the top of the chemical film 2. This reduces the base-collector capacitance and emitter-collector capacitance, improving high frequency characteristics. However, a new problem arose. That is, in the case of FIG. 2, the emitter and base electrodes 5 and 6 were separated by the inverted trapezoidal polysilicon layer 4, but in the case of FIG. 3, in order to separate the emitter and base electrodes 5 and 6, It is necessary to pattern the photoresist so as to expose the corners of the inverted trapezoidal polysilicon layer 4, as shown in sections 7 and 8. Due to the shape of the inverted trapezoidal polysilicon layer 4, the photoresist shape is unstable, and as a result, it is difficult to reliably separate the electrodes, and the number of emitter-base short circuit defects increases rapidly due to patterning deviation K.
上述したように、従来のＳＥＴでは、高周波特性の劣化
やエミッターベース間短絡不良による歩留低下という問
題があり、ＳＥＴという特殊構造トランジスタの能力を
充分出すことができなかった。As described above, conventional SETs have problems such as deterioration of high frequency characteristics and decreased yield due to poor emitter-base short circuits, and have not been able to fully utilize the capabilities of the special structure transistor called SET.
本発明の目的は、エミッターベース間及びベース−コレ
クタ間容量を小さくシ、かつエミッターベース電極間短
絡を防止した構造を提供することにあり、その特徴とす
るところは、逆台形状ポリシリコン層により分離した電
極上に絶縁膜を形成し、この膜のエミッタおよびベース
各電極上の部分に開口部を形成し、この開口部を介して
ベース。An object of the present invention is to provide a structure that reduces emitter-base and base-collector capacitances and prevents short circuits between emitter-base electrodes, and is characterized by an inverted trapezoidal polysilicon layer. An insulating film is formed on the separated electrodes, an opening is formed in this film on the emitter and base parts of each electrode, and the base is passed through this opening.
エミッタ電極と接触しかつ絶縁膜上に延在するエミッタ
、ベース引出電極を形成したことにある。The present invention is based on forming emitter and base lead electrodes that are in contact with the emitter electrode and extend over the insulating film.
次に本発明の一実施例を図面を参照して説明する。 Next, one embodiment of the present invention will be described with reference to the drawings.
第１図に本発明の一実施例を示す。このＳＥＴの特徴は
、２層電極構造を用いていることである。FIG. 1 shows an embodiment of the present invention. A feature of this SET is that it uses a two-layer electrode structure.
すなわち、従来のように逆台形ポリシリコン層４を形成
してエミッタ領域９を形成する。このとき、酸化膜２上
に延在するポリシリコン層４はコンタクトホールが形成
できる程度に小さくする。パターニングされたホトレジ
ストを形成して金属を垂直方向から蒸着する。ホトレジ
ストのパターニングは、ベース領域３形成のための酸化
膜２の開口端部およびポリシリコン層４の端部に沿って
行なっている。この結果、ポリシリコン層４によって確
実に分離されたベース、エミッタ電極６，５が形成され
る。次に、全面にシリコン酸化膜、シリコン窒化膜等の
絶縁物１２を形成し、この絶縁物１２のエミッタ電極５
上及びベース電極６上に位置する部分にコンタクトホー
ルを形成し、このコンタクトホールを介して接続用引出
し電極１３．１４を形成する。この結果、引出電極１３
．１４下には二つの絶縁層２．１２があるので、容量が
小さくなり、さらに、ベース、エミッタ電極６，５の短
絡が防止ちれる。That is, an inverted trapezoidal polysilicon layer 4 is formed to form an emitter region 9 as in the conventional method. At this time, the polysilicon layer 4 extending on the oxide film 2 is made small enough to form a contact hole. A patterned photoresist is formed and metal is vertically deposited. The photoresist is patterned along the opening edges of the oxide film 2 for forming the base region 3 and along the edges of the polysilicon layer 4. As a result, base and emitter electrodes 6 and 5 that are reliably separated by polysilicon layer 4 are formed. Next, an insulator 12 such as a silicon oxide film or a silicon nitride film is formed on the entire surface, and an emitter electrode 5 of this insulator 12 is formed.
A contact hole is formed in a portion located above the upper and base electrodes 6, and connection extraction electrodes 13 and 14 are formed through this contact hole. As a result, the extraction electrode 13
．． Since there are two insulating layers 2 and 12 below 14, the capacitance is reduced, and short circuits between the base and emitter electrodes 6 and 5 are prevented.
以上説明したように、本発明は逆台形ポリシリコン層（
即ちエミッタ電極）及びペース電極を小さくしてエミッ
ターコレクタ間及びペース−コレクタ間容量を小さくし
、一方、引き出し用電極は厚い絶縁膜を介して得るため
に、従来より良好な高周波特性を得ることができた。ま
た、エミッターペース間の電極は、逆台形ポリシリコン
層によって分離するため、エミッターペース間短絡不良
は皆無となった。As explained above, the present invention provides an inverted trapezoidal polysilicon layer (
That is, the emitter electrode) and the pace electrode are made smaller to reduce the emitter-collector and pace-collector capacitance, while the extraction electrode is obtained through a thick insulating film, making it possible to obtain better high frequency characteristics than before. did it. Furthermore, since the electrodes between the emitter pastes are separated by an inverted trapezoidal polysilicon layer, there were no short circuits between the emitter pastes.
このように、本発明によるＳＥＴは、歩留、Ｐ／Ｗが良
く、かつ高周波特性の優れたものであり、ＳＥＴ本来の
性能を充分に出すことができるものである。As described above, the SET according to the present invention has good yield and P/W, and excellent high frequency characteristics, and can fully exhibit the original performance of the SET.
第１図（５）および（Ｂ）は夫々本発明の一実施例を示
す平面図およびａ−ａ線に沿った縦断面図、第２図（５
）、（Ｂ）は夫々従来例を示す平面図、ｂ−ｂ線に沿っ
た縦断面図、第３図（５）、（Ｂ）は夫々他の従来例を
示す平面図、Ｃ−Ｃ線に沿った断面図である。
１・・・・・・シリコン基板、２・・・・・・シリコン
酸化膜、３・・・・・・ペース領域、４・・・・・・不
純物を含む逆台形加工されたポリシリコン層、５・・・
・・・エミッタ電極、６・・・・・・ペース電極、７・
・・・・・エミッタ、ベース間電極の分離箇所、８・・
・・・・エミッタ、ベース間電極の分離箇所、９−・・
・・・エミッタ領域、ｌＯ・・・・・・シリコン酸化膜
、１１・・・・・・シリコン窒化膜、１２・・・・・・
絶縁膜、１３・・・・・・ペース引出電極、１４・・・
・・・エミッタ引出電極。
茶 ／Ｉ！Ｉ
第 ２ 図FIGS. 1(5) and 1(B) are a plan view and a vertical cross-sectional view taken along the a-a line showing an embodiment of the present invention, respectively, and FIG.
) and (B) are respectively a plan view showing a conventional example and a vertical cross-sectional view taken along the line bb. FIG. FIG. 1...Silicon substrate, 2...Silicon oxide film, 3...Pase region, 4...Polysilicon layer processed into an inverted trapezoid containing impurities, 5...
...Emitter electrode, 6...Pace electrode, 7.
... Separation point of electrode between emitter and base, 8...
... Separation point of electrode between emitter and base, 9-...
...Emitter region, lO...Silicon oxide film, 11...Silicon nitride film, 12...
Insulating film, 13... Pace extraction electrode, 14...
...Emitter extraction electrode. Tea /I! I Figure 2
Claims (1)
ポリシリコンが形成され、該ポリシリコン層上及びその
周囲にそれぞれ形成されかつ互いに電気的に分離された
第１および第２の金属層が形成され、これら金属層を覆
う絶縁膜が形成され、この絶縁膜に設けられた第１およ
び第２の開口を介して前記第１および第２の金属層とそ
れぞれ接触し前記絶縁膜に延在する第３および第４の引
出金属層が形成されていることを特徴とする半導体装置
。Polysilicon processed into an inverted trapezoidal shape and containing impurities is formed on a semiconductor substrate, and first and second metal layers are formed on and around the polysilicon layer and are electrically isolated from each other. an insulating film covering these metal layers is formed, and the insulating film contacts the first and second metal layers through first and second openings provided in the insulating film, respectively, and extends to the insulating film. A semiconductor device characterized in that third and fourth lead metal layers are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4880285A JPS61207069A (en) | 1985-03-12 | 1985-03-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4880285A JPS61207069A (en) | 1985-03-12 | 1985-03-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207069A true JPS61207069A (en) | 1986-09-13 |
Family
ID=12813343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4880285A Pending JPS61207069A (en) | 1985-03-12 | 1985-03-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61207069A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63249792A (en) * | 1987-01-19 | 1988-10-17 | エー．アールストロム コーポレーション | Method and apparatus for separating undigested substance |
| JPH01205466A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Semiconductor device and its manufacture |
-
1985
- 1985-03-12 JP JP4880285A patent/JPS61207069A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63249792A (en) * | 1987-01-19 | 1988-10-17 | エー．アールストロム コーポレーション | Method and apparatus for separating undigested substance |
| JPH01205466A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Semiconductor device and its manufacture |
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