JPH02119229A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH02119229A
JPH02119229A JP27345688A JP27345688A JPH02119229A JP H02119229 A JPH02119229 A JP H02119229A JP 27345688 A JP27345688 A JP 27345688A JP 27345688 A JP27345688 A JP 27345688A JP H02119229 A JPH02119229 A JP H02119229A
Authority
JP
Japan
Prior art keywords
emitter
collector
polycrystalline silicon
region
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27345688A
Other languages
Japanese (ja)
Inventor
Takehiro Hirai
健裕 平井
Mitsuo Tanaka
光男 田中
Yoshiro Fujita
藤田 良郎
Akihiro Kanda
神田 彰弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP27345688A priority Critical patent/JPH02119229A/en
Publication of JPH02119229A publication Critical patent/JPH02119229A/en
Pending legal-status Critical Current

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  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance a high-frequency characteristic of a lateral-type transistor and to realize a high density by a method wherein an emitter diffusion layer and a collector diffusion layer are formed by diffusing an impurity from polycrystalline silicon in order to prevent the impurity from being dispersed largely into a substrate and to prevent a base width from becoming wider than a maximum pattern of a mask. CONSTITUTION:An emitter region, a base region and a collector region E, B, C which have been arranged in a transverse direction on one main face of a semiconductor substrate 3 of a second conductivity type have respective recessed parts whose cross-sectional shape is nearly rectangular; polycrystalline silicon 6-1, 6-3, 6-2 as electrodes is filled into the recessed parts; the emitter region and the collector region E, C have individually an emitter diffusion layer and a collector diffusion layer 5-1, 5-2 formed by diffusing an impurity of a first conductivity type into the semiconductor substrate 3 from the polycrystalline silicon 6-1, 6-2 inside the respective recessed parts; junction faces of the diffusion layers 5-1, 5-2 opposite to each other are nearly parallel to each other; the base region B has a base contact layer 8 formed by diffusing an impurity of a second conductivity type into the semiconductor substrate 3 from the polycrystalline silicon 6-3 inside the recessed part.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ラテラル型トランジスタ装置及びそれらを多
数同一半導体基板上に集積した集積回路装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a lateral transistor device and an integrated circuit device in which a large number of these devices are integrated on the same semiconductor substrate.

従来の技術 従来のラテラル型トランジスタは、第2図に示すように
、第2導電型の埋め込み領域2が形成された第1導電型
半導体基板1の一生面上に、第2導電型半導体層3を成
長し、この半導体層3の表面に絶縁膜4を形成し、ラテ
ラル型トランジスタのエミッタ、ベース、コレクタとな
るための凹部を絶縁膜4をマスクとしたシリコンのエツ
チングによって形成した後、エミッタ、コレクタとなる
べき領域には第1導電型の不純物を、ベースとなるべき
領域には第2導電型の不純物を拡散して、エミッタ拡散
層5−1、コレクタ拡散層5−2、ベースコンタクト層
8を形成する。そして、拡散領域を覆うようにAL電極
7−1.7−2.7−3を形成する。
2. Description of the Related Art As shown in FIG. 2, a conventional lateral transistor includes a second conductivity type semiconductor layer 3 on the entire surface of a first conductivity type semiconductor substrate 1 in which a second conductivity type buried region 2 is formed. An insulating film 4 is formed on the surface of the semiconductor layer 3, and recesses to become the emitter, base, and collector of the lateral transistor are formed by silicon etching using the insulating film 4 as a mask. An impurity of the first conductivity type is diffused into the region to become the collector, and an impurity of the second conductivity type is diffused to the region to become the base. form 8. Then, an AL electrode 7-1.7-2.7-3 is formed to cover the diffusion region.

発明が解決しようとする課題 従来の構造では、半導体基板へ直接高濃度の不純物を拡
散することになるので、どうしても不純物が半導体基板
中に大きく広がることになって高密度化を妨げるだけで
なく、接合容量の増加をもたらし高周波特性もよ(なか
った。さらに、電極?−1,7−2が、凹部を覆う形に
なっているので、マスクの最小パターン寸法a(第2図
参照)よりも常にベース幅が広くできてしまうことも高
密度化、高周波特性の向上という点で問題になっていた
Problems to be Solved by the Invention In the conventional structure, a high concentration of impurities is diffused directly into the semiconductor substrate, which inevitably causes the impurities to spread widely throughout the semiconductor substrate, which not only hinders high density. This increases the junction capacitance and improves the high frequency characteristics.Furthermore, since the electrodes ?-1 and 7-2 cover the recesses, they are smaller than the minimum pattern dimension a of the mask (see Figure 2). The fact that the base width is always wide has also been a problem in terms of increasing density and improving high frequency characteristics.

本発明は、上述の問題点に鑑みて試されたもので、不純
物が半導体基板中へ大きく広がることなく、また、マス
クの最小パターンよりもベース幅が広くなることなくラ
テラル型トランジスタの高周波特性の向上、高密度化と
いったものが実現でき得る半導体装置とその製造方法を
提供することを目的とする。
The present invention was attempted in view of the above-mentioned problems, and improves the high frequency characteristics of lateral transistors without causing impurities to spread significantly into the semiconductor substrate and without making the base width wider than the minimum pattern of the mask. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can realize improved performance and higher density.

課題を解決するための手段 本発明は上述の課題を解決するため、第2導電型半導体
基板の一生面上に、エミッタ、コレクタ、ベース領域そ
れぞれが、横方向に配置された半導体装置において、前
記エミッタ、ベース、コレクタ領域がそれぞれ、その断
面形状がほぼ長方形であるような凹部を持ち、前記凹部
内に多結晶シリコンが、電極として埋め込まれ、肩記エ
ミッタ、前記コレクタ領域の少なくとも一方の領域の前
記凹部内の多結晶シリコンが、少な(とも前記エミッタ
と前記コレクタ領域の前記回部に挟まれた半導体基板表
面領域上に延在していない構造で、前記エミッタと前記
コレクタ領域において、それぞれの凹部内の多結晶シリ
コンから第1導電型の不純物が前記半導体基板内に拡散
されて形成されたエミッタ、コレクタ拡散層を存し、前
記エミッタと前記コレクタ領域が対向している部分にお
いて、前記エミッタと前記コレクタの拡散層の接合面が
互いにほぼ平行であり、前記ベース領域において、凹部
内の多結晶シリコンから第2導電型の不純物が前記半導
体基板内に拡散されて形成されたベースコンタクト層を
有しているような構造を有する半導体装置である。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a semiconductor device in which an emitter, a collector, and a base region are each disposed laterally on the whole surface of a second conductivity type semiconductor substrate. The emitter, base, and collector regions each have a recess whose cross-sectional shape is approximately rectangular, and polycrystalline silicon is embedded as an electrode in the recess. A structure in which the polycrystalline silicon in the recessed portion does not extend over a surface region of the semiconductor substrate sandwiched between the circuit portions of the emitter and collector regions, and An emitter and collector diffusion layer is formed by diffusing a first conductivity type impurity from polycrystalline silicon in the recess into the semiconductor substrate, and in a portion where the emitter and the collector region face each other, the emitter and the collector diffusion layer are substantially parallel to each other, and in the base region, a base contact layer is formed by diffusing a second conductivity type impurity from the polycrystalline silicon in the recess into the semiconductor substrate. This is a semiconductor device having a structure similar to that shown in FIG.

作用 本発明は前記したように、エミッタ及びコレクタ拡散層
が多結晶シリコンからの不純物の拡散によって形成され
るので、高濃度に不純物を拡散しても半導体基板中に太
き(広がることなく、エミッタ拡散層、コレクタ拡散層
、ベースコンタクト層を形成することができる。さらに
、前述のような方法で多結晶シリコンを電極として凹部
内に埋め込む構造のため、マスク最小寸法でベース幅を
形成することができる。
Operation As described above, in the present invention, the emitter and collector diffusion layers are formed by diffusing impurities from polycrystalline silicon, so even if the impurities are diffused in a high concentration, the emitter and collector diffusion layers are formed thickly (without spreading) in the semiconductor substrate. A diffusion layer, a collector diffusion layer, and a base contact layer can be formed.Furthermore, since the structure is such that polycrystalline silicon is buried in the recess as an electrode using the method described above, the base width can be formed using the minimum dimension of the mask. can.

実施例 本発明の構造とその製造方法についての一実施例を第1
図A−Dに沿って述べる。
Example A first example of the structure and manufacturing method of the present invention is described below.
This will be described along Figures A to D.

[A]第1導電型半導体基板1に高濃度の第2導電型半
導体領域2を設け、第2導電型半導体層3を成長し、さ
らに絶縁膜4をその上に形成する。
[A] A highly concentrated second conductive type semiconductor region 2 is provided on a first conductive type semiconductor substrate 1, a second conductive type semiconductor layer 3 is grown, and an insulating film 4 is further formed thereon.

[Bコ絶縁膜4上に、エミッタ、ベース、コレクタそれ
ぞれのパターンを形成した後、絶縁M4をそのパターン
通りにエツチングし、その後前記第2導電型半導体層3
をエツチングして、エミッタ、コレクタ、ベース領域の
四部を形成する。そして、多結晶シリコンを堆積し、エ
ッチバック法、ポリッシングなどを用いて多結晶シリコ
ンを前記凹部中に埋め込んで多結晶シリコンのエミッタ
電極6−1、同コレクタ電極6−2、同ベース電極6−
3を形成する。
[After forming emitter, base, and collector patterns on the Bco insulating film 4, the insulating layer M4 is etched according to the pattern, and then the second conductive type semiconductor layer 3 is etched.
to form the emitter, collector, and base regions. Then, polycrystalline silicon is deposited, and the polycrystalline silicon is buried in the recessed portions using an etch-back method, polishing, etc., and the polycrystalline silicon emitter electrode 6-1, the collector electrode 6-2, and the base electrode 6- are made of polycrystalline silicon.
form 3.

[Cコレクタ多結晶シリコン6−3内に第1導電型の不
純物が導入されないようにその表面をマスクで覆い、エ
ミッタ多結晶シリコン6−1、コレクタ多結晶シリコン
6−2に第1導電型の不純物をイオン注入、固相拡散な
どによって導入し、その多結晶シリコンより第1導電型
の不純物を前記半導体層3内に拡散し、エミッタ拡散層
5−1、コレクタ拡散層5−2を形成する。次に、エミ
ッタ及びコレクタ多結晶シリコン6−1.8−2内に第
2導電型の不純物が導入されないようにその表面をマス
クで覆い、ベース多結晶シリコン6−3に第2導電型の
不純物をイオン注入、固相拡散などによって導入し、そ
の多結晶シリコンより第2導電型の不純物を前記半導体
層3内に拡散し、ベースコンタクト層8を形成する。
[The surface of the C collector polycrystalline silicon 6-3 is covered with a mask so that impurities of the first conductivity type are not introduced into the emitter polycrystalline silicon 6-1 and collector polycrystalline silicon 6-2. Impurities are introduced by ion implantation, solid phase diffusion, etc., and the impurities of the first conductivity type are diffused into the semiconductor layer 3 from the polycrystalline silicon to form an emitter diffusion layer 5-1 and a collector diffusion layer 5-2. . Next, the surfaces of the emitter and collector polycrystalline silicon 6-1, 8-2 are covered with a mask so that impurities of the second conductivity type are not introduced into the base polycrystalline silicon 6-3, and the second conductivity type impurities are introduced into the base polycrystalline silicon 6-3. is introduced by ion implantation, solid-phase diffusion, etc., and impurities of the second conductivity type are diffused into the semiconductor layer 3 from the polycrystalline silicon to form the base contact layer 8.

[D]エミッタ、コレクタ、ベース多結晶シリコン6−
1.6−2.6−3表面に絶縁膜を形成した後、図のよ
うに互い違いにコンタクトを開口し、金属電極をそれぞ
れエミッタ、コレクタ、ベース上に形成する。(7−L
  7−2.7−3)なお、本実施例では、 [Cコに
おいて、エミッタ拡散層5−1、コレクタ拡散層5−2
、ベースコンタクト層8を形成する際、エミッタ、コレ
クタ拡散層をさきに形成した後ベースコンタクト層を形
成したが、どちらを先に形成してもかまわない。また、
 CB]、  [C]において、多結晶シリコン電極6
−1.8−2.6−3を第2導電型半導体層3の凹部に
埋め込んでから、その多結晶シリコン中に第1及び第2
導電型の不純物を導入してエミッタ拡散層5−1、コレ
クタ拡散層5−2、ベースコンタクト層8を形成したが
、第1導電型の不純物が導入された多結晶シリコンをエ
ミッタ、コレクタ領域に埋め込み、第2導電型の不純物
が導入された多結晶シリコンをベース領域に埋め込んで
、エミッタ拡散層5−1、コレクタ拡散層5−2、ベー
スコンタクト層8を形成してもよい。
[D] Emitter, collector, base polycrystalline silicon 6-
1.6-2.6-3 After forming an insulating film on the surface, contacts are opened alternately as shown in the figure, and metal electrodes are formed on the emitter, collector, and base, respectively. (7-L
7-2.7-3) In this example, [in C, emitter diffusion layer 5-1, collector diffusion layer 5-2
When forming the base contact layer 8, the emitter and collector diffusion layers were formed first and then the base contact layer was formed, but it does not matter which one is formed first. Also,
CB], [C], polycrystalline silicon electrode 6
-1.8-2.6-3 is buried in the recess of the second conductivity type semiconductor layer 3, and then the first and second semiconductor layers are buried in the polycrystalline silicon.
Although the emitter diffusion layer 5-1, the collector diffusion layer 5-2, and the base contact layer 8 were formed by introducing conductivity type impurities, the polycrystalline silicon into which the first conductivity type impurities were introduced was used in the emitter and collector regions. Emitter diffusion layer 5-1, collector diffusion layer 5-2, and base contact layer 8 may be formed by embedding polycrystalline silicon into which second conductivity type impurities have been introduced into the base region.

さらに、 [Dコにおいて、金属電極を形成する際に、
電極を図のように互い違いに配置したが、 〔Cコ図b
(エミッタ凹部とコレクタ凹部間距離)が、マスクの最
小寸法にできるような電極配置にすればよい。さらに、
bをマスクの最小寸法にできるように、金属電極を形成
する前に、多結晶シリコン電極6−1、または6−2、
または6−3上に、新たに多結晶シリコン電極を形成し
、引出し電極としてから、その引出し電極上に金属電極
を形成してもよい。また、多結晶シリコン電極6−1.
6−2.6−3の少なくとも一つの電極において、その
底面、あるいは一つ以上の側面を絶縁物で覆ってもよい
Furthermore, [in Dco, when forming the metal electrode,
Although the electrodes were arranged alternately as shown in the figure,
The electrode arrangement may be such that (distance between the emitter recess and the collector recess) can be made the minimum dimension of the mask. moreover,
Before forming the metal electrode, a polycrystalline silicon electrode 6-1 or 6-2 is formed so that b can be the minimum dimension of the mask.
Alternatively, a new polycrystalline silicon electrode may be formed on 6-3 to serve as an extraction electrode, and then a metal electrode may be formed on the extraction electrode. Moreover, polycrystalline silicon electrode 6-1.
In at least one electrode of 6-2.6-3, the bottom surface or one or more side surfaces may be covered with an insulator.

発明の効果 以上の説明から明らかなように、本発明は、第2導電型
半導体基板の一生面上に、エミッタ、コレクタ、ベース
領域それぞれが、横方向に配置された半導体装置におい
て、前記エミッタ、ベース、コレクタ領域がそれぞれ、
その断面形状がほぼ長方形であるような凹部を持ち、前
記凹部内に多結晶シリコンが、電極として埋め込まれ、
前記エミッタ、前記コレクタ領域の少なくとも一方の領
域の前記凹部内の多結晶シリコンが、少なくとも前記エ
ミッタと前記コレクタ領域の前記凹部に挟まれた半導体
基板表面領域上に延在していない構造で、前記エミッタ
と前記コレクタ領域において、それぞれの凹部内の多結
晶シリコンから第1導電型の不純物が前記半導体基板内
に拡散されて形成されたエミッタ、コレクタ拡散層を有
し、前記エミッタと前記コレクタ領域が対向している部
分において、前記エミッタと前記コレクタの拡散層の接
合面が互いにほぼ平行であり、前記ベース領域において
、凹部内の多結晶シリコンから第2導電型の不純物が前
記半導体基板内に拡散されて形成されたベースコンタク
ト層を有しているという構造を取っているので、多結晶
シリコンから半導体基板中へ不純物が拡散されることと
なり、高濃度に不純物を拡散しても半導体基板中に大き
く広がることなく、エミッタ拡散層、コレクタ拡散層、
ベースコンタクト層を形成することができる。さらに、
前述のような方法で多結晶シリコンを電極として凹部内
に埋め込む構造のため、マスク最小寸法でベース幅を形
成することができる。
Effects of the Invention As is clear from the above description, the present invention provides a semiconductor device in which an emitter, a collector, and a base region are each disposed laterally on the entire surface of a second conductivity type semiconductor substrate. The base and collector areas are
It has a recess whose cross-sectional shape is approximately rectangular, and polycrystalline silicon is embedded in the recess as an electrode,
The polycrystalline silicon in the recess in at least one of the emitter and collector regions does not extend over at least a surface region of the semiconductor substrate sandwiched between the recesses in the emitter and collector regions, The emitter and the collector regions have emitter and collector diffusion layers formed by diffusing a first conductivity type impurity into the semiconductor substrate from the polycrystalline silicon in the respective recesses, and the emitter and the collector regions In the opposing portions, the bonding surfaces of the diffusion layers of the emitter and the collector are substantially parallel to each other, and in the base region, impurities of the second conductivity type are diffused into the semiconductor substrate from the polycrystalline silicon in the recess. Since the structure has a base contact layer formed using a polycrystalline silicon, impurities are diffused from the polycrystalline silicon into the semiconductor substrate. Emitter diffusion layer, collector diffusion layer,
A base contact layer can be formed. moreover,
Since the structure is such that polycrystalline silicon is used as an electrode and is buried in the recess by the method described above, the base width can be formed using the minimum dimension of the mask.

従って、本発明は、以下のような効果を有する。Therefore, the present invention has the following effects.

まず第一は、エミッタ拡散層、コレクタ拡散層、ベース
コンタクト層が、半導体基板中に大きく広がることなく
形成できることにより、非常に高密度化に適し、またエ
ミッターベース間容量、コレクターベース間容量が小さ
くなり、高周波特性の向上にもつながる。さらにエミッ
タ拡散層とコレクタ拡散層が互いにほぼ平行であるので
対向面積を一層大きく取ることができ高い電流増幅率が
得られることである。第二は、マスク最小寸法でベース
幅を形成することができることにより、従来よりもベー
ス幅が薄くでき高い電流増幅率が得られると共に、高周
波特性の向上にもつながることである。
First of all, the emitter diffusion layer, collector diffusion layer, and base contact layer can be formed without spreading widely in the semiconductor substrate, making it suitable for extremely high density, and the emitter-base capacitance and collector-base capacitance are small. This also leads to improved high frequency characteristics. Furthermore, since the emitter diffusion layer and the collector diffusion layer are substantially parallel to each other, the opposing area can be further increased, and a high current amplification factor can be obtained. Second, since the base width can be formed with the minimum dimension of the mask, the base width can be made thinner than in the past, resulting in a higher current amplification factor and improved high frequency characteristics.

以上のように、本発明による実用的効果は太きい。As described above, the practical effects of the present invention are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の製造工程断面図、第2図は
従来例の半導体装置の断面構造図である。 1・・・第1導電型半導体基板、2・Φ・第2導電型半
導体領域、3ΦΦ・第2導電型半導体届、4・・・絶縁
膜、5−1・・・エミッタ拡散層、5−2・拳Φコレク
タ拡散ff、8−1φ・・エミッタ多結晶シリコン電極
、6−2・・・コレクタ多結晶シリコン電極、6−3・
・・ベース多結晶シリコン電極、7−1.7−2.7−
3・・・金属電極、8・・拳ベースコンタクト層。 代理人の氏名 弁理士 栗野重孝 はか1名据 Cす 城
FIG. 1 is a sectional view of the manufacturing process of an embodiment of the present invention, and FIG. 2 is a sectional structural view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...1st conductivity type semiconductor substrate, 2.Φ.2nd conductivity type semiconductor region, 3.PHI..2nd conductivity type semiconductor substrate, 4..Insulating film, 5-1..Emitter diffusion layer, 5- 2. Fist Φ Collector diffusion ff, 8-1φ... Emitter polycrystalline silicon electrode, 6-2... Collector polycrystalline silicon electrode, 6-3.
...Base polycrystalline silicon electrode, 7-1.7-2.7-
3... Metal electrode, 8... Fist base contact layer. Name of agent: Patent attorney Shigetaka Kurino

Claims (2)

【特許請求の範囲】[Claims] (1)第2導電型半導体基板の一主面上に、エミッタ、
コレクタ、ベース領域それぞれが、横方向に配置された
半導体装置において、前記エミッタ、ベース、コレクタ
領域がそれぞれ、その断面形状がほぼ長方形であるよう
な凹部を持ち、前記凹部内に多結晶シリコンが、電極と
して埋め込まれ、前記エミッタ、前記コレクタ領域の少
なくとも一方の領域の前記凹部内の多結晶シリコンが、
少なくとも前記エミッタと前記コレクタ領域の前記凹部
に挟まれた半導体基板表面領域上に延在していない構造
で、前記エミッタと前記コレクタ領域において、それぞ
れの凹部内の多結晶シリコンから第1導電型の不純物が
前記半導体基板内に拡散されて形成されたエミッタ、コ
レクタ拡散層を有し、前記エミッタと前記コレクタ領域
が対向している部分において、前記エミッタと前記コレ
クタの拡散層の接合面が互いにほぼ平行であり、前記ベ
ース領域において、凹部内の多結晶シリコンから第2導
電型の不純物が前記半導体基板内に拡散されて形成され
たベースコンタクト層を有していることを特徴とする半
導体装置。
(1) On one main surface of the second conductivity type semiconductor substrate, an emitter,
In a semiconductor device in which a collector region and a base region are arranged in a horizontal direction, each of the emitter region, the base region, and the collector region has a recessed portion whose cross section is approximately rectangular, and polycrystalline silicon is disposed within the recessed portion. Polycrystalline silicon embedded as an electrode in the recess in at least one of the emitter and collector regions,
At least a structure that does not extend over a surface region of the semiconductor substrate sandwiched between the recesses of the emitter and collector regions, and in the emitter and collector regions, a first conductivity type is formed from the polycrystalline silicon in the respective recesses. It has an emitter and a collector diffusion layer formed by diffusing impurities into the semiconductor substrate, and in a portion where the emitter and the collector region face each other, the bonding surfaces of the emitter and the collector diffusion layers are substantially mutual to each other. A semiconductor device comprising a base contact layer which is parallel to the semiconductor substrate and is formed by diffusing a second conductivity type impurity from polycrystalline silicon in the recess into the semiconductor substrate in the base region.
(2)第2導電型半導体基板の一主面にエミッタ、コレ
クタ、ベース領域となる凹部を、その断面形状がほぼ長
方形となるように同時に設ける工程と、前記凹部内に多
結晶シリコンを、電極として埋め込むが、前記エミッタ
、前記コレクタ領域の少なくとも一方の領域の前記凹部
内の多結晶シリコンが、少なくとも前記エミッタと前記
コレクタ領域の前記凹部に挟まれた半導体基板表面領域
上に延在しないように前記凹部内に多結晶シリコンを埋
め込む工程と、前記エミッタ領域と前記コレクタ領域の
凹部内の多結晶シリコンからそれぞれ第1導電型の不純
物を前記半導体基板へ拡散し、同時に前記エミッタ及び
前記コレクタ拡散層を形成するが、その場合前記エミッ
タと前記コレクタ領域が対向している部分において、前
記エミッタと前記コレクタの拡散層の接合面が互いにほ
ぼ平行であるように前記拡散層を形成する工程と、前記
ベース領域の凹部内の多結晶シリコンから前記半導体基
板に第2導電型の不純物を拡散して、ベースコンタクト
層を形成する工程とを少なくとも有する半導体装置の製
造方法。
(2) A step of simultaneously providing recesses to serve as emitter, collector, and base regions on one main surface of the second conductivity type semiconductor substrate so that the cross-sectional shape thereof is approximately rectangular, and forming polycrystalline silicon in the recesses to form electrodes The polycrystalline silicon in the recess in at least one of the emitter and collector regions does not extend over at least a surface region of the semiconductor substrate sandwiched between the recesses in the emitter and collector regions. burying polycrystalline silicon in the recess, diffusing impurities of a first conductivity type from the polycrystalline silicon in the emitter region and the collector region into the semiconductor substrate, and simultaneously burying the emitter and collector diffusion layers; forming the diffusion layer so that the bonding surfaces of the diffusion layers of the emitter and collector are substantially parallel to each other in a portion where the emitter and collector regions face each other; A method for manufacturing a semiconductor device, comprising at least the step of diffusing a second conductivity type impurity from polycrystalline silicon in a recessed portion of a base region into the semiconductor substrate to form a base contact layer.
JP27345688A 1988-10-28 1988-10-28 Semiconductor device and manufacture thereof Pending JPH02119229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27345688A JPH02119229A (en) 1988-10-28 1988-10-28 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27345688A JPH02119229A (en) 1988-10-28 1988-10-28 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH02119229A true JPH02119229A (en) 1990-05-07

Family

ID=17528167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27345688A Pending JPH02119229A (en) 1988-10-28 1988-10-28 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH02119229A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108133959A (en) * 2017-12-25 2018-06-08 深圳市晶特智造科技有限公司 Groove triode and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108133959A (en) * 2017-12-25 2018-06-08 深圳市晶特智造科技有限公司 Groove triode and preparation method thereof
CN108133959B (en) * 2017-12-25 2020-12-15 浙江昌新生物纤维股份有限公司 Groove triode and manufacturing method thereof

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