JPS6346583B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a high frequency, high power transistor.

In recent years, the characteristics of high-frequency, high-output transistors (hereinafter abbreviated as Tr) have been increasing in higher frequency bands,
High output is required. In order to satisfy this requirement, the emitter of the high-frequency, high-power transistor must be
The shape and spacing of each impurity region of the base and each electrode layer must be formed precisely and minutely. Therefore, if a self-alignment method is used to form each impurity region and each electrode layer, the problem of deviation from design dimensions due to mask alignment and processing in each PR process will be eliminated, which is advantageous. Furthermore, if the spacing between each electrode layer is determined in the vertical direction with respect to the semiconductor surface, the spacing between each impurity region can be designed to be very small, resulting in good high frequency characteristics.

As a conventional technology having such a structure, as a stepped electrode transistor, for example,
34485. This is a structure that has an inverted trapezoidal polycrystalline silicon layer on the emitter region, and the emitter region is determined from the position and size of the bottom of this inverted trapezoid, and the vertical direction between the bottom and the upper surface of the inverted trapezoid is The distance between the emitter region and the base contact is determined from the relative relationship with the projected position.

However, since the formation of each region depends on the shape of the inverted trapezoidal polycrystalline silicon, the height of the inverted trapezoid is inevitably restricted due to manufacturing technology limitations, and as a result, the height of the inverted trapezoid is inevitably limited, and as a result, the height of the inverted trapezoid is inevitably limited due to the limitations of manufacturing technology. There was a problem in that it was not possible to make the film thickness necessary for reliability as a high-frequency, high-output transistor. Especially highly reliable multilayer electrodes (Ti-Pt-Au, Ti-W-Au)
When using , this tendency became more pronounced.
Therefore, in conventional high-frequency, high-output transistors using this inverted trapezoidal structure, after forming electrode metal from the top surface,
Furthermore, a conductive path metal (shotting the emitter and base) is provided using the normal lift-off method.
By plating using this metal, the film thickness of the electrode fittings (Au, etc.) of the collector electrode part was raised to the desired thickness.

However, with this conventional manufacturing method, not only is the process complicated and long, but when Ti or Al, which is advantageous as a conductive path metal, is used, it tends to react with the electrode metal (Au) and form an alloy layer. Even after plating, the problem often occurred that the etching could not be removed, resulting in poor appearance.

The present invention has been developed in view of the above points, and is a stepped electrode transistor in which the emitter and base are shot with vapor-deposited electrode metal by processing only a part of the polycrystalline silicon layer on the emitter region into a trapezoidal shape. The purpose is to provide a new plating method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to better understand the present invention, an example of a method for manufacturing a transistor to which the present invention is applied will be described below in comparison with a conventional manufacturing method, with reference to the accompanying drawings.

The same reference numerals will be used in the drawings below.

Fig. 1 is a plan view showing an example of a Tr having an inverted trapezoidal emitter shape, and Fig. 2 shows a case in which a conventional manufacturing method is applied to the inverted trapezoidal emitter type Tr shown in Fig. 1. FIG. 2 is a sectional view taken along the direction of the arrow.

In FIG. 2, a semiconductor substrate 1 contains a base contact region 7 and an active base region 3 having a conductivity type opposite to that of the semiconductor substrate 1, and an impurity having the same conductivity type as the semiconductor substrate, and is processed into an inverted trapezoidal shape. An emitter region 5 is formed by introducing impurities from the polycrystalline silicon layer 4, the inverted trapezoidal part is further protected by an insulating layer 6, an electrode metal 8 is formed by vapor deposition from the vertical upper surface direction, and a photoresist is used. A plating layer 9 is provided by a normal lift method. However, with this manufacturing method, the process is not only complicated and long, but also when general Al or titanium is used as the plating conductive path metal 10, it reacts with the electrode metal (Au) during sputtering or vapor deposition, forming an alloy layer. Because it is easy to form, there was a problem that the conductive path metal could not be removed by etching even after plating was completed.

FIG. 3 is a plan view when the present invention is applied to an inverted trapezoidal emitter type Tr, and FIG.
FIG. 3 is a cross-sectional view taken along line B' and viewed in the direction of the arrow.

FIG. 5 to FIG. 8 show that the present invention is applied to a high-frequency transistor having an inverted trapezoidal emitter structure.
It is a sectional view taken along line B' and viewed in the direction of the arrow for each main process.

After forming an active base region 3, a polycrystalline silicon layer (dobos layer) 4 containing a large amount of impurities, a polysilicon layer 14 containing no impurities, and an insulating layer 13 on a semiconductor substrate 1 in the same manner as in the conventional manufacturing method, The insulating layer 13 is formed into an emitter electrode pattern using a photoresist 15 by photolithography (FIG. 5).

Thereafter, the exposed insulating layer 13 and polysilicon layer 14 are completely removed by ion milling or sputter etching, and then the dopos layer 4 is etched to about 1/2 of its thickness.
In this manufacturing method example, the dopos layer was removed by etching about 1/2 of the film thickness, but the etching thickness of this dopos layer was 0.
The above is sufficient as long as it is equal to or less than the initially formed film thickness. Next, after covering and protecting the emitter-base short circuit forming part with photoresist 16 using the usual photolithography method (6th
(Fig. 7), the exposed dopos layer 4 is removed by etching with a fluoro-nitric acid mixture, and then the photoresist 16 is removed (Fig. 7). By this wet etching, the cross-section of the dopos layer 4 using the photoresist 16 as an etching-resistant mask becomes trapezoidal 12, and the cross-sections of the dopos layer 4 using the insulating layer 13 as an etching-resistant mask and the polysilicon layer 14 are reversed. Trapezoid 1
Processed into 1.

Next, emitter region 5, insulating layer 6, and base contact region 7 are formed in the same manner as in the conventional manufacturing method, and after removing insulating layer 13 by etching, electrode metal 8 is deposited from the vertical upper surface (FIG. 8). When forming emitter region 5 by introducing impurities from dopos layer 4, polysilicon layer 14 is also doped with impurities. In this example, the vapor-deposited electrode metal 8 is Ti, Pt,
Au was continuously deposited to create a three-layer structure. This vapor-deposited metal 8 forms a trapezoidal portion 12 between the emitter and the base.
Since this is inevitably short-circuited through the process, Au plating 9 on the emitter electrode is performed using this (Fig. 4).
In some cases, Au may also be applied to certain areas on the base electrode.
You can also do some mitsuki. Next, a photoresist is applied to expose the short-circuited portion of the vapor-deposited metal (near the trapezoidal portion 12), and the short-circuited portion is removed to separate the emitter and base electrodes (not shown).

As can be seen from the above description of the manufacturing method example, in the Tr to which the present invention is applied, there is no need to provide a plating conductive bus metal (Ti or Al) unlike in the conventional manufacturing method, so the manufacturing process is simplified. Further, although the photolithography step for forming a new emitter-base shorting portion is increased, the manufacturing method is not difficult because it is only necessary to cover the stepped portion with photoresist. Furthermore, there is no need to provide a plating conductive bus metal, which has often occurred in the past. Defects in appearance due to the formation of an alloy layer between the plating conductive path metal and the electrode metal can also be completely eliminated.

In the above embodiment, a transistor was used, but a diode,
It goes without saying that the same can be done with IC.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of a transistor having a polycrystalline silicon layer with an inverted trapezoidal structure on the emitter region.
FIG. 2 is a cross-sectional view of the Tr shown in FIG. 1 taken along line AA' and viewed in the direction of the arrow. Fig. 3 is a plan view of the case where the present invention is applied to an inverted trapezoidal emitter type Tr, and Figs. It is a sectional view seen in the direction. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating layer, 3... Active base layer, 4... High concentration polycrystalline silicon layer (dopos layer),
5... Emitter layer, 6... Insulating layer, 7... Base contact layer, 8... Electrode metal layer, 9... Au plating layer, 1
0...Metal for plating conductive path, 11...Inverted trapezoidal part, 1
2... Trapezoidal part, 13... Insulating layer, 14... Polycrystalline silicon layer (polysilicon layer) not containing impurities, 15
...Photoresist layer, 16...EB short circuit forming part (photoresist layer).

Claims (1)

[Claims] 1. A step of selectively forming a base region on the surface of a semiconductor substrate of one conductivity type, a step of providing a polycrystalline silicon layer in contact with at least a portion of the base region, and an emitter electrode of the polycrystalline silicon layer. a step of making the polycrystalline silicon layer on the base electrode extraction portion of the base region thinner than the polycrystalline silicon layer on the emitter electrode formation portion by removing the portion other than the formation portion to a predetermined thickness; After covering and protecting the emitter-base short circuit formation portion on the layer, the polycrystalline silicon layer on the base electrode extraction portion is selectively removed, thereby removing the polycrystalline silicon layer that is not adjacent to the base electrode extraction portion. processing a part of the emitter electrode forming part into a trapezoidal shape, and processing an end of the emitter electrode forming part adjacent to the base electrode extraction part of the polycrystalline silicon layer into an inverted trapezoidal shape;
forming an emitter region in contact with the polycrystalline silicon in the base region, depositing an electrode metal from the vertical upper surface, and forming an emitter-base short circuit on the emitter electrode, the base electrode, and the trapezoidal portion; a step of plating at least the emitter electrode; and a step of removing the emitter-base short circuit to separate the emitter electrode and the base electrode. Method.