JPH06120234A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH06120234A
JPH06120234A JP26446892A JP26446892A JPH06120234A JP H06120234 A JPH06120234 A JP H06120234A JP 26446892 A JP26446892 A JP 26446892A JP 26446892 A JP26446892 A JP 26446892A JP H06120234 A JPH06120234 A JP H06120234A
Authority
JP
Japan
Prior art keywords
diffusion layer
emitter
base
semiconductor device
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26446892A
Other languages
Japanese (ja)
Inventor
Eigo Fuse
英悟 布施
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26446892A priority Critical patent/JPH06120234A/en
Publication of JPH06120234A publication Critical patent/JPH06120234A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent defective breakdown strength or short-circuit between a collector and an emitter, and obtain a semiconductor device excellent in high frequency characteristics by reducing base resistance. CONSTITUTION:Periheries of a base diffusion layer 2 of a bipolar transistor is surrounded with a high concentration P-type diffusion layer 4. In a photoresist process, defective breakdown strength or short-circuit failure between a collector and an emitter which failure is caused by alignment deviation or the like of a base diffusion layer 2 or an emitter contact hole 9 is prevented, and high frequency characteristics are improved by reducing base resistance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
バイポーラトランジスタの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a bipolar transistor.

【0002】[0002]

【従来の技術】従来のバイポーラトランジスタは、図3
(a),(b)に示すように、半導体基板上に、N型エ
ピタキシャル層1を形成し、N型エピタキシャル層上の
主表面に選択的に形成されたフィールド酸化膜10で区
画されたトランジスタ形成領域内に、P型のベース拡散
層2,N型のエミッタ拡散層3及びベース電極引き出し
のためのベース拡散層2に接続する高濃度P型拡散層4
Aを形成する。この高濃度P型拡散層4Aは一般的にベ
ース電極配線として用いられるアルミ配線とのコンタク
ト抵抗を下げる目的で形成されている。さらに、エミッ
タ電極7とエミッタ拡散層3を接続するため第1絶縁膜
5にエミッタコンタクト孔9を開孔し、このエミッタ電
極7にアルミ配線8が接続されている。
2. Description of the Related Art A conventional bipolar transistor is shown in FIG.
As shown in (a) and (b), a transistor in which an N type epitaxial layer 1 is formed on a semiconductor substrate and is partitioned by a field oxide film 10 selectively formed on the main surface of the N type epitaxial layer. A high-concentration P-type diffusion layer 4 connected to the P-type base diffusion layer 2, the N-type emitter diffusion layer 3, and the base diffusion layer 2 for drawing out the base electrode in the formation region.
Form A. The high-concentration P-type diffusion layer 4A is formed for the purpose of reducing the contact resistance with the aluminum wiring generally used as the base electrode wiring. Further, an emitter contact hole 9 is opened in the first insulating film 5 for connecting the emitter electrode 7 and the emitter diffusion layer 3, and an aluminum wiring 8 is connected to the emitter electrode 7.

【0003】[0003]

【発明が解決しようとする課題】この従来のバイポーラ
トランジスタの構造では、フォトレジスト工程の目ずれ
等によりエミッタコンタクト孔9及びベース拡散層3が
横方向にずれて形成された場合、図3(b)に示した横
方向の間隔t1 が狭くなり、トランジスタ特性のコレク
タ・エミッタ間の耐圧不足あるいはショートとなる場合
が多くなり、半導体装置の信頼性及び歩留りを低下させ
るという問題点があった。
In the structure of this conventional bipolar transistor, when the emitter contact hole 9 and the base diffusion layer 3 are formed laterally displaced due to misalignment of the photoresist process, etc., as shown in FIG. In this case, the lateral distance t 1 shown in FIG. 4) becomes narrow, and the collector-emitter breakdown voltage of the transistor characteristics often becomes insufficient or short-circuited, and there is a problem that the reliability and yield of the semiconductor device are reduced.

【0004】さらに、ベース拡散層2は高濃度P型拡散
層4Aに比べ約2桁低ドーズ量で形成されているため、
エミッタ拡散層3と高濃度P型拡散層4Aまでの距離t
2 が長くなると、ベース抵抗が大きくなり高周波特性に
悪影響を及ぼす場合が多かった。一般に定義されている
高周波遮断周波数fmax は、次式で表わされる。 fmax =(1/rb +1/rE )/(CE +CC ),た
だしrb :ベース抵抗,rE :エミッタ抵抗,CE :エ
ミッタ容量,CC :コレクタ容量である。従ってベース
抵抗rb が大きくなると、高周波遮断周波数が小さくな
る。
Further, since the base diffusion layer 2 is formed with a dose of about two orders of magnitude lower than that of the high concentration P type diffusion layer 4A,
Distance t between the emitter diffusion layer 3 and the high concentration P-type diffusion layer 4A
When 2 becomes long, the base resistance increases and often affects the high frequency characteristics. The commonly defined high frequency cutoff frequency f max is expressed by the following equation. f max = (1 / r b + 1 / r E ) / (C E + C C ), where r b is the base resistance, r E is the emitter resistance, C E is the emitter capacitance, and C C is the collector capacitance. Therefore, as the base resistance r b increases, the high frequency cutoff frequency decreases.

【0005】本発明の目的は、このようなトランジスタ
特性の低下を防止し、信頼性及び歩留りの向上した半導
体装置を提供することにある。
An object of the present invention is to provide a semiconductor device which prevents such deterioration of transistor characteristics and improves reliability and yield.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板主表面に形成されたコレクタ拡散層とベース
拡散層とエミッタ拡散層とを有する半導体装置におい
て、前記ベース拡散層はベース拡散層と同一型の不純物
でかつベース拡散層の不純物濃度より高い不純物濃度の
拡散層で囲まれているものである。
The semiconductor device of the present invention comprises:
In a semiconductor device having a collector diffusion layer, a base diffusion layer, and an emitter diffusion layer formed on a main surface of a semiconductor substrate, the base diffusion layer is of the same type as the base diffusion layer and has an impurity concentration higher than that of the base diffusion layer. It is surrounded by a diffusion layer of concentration.

【0007】[0007]

【実施例】以下本発明の実施例について図面を参照して
説明する。図1(a),(b)は本発明の第1の実施例
の平面図及びA−A線断面図である。
Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B are a plan view and a sectional view taken along the line AA of the first embodiment of the present invention.

【0008】図1(a),(b)において半導体基板上
にはN型エピタキシャル層1が形成されており、このエ
ピタキシャル層1に選択的に形成されたフィールド酸化
膜10で区画されたトランジスタ形成領域は、不純物添
加層で選択的に設けられたP型のベース拡散層2と、こ
のベース層2の周囲に設けられた高濃度P型拡散層4
と、ベース層2内に設けられたエミッタ拡散層3を有し
ている。そしてエミッタ配線引き出しのためエピタキシ
ャル層1上に設けられた第1絶縁膜5にエミッタコンタ
クト孔9を開孔しヒ素を添加した多結晶シリコンでエミ
ッタ電極7を形成している。尚エミッタ拡散層3はエミ
ッタ電極7の多結晶シリコンに添加されたヒ素の拡散を
利用して形成している。尚6は第2絶縁膜、8はアルミ
配線である。この高濃度P型拡散層4は、エミッタ電極
7を形成後この電極をマスクにセルフアラインでイオン
注入し形成しているため、特別のフォトレジスト工程は
不要である。
In FIGS. 1A and 1B, an N type epitaxial layer 1 is formed on a semiconductor substrate, and a transistor is formed which is partitioned by a field oxide film 10 selectively formed on the epitaxial layer 1. The region is a P-type base diffusion layer 2 selectively provided as an impurity-added layer, and a high-concentration P-type diffusion layer 4 provided around the base layer 2.
And an emitter diffusion layer 3 provided in the base layer 2. Then, an emitter contact hole 9 is opened in the first insulating film 5 provided on the epitaxial layer 1 to lead out the emitter wiring, and the emitter electrode 7 is formed of arsenic-added polycrystalline silicon. The emitter diffusion layer 3 is formed by utilizing the diffusion of arsenic added to the polycrystalline silicon of the emitter electrode 7. Reference numeral 6 is a second insulating film, and 8 is an aluminum wiring. The high-concentration P-type diffusion layer 4 is formed by self-aligned ion implantation using the emitter electrode 7 as a mask after forming the emitter electrode 7, so that no special photoresist process is required.

【0009】このように第1の実施例によれば、エミッ
タ拡散層3と高濃度P型拡散層4との横方向の距離はエ
ミッタ電極7の幅で決定されるため、従来のようにベー
ス拡散層2がずれてコレクタ・エミッタ間の耐圧不足あ
るいはショートが生じることはなくなる。
As described above, according to the first embodiment, the lateral distance between the emitter diffusion layer 3 and the high-concentration P-type diffusion layer 4 is determined by the width of the emitter electrode 7. The diffusion layer 2 will not be displaced and the short-circuit or short circuit between the collector and the emitter will not occur.

【0010】図2(a),(b)は本発明の第2の実施
例の平面図及びB−B線断面図である。
2 (a) and 2 (b) are a plan view and a sectional view taken along line BB of the second embodiment of the present invention.

【0011】この第2の実施例で、第1の実施例との大
きな構造上の相違は図1(b)の第1絶縁膜5をなく
し、エミッタ電極7Aを形成した後図2(b)に示した
ように、エミッタ電極7Aの側面に絶縁膜からなるサイ
ドウォール11を形成したことである。またエミッタコ
ンタクト孔を形成していないため、エミッタ拡散層3A
がエミッタ電極7Aとほぼ同等の幅になっている。従っ
て同一トランジスタ形成領域内で第1の実施例より高電
流型トランジスタが形成できる。
In the second embodiment, the major structural difference from the first embodiment is that the first insulating film 5 of FIG. 1 (b) is eliminated and the emitter electrode 7A is formed, and then FIG. 2 (b) is formed. As shown in, the side wall 11 made of an insulating film is formed on the side surface of the emitter electrode 7A. Since the emitter contact hole is not formed, the emitter diffusion layer 3A
Has almost the same width as the emitter electrode 7A. Therefore, a high current type transistor can be formed in the same transistor formation region as in the first embodiment.

【0012】さらにエミッタ拡散層3Aと高濃度P型拡
散層4との横方向の距離は、サイドウォール11の幅で
決まるため、第1の実施例よりも1.0〜1.5μm狭
くすることができる。このため、第1の実施例よりさら
に高周波特性に優れたトランジスタが得られる。
Further, the lateral distance between the emitter diffusion layer 3A and the high-concentration P-type diffusion layer 4 is determined by the width of the sidewall 11, so it should be narrower by 1.0 to 1.5 μm than in the first embodiment. You can Therefore, a transistor having higher high frequency characteristics than that of the first embodiment can be obtained.

【0013】[0013]

【発明の効果】以上説明した通り本発明は、ベース拡散
層の周囲を不純物濃度の高い拡散層で囲んでいるため、
コレクタ・エミッタ間での耐圧不足あるいはショート等
を防止できる。従って半導体装置の信頼性及び歩留りを
向上させることができる。またベース抵抗を小さくする
ことができるため、半導体装置の高周波特性を向上させ
ることができるという効果もある。
As described above, according to the present invention, the base diffusion layer is surrounded by the diffusion layer having a high impurity concentration.
Insufficient breakdown voltage or short circuit between collector and emitter can be prevented. Therefore, the reliability and yield of the semiconductor device can be improved. Further, since the base resistance can be reduced, there is an effect that the high frequency characteristics of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の平面図及び断面図。FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.

【図2】本発明の第2の実施例の平面図及び断面図。FIG. 2 is a plan view and a sectional view of a second embodiment of the present invention.

【図3】従来の半導体装置の一例の平面図及び断面図。3A and 3B are a plan view and a cross-sectional view of an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 N型エピタキシャル層 2 ベース拡散層 3,3A エミッタ拡散層 4,4A 高濃度P型拡散層 5 第1絶縁膜 6 第2絶縁膜 6A 絶縁膜 7,7A エミッタ電極 8 アルミ配線 9 エミッタコンタクト孔 10 フィールド酸化膜 11 サイドウォール 1 N-type epitaxial layer 2 Base diffusion layer 3, 3A Emitter diffusion layer 4, 4A High-concentration P-type diffusion layer 5 First insulating film 6 Second insulating film 6A Insulating film 7, 7A Emitter electrode 8 Aluminum wiring 9 Emitter contact hole 10 Field oxide film 11 Sidewall

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板主表面に形成されたコレクタ
拡散層とベース拡散層とエミッタ拡散層とを有する半導
体装置において、前記ベース拡散層はベース拡散層と同
一型の不純物でかつベース拡散層の不純物濃度より高い
不純物濃度の拡散層で囲まれていることを特徴とする半
導体装置。
1. A semiconductor device having a collector diffusion layer, a base diffusion layer, and an emitter diffusion layer formed on a main surface of a semiconductor substrate, wherein the base diffusion layer is an impurity of the same type as the base diffusion layer, A semiconductor device characterized by being surrounded by a diffusion layer having an impurity concentration higher than the impurity concentration.
JP26446892A 1992-10-02 1992-10-02 Semiconductor device Pending JPH06120234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26446892A JPH06120234A (en) 1992-10-02 1992-10-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26446892A JPH06120234A (en) 1992-10-02 1992-10-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06120234A true JPH06120234A (en) 1994-04-28

Family

ID=17403644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26446892A Pending JPH06120234A (en) 1992-10-02 1992-10-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06120234A (en)

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