JPS61202450A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase an effective inner logic cell region without increasing a chip area by forming a region of part of a peripheral cell in the same construction as the inner logic cell region. CONSTITUTION:A peripheral cell 12 is formed at partial region 30 above the cell 12 in the same cell as an inner logic cell 11. An inner logic cell 21 is disposed on the upper region of an unused peripheral cell 33a not used as an input/output buffer. Accordingly, a new inner logic block is disposed on a vacant cell region 61 in which the block 21 is moved. Thus, effective inner logic cell region is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit device with an improved cell configuration.

[Conventional technology]

Conventionally, the chip layout of a master slice type semiconductor integrated circuit device (hereinafter referred to as IC) is, for example, a second
As shown in the figure, it consists of an internal logic cell 11, a peripheral cell 12, and a wiring area 13], and the peripheral cell 12 was used only for the configuration of input/output covers and fur.[Problems to be Solved by the Invention] ] FIG. 3 shows a part of the above-mentioned Terrag layout in rough detail. In the same figure.

21 to 26 are internal logic processors, 31 and 32 are input/output covers and far processors, and 33 is an unused peripheral cell. These blocks are connected by a first metal wiring 41, a second metal wiring tJ42, and a peer hole 43, and the unused peripheral cells 33 forming the logic circuit have an input cover, a far outer cover, and an output cover. This cell is not even used for fur.

In master slice type ICs, such empty cells usually occur in most cases and exist on the chip as a part that does not function as a logic circuit, and there is a problem that the TEG area cannot be used effectively.Objective of the present invention. By solving the above problems, we have developed a semiconductor integrated circuit device with a new cell configuration that can reduce the unused area of peripheral cells in a master slice IC and effectively utilize the tear area. It is about providing.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention is a master slice type semiconductor integrated circuit device having internal logic cells arranged in an array and peripheral cells, in which a part of the peripheral cells are arranged in the same group logic cell column (or It consists of the same structure as (row).

〔Example〕

The present invention will be described below with reference to the drawings.

FIG. 1 is a layout diagram showing a part of a tip layout according to an embodiment of the present invention. In the figure, a part of the upper region 30 of the peripheral cell 12 is made up of the same cells as the internal logic cell 11, and the arrangement method thereof is also the same as that of the internal logic cell region.

The input/output buffer 7 is configured by all or some cells of the region 30 of the peripheral cell 12 and other regions.

However, the area 30 above the unused peripheral cells 33a, which is not used as an input/output cover or fur, is no different from the internal logic cell area, and an internal logic block can be placed therein. In this embodiment, the internal logic cell 21 is arranged in the area above the unused peripheral cell 33a. Therefore, the empty cell area 61 of the internal logic block 21 is moved.
A new internal logic processor can be placed.

Furthermore, it is clear that even in the peripheral cells used as the input/output buffer blocks 31a and 32a, internal logic blocks can be placed in the unused areas 51 and 52 of the area 30 in the same way as the internal logic cells.

〔Effect of the invention〕

As described above, in the semiconductor integrated circuit device of the present invention, by making a part of the peripheral cell have the same configuration as the internal logic cell area, the effective internal logic cell area can be reduced without increasing the chip area. It has the effect of expanding the

[Brief explanation of drawings]

Fig. 1 is a layout diagram showing a part of a tear gray act according to an embodiment of the present invention, Fig. 2 is a lay act diagram showing a tip layout of a conventional example, and Fig. 3 is a partial detailed view of Fig. 2. . 11... Internal logic cell, 12... Peripheral cell. 13...Wiring area %21-26...Internal logic pro, ri, 30...Part of peripheral cell area, 31° metal wiring, 42... ...Second metal wiring, 43...Pier hole, 51.52...
・Unused area, 61...Empty cell area 0 il: 4fsf storage space J 31, 32tt
: Input/output cover ゛°7 UP'' mouth/tsuk t2: Round return 7l to 21-2: Ka number l Kurari block 13
2nd side line #It 51, 52: water shortage use shiyuukunken 1 diagram / 3 slave leaning castle

Claims (1)

[Claims] In a master slice type semiconductor integrated circuit device having internal logic cells arranged in an array and peripheral cells, some of the peripheral cells have the same configuration as the internal logic cell columns (or rows). A semiconductor integrated circuit device characterized by: